August 2023 - flashrom - mail.coreboot.org

RDID Values Constantly Changing
by Ryne Everett April 2, 2024

April 2, 2024

Hello group, I'm attempting to flash a W25Q64FW with a CH341A. Despite this chip's RDID being supported (under "W25Q64.W"), flashrom identifies it as an "unknown SPI chip (RDID)" which I presume explains the "status NOT WORKING for operations: PROBE READ ERASE WRITE". Upon further inspection with '-VV' I see that id1 and id2 are not only wrong -- they're different every time I run flashrom! What could cause this? Thanks, Ryne

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flashrom meeting notes 31.08.2023
by Anastasia Klimchuk Aug. 31, 2023

Aug. 31, 2023

# 31th August 2023, 6.00-7.00am UTC+0 Attendees: Stefan, Alex, Anastasia ## Decision summary * not much ## Agenda * Who is using libpayload, which state it is in, how to test it before release? * write a post to the mailing list * see how it goes. if no one responds, can we at least try to compile it * Libflashrom versioning? * [https://ticket.coreboot.org/issues/381](https://ticket.coreboot.org/issues/… * probably can keep it as is for 1.4 -- Anastasia.

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Support for M50FLW080A
by Javier Bizcocho Aug. 26, 2023

Aug. 26, 2023

Hello guys, I'm trying to flash a modded bios on my motherboard. The computer is a Dell SC1435 and the flash chip in question "M50FLW080A" is supported by the tool already, but just partially. It looks like it can read the bios, but when reading or erasing it always fails (and every now and then it even forces my PC to reboot). My server is running FreeBSD 13.1, but I've also tried with Ubuntu (same result). Even though it fails to erase / write the chip was never altered at all, so I wonder if there is any kind of protection on it. Is there any logs that I can extract from the tool itself? I'd like to avoid the need to de-soldering the chip in order to flash it :). Any thoughts? Thank you in advance, Javi.

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dev feature enabled: unresolved comments block submit
by Anastasia Klimchuk Aug. 18, 2023

Aug. 18, 2023

Hello everyone, An announcement to everyone who is doing (or planning to do) any flashrom development. Since today, we are enabling the feature in Gerrit which blocks patch submit until all comments are resolved. You can see it in Gerrit if you open any patch, in the top-left section, "All-Comments-Resolved" label. If all the comments are resolved, the label is marked with a green checkbox. If there are unresolved comments, the label says "No votes" and submit is blocked. Thanks heaps to Patrick for helping to set this up! -- Anastasia.

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UNKNOWN FLASH CHIP
by Bolivar Peralta Aug. 17, 2023

Aug. 17, 2023

HI, thanks for the support, im sending you the output of the instruction for unknown chip

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flashrom meeting notes 17.08.2023
by Anastasia Klimchuk Aug. 17, 2023

Aug. 17, 2023

# 17th August 2023, 6.00-7.00am UTC+0 Attendees: Joursoir, Stefan, Anastasia ## Decision summary * logo files will be copied from flashrom-media to flashrom repo (into doc/ to display on website) * enable Gerrit feature to not submit with unresolved comments ## Agenda * [aklm] is it okay to copy the logo from one repo to another and add it to new website? Any licensing considerations? * copy the whole logo directory from media repository to docs * include svg in color on the page * licence is CC BY-ND 4.0 [https://github.com/flashrom/flashrom-media/blob/master/logo/COPYING](https:… so all good * What is the normal release process? what do we do for v1.4? * when all that is needed for rc1 is ready, put the tag v1.4_rc1 on master * then freeze the master for new features for 1 month, announce on mailing list * code reviews can continue, just not merging * do the testing * fix bugs if discovered, put v1.4_rc2, .... rcN * at the end of 1 month (hopefully bugs are fixed), put v1.4 on master, and then branch v1.4 * and then unfreeze, and merge everything that was waiting * [aklm] we need more people to subscribe to flashchips.c. I did already. We have contributors adding chips, and marking chips as tested, and they may not know whom to add as reviewer. [https://review.coreboot.org/q/status:open+project:flashrom+flashchips](http… * like this [https://review.coreboot.org/c/flashrom/+/75895](https://review.coreboot.org… * * let's add gerrit feature "do not submit with unresolved comments". it makes life easier for people who submit patches. * yes, lets add this feature * Joursoir: get a warning (do NOT restrict) if 24 hours have not passed. Is it possible? -- Anastasia.

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Re: ISSI Flash parts request to be added
by Johnny Chien Aug. 15, 2023

Aug. 15, 2023

Hi Everyone, The links provided to us are no longer working. Please help advise if there were new links setup or it this is a temporary issue and we should check back again. Johnny Chien Integrated Silicon Solution, Inc. Phone: 408.969.4647 Mobile: 408.786.8210 Fax: 408.969.4747 Email: Jchien(a)issi.com<mailto:Jchien@issi.com> Follow us on Twitter Hi Johnny, I couldn't connect the link, https://www.flashrom.org/Development_Guidelines#Adding/reviewing_a_new_flas… with the error below. Maybe the link was changed. Also the links below. [cid:image002.png@01D9C60E.013F0790] To send a patch you need to follow the guidelines here https://www.flashrom.org/Development_Guidelines#Patch_submission --> with the same error above. In addition, read specifically the section about adding a new chip https://www.flashrom.org/Development_Guidelines#Adding/reviewing_a_new_flas… --> with the same error above. One more document is about building flashrom from source https://doc.flashrom.org/dev_guide/building_from_source.html --> with the message below (unsupported protocol). [cid:image003.png@01D9C60E.013F0790] Can you please get the latest information about the links above through your contact in FalshRom? From: Peter Marheine <pmarheine(a)chromium.org<mailto:pmarheine@chromium.org>> Sent: Thursday, May 25, 2023 5:50 PM To: Johnny Chien <jchien(a)issi.com<mailto:jchien@issi.com>> Cc: flashrom(a)flashrom.org<mailto:flashrom@flashrom.org> Subject: Re: [flashrom] ISSI Flash parts request to be added The tips at https://www.flashrom.org/Development_Guidelines#Adding/reviewing_a_new_flas… will probably help you get started; if the chips you want to add support for are similar to already-supported chips it should be easy to add the new ones, but as long as they don't have any very unusual behavior there shouldn't be anything difficult about it. On Tue, May 23, 2023 at 11:53 AM Johnny Chien <jchien(a)issi.com<mailto:jchien@issi.com>> wrote: Hi FlashROM, We have a customer who pointed us to your organization. They asked if we could get more of our SPI NOR flash supported. Do you have a contact or person who would be able to guide us in this activity? We see the following parts supported here: [cid:image004.png@01D9C60E.013F0790] Johnny Chien Integrated Silicon Solution, Inc. Phone: 408.969.4647<tel:(408)%20969-4647> Mobile: 408.786.8210<tel:(408)%20786-8210> Fax: 408.969.4747<tel:(408)%20969-4747> Email: Jchien(a)issi.com<mailto:Jchien@issi.com> Follow us on Twitter _______________________________________________ flashrom mailing list -- flashrom(a)flashrom.org<mailto:flashrom@flashrom.org> To unsubscribe send an email to flashrom-leave(a)flashrom.org<mailto:flashrom-leave@flashrom.org> ________________________________ This email has been scanned for spam and viruses. Click here<https://securemail.cloud-protect.net/index01.php?mod_id=11&mod_option=logit…> to report this email as spam.

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Missing chip definition for ZD25WQ80Y
by a.b.c＠ntlworld.com Aug. 12, 2023

Aug. 12, 2023

ZD25WQ80Y Hope this info is of use

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Re: HP 11 G5 EE - WP disable failure
by Peter Marheine Aug. 9, 2023

Aug. 9, 2023

You don't need to cut any tracks, and that might not even do what you want because there probably isn't a pull-up or -down on the WP signal so it would be left floating in an indeterminate state. It looks like your Meep uses battery presence for WP, so disconnecting the battery should be all you need to do in order to temporarily disable hardware write protection. On Thu, Aug 10, 2023 at 11:16 AM E239 76BF <e23976bf(a)gmail.com> wrote: > I think the apparent thin link might be on the other side of the board. I > need to extract the board to confirm this, cut it and try again. > I'm a hardware tech with 40 yrs experience, so no issue. Just > unfamiliar with ChromeOS. > Need to remove the board. But it's the only IT platform I have. > Learned ChromeOS, Time to go back to linux. > > > On Thu, 10 Aug 2023 at 13:01, Peter Marheine <pmarheine(a)chromium.org> > wrote: > >> > Note: hardware status register protection is enabled. The chip's WP# >> pin must be set to an inactive voltage level to be able to change the WP >> settings. >> >> You need to disable hardware write protect: >> https://chromium.googlesource.com/chromiumos/docs/+/master/write_protection… >> >> On Tue, Aug 8, 2023 at 1:02 PM E239 76BF <e23976bf(a)gmail.com> wrote: >> >>> Glenn in Wellington, New Zealand >>> I know little about ChromeOS, but am moderately comfortable with Linux. >>> Got this machine two months ago (because I lost all my gear in a big >>> fire 11 weeks ago) and having learned ChromeOS, I'm now ready to return to >>> the comfort of a linux environment. >>> >>> Verbose output : >>> >>> # flashrom --wp-disable -V >>> flashrom 68022911 on Linux 4.14.313-20323-gc32c2d54e434 (x86_64) >>> flashrom is free software, get the source code at https://flashrom.org >>> >>> Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). >>> flashrom was built with LLVM Clang 16.0.0 >>> (/var/tmp/portage/sys-devel/llvm-16.0_pre484197_p20230405-r7/work/llvm-16.0_pre484197_p20230405/clang >>> 2916b99182752b1aece8cc4479d8d6a20b5e02da), little endian >>> Command line (2 args): flashrom --wp-disable -V >>> Using default programmer "internal" with arguments "". >>> Acquiring lock (timeout=180 sec)... >>> Opened file lock "/run/lock/firmware_utility_lock" >>> Lock acquired. >>> Initializing internal programmer >>> /sys/class/mtd/mtd0 does not exist >>> Found candidate at: 00000500-00000528 >>> Found coreboot table at 0x00000500. >>> Found candidate at: 00000000-000005cc >>> Found coreboot table at 0x00000000. >>> coreboot table found at 0x79b2a000. >>> coreboot header(24) checksum: a42a table(1460) checksum: c446 entries: 45 >>> Vendor ID: Google, part ID: Meep >>> Using Internal DMI decoder. >>> DMI string chassis-type: "Laptop" >>> Laptop detected via DMI. >>> DMI string system-manufacturer: "HP" >>> DMI string system-product-name: "Meep" >>> DMI string system-version: "rev7" >>> DMI string baseboard-manufacturer: "HP" >>> DMI string baseboard-product-name: "Meep" >>> DMI string baseboard-version: "rev7" >>> Found chipset "Intel Gemini Lake" with PCI ID 8086:3197. >>> This chipset is marked as untested. If you are using an up-to-date >>> version >>> of flashrom *and* were (not) able to successfully update your firmware >>> with it, >>> then please email a report to flashrom(a)flashrom.org including a verbose >>> (-V) log. >>> Thank you! >>> Enabling flash write... BIOS_SPI_BC = 0x9: BIOS Interface Lock-Down: >>> disabled, Boot BIOS Straps: 0x0 (SPI) >>> Top Swap: not enabled >>> SPI Read Configuration: prefetching enabled, caching enabled, >>> BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled >>> SPIBAR = 0x00007bd11ce10000 (phys = 0xc1121000) >>> 0x04: 0x6000 (HSFS) >>> HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=0, SCIP=0, FDOPSS=1, FDV=1, >>> FLOCKDN=0 >>> Programming OPCODES... done >>> 0x06: 0x020c (HSFC) >>> HSFC: FGO=0, FCYCLE=2, FDBC=2, SME=0 >>> 0x0c: 0x00000000 (DLOCK) >>> DLOCK: BMWAG_LOCKDN=0, BMRAG_LOCKDN=0, SBMWAG_LOCKDN=0, SBMRAG_LOCKDN=0, >>> PR0_LOCKDN=0, PR1_LOCKDN=0, PR2_LOCKDN=0, PR3_LOCKDN=0, >>> PR4_LOCKDN=0, >>> SSEQ_LOCKDN=0 >>> 0x50: 0x000042c3 (FRAP) >>> BMWAG 0x00, BMRAG 0x00, BRWA 0x42, BRRA 0xc3 >>> 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) >>> is read-only. >>> 0x58: 0x0f7e0001 FREG1: BIOS region (0x00001000-0x00f7efff) is >>> read-write. >>> 0x68: 0x0fff0f7f FREG5: Device Expansion region (0x00f7f000-0x00ffffff) >>> is locked. >>> 0x7C: 0x7fff7fff FREG10: unknown region (0x07fff000-0x07ffffff) has >>> unknown permissions. >>> 0x80: 0x7fff7fff FREG11: unknown region (0x07fff000-0x07ffffff) has >>> unknown permissions. >>> 0xE0: 0x7fff7fff FREG12: unknown region (0x07fff000-0x07ffffff) has >>> unknown permissions. >>> 0xE4: 0x7fff7fff FREG13: unknown region (0x07fff000-0x07ffffff) has >>> unknown permissions. >>> 0xE8: 0x7fff7fff FREG14: unknown region (0x07fff000-0x07ffffff) has >>> unknown permissions. >>> 0xEC: 0x7fff7fff FREG15: unknown region (0x07fff000-0x07ffffff) has >>> unknown permissions. >>> Not all flash regions are freely accessible by flashrom. This is most >>> likely >>> due to an active ME. Please see https://flashrom.org/ME for details. >>> At least some flash regions are read protected. You have to use a flash >>> layout and include only accessible regions. For write operations, you'll >>> additionally need the --noverify-all switch. See manpage for more >>> details. >>> 0xa0: 0xc0 (SSFS) >>> SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 >>> 0xa1: 0xfe0000 (SSFC) >>> SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=6 >>> 0xa4: 0x5006 (PREOP) >>> 0xa6: 0x463b (OPTYPE) >>> 0xa8: 0x05200302 (OPMENU) >>> 0xac: 0xc79f0190 (OPMENU+4) >>> 0xc4: 0xb1d82024 (LVSCC) >>> LVSCC: BES=0x0, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 >>> 0xc8: 0x00002000 (UVSCC) >>> UVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x20 >>> Enabling hardware sequencing by default for >>> Apollo/Gemini/Jasper/Elkhart/Meteor Lake. >>> OK. >>> The following protocols are supported: Programmer-specific. >>> Probing for Programmer Opaque flash chip, 0 kB: Hardware sequencing >>> reports 1 attached SPI flash chip with a density of 16384 kB. >>> HSFC: FGO=1, FCYCLE=2, FDBC=2, SME=0 >>> Chip identified: GD25LQ128C/GD25LQ128D/GD25LQ128E >>> Added layout entry 00000000 - 00ffffff named complete flash >>> Found GigaDevice flash chip "GD25LQ128C/GD25LQ128D/GD25LQ128E" (16384 >>> kB, Programmer-specific) on internal. >>> Found GigaDevice flash chip "GD25LQ128C/GD25LQ128D/GD25LQ128E" (16384 >>> kB, Programmer-specific). >>> This chip may contain one-time programmable memory. flashrom cannot read >>> and may never be able to write it, hence it may not be able to completely >>> clone the contents of this chip (see man page for details). >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> ich_hwseq_read_status: only supports STATUS1 >>> wp_read_register: read from register 2 not is supported by programmer, >>> writeprotect operations will assume it contains 0x00. >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> ich_hwseq_read_status: only supports STATUS1 >>> wp_read_register: read from register 2 not is supported by programmer, >>> writeprotect operations will assume it contains 0x00. >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> ich_hwseq_read_status: only supports STATUS1 >>> wp_read_register: read from register 2 not is supported by programmer, >>> writeprotect operations will assume it contains 0x00. >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> ich_hwseq_read_status: only supports STATUS1 >>> wp_read_register: read from register 2 not is supported by programmer, >>> writeprotect operations will assume it contains 0x00. >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> ich_hwseq_read_status: only supports STATUS1 >>> wp_read_register: read from register 2 not is supported by programmer, >>> writeprotect operations will assume it contains 0x00. >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> ich_hwseq_read_status: only supports STATUS1 >>> wp_read_register: read from register 2 not is supported by programmer, >>> writeprotect operations will assume it contains 0x00. >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> Writing status register >>> HSFC: FGO=1, FCYCLE=3, FDBC=0, SME=0 >>> ich_hwseq_read_status: only supports STATUS1 >>> wp_read_register: read from register 2 not is supported by programmer, >>> writeprotect operations will assume it contains 0x00. >>> Reading Status register >>> HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 >>> write_wp_bits: wp_verify failed: reg:1 actual:0xb4 expected:0x34 >>> ich_hwseq_read_status: only supports STATUS1 >>> wp_read_register: read from register 2 not is supported by programmer, >>> writeprotect operations will assume it contains 0x00. >>> Failed to apply new WP settings: unexpected WP configuration read back >>> from chip >>> Note: hardware status register protection is enabled. The chip's WP# pin >>> must be set to an inactive voltage level to be able to change the WP >>> settings. >>> Restoring MMIO space at 0x7bd11ce10084 >>> Restoring MMIO space at 0x7bd11ce100ac >>> Restoring MMIO space at 0x7bd11ce100a8 >>> Restoring MMIO space at 0x7bd11ce100a6 >>> Restoring MMIO space at 0x7bd11ce100a4 >>> _______________________________________________ >>> flashrom mailing list -- flashrom(a)flashrom.org >>> To unsubscribe send an email to flashrom-leave(a)flashrom.org >>> >>

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HP 11 G5 EE - WP disable failure
by E239 76BF Aug. 9, 2023

Aug. 9, 2023

Glenn in Wellington, New Zealand I know little about ChromeOS, but am moderately comfortable with Linux. Got this machine two months ago (because I lost all my gear in a big fire 11 weeks ago) and having learned ChromeOS, I'm now ready to return to the comfort of a linux environment. Verbose output : # flashrom --wp-disable -V flashrom 68022911 on Linux 4.14.313-20323-gc32c2d54e434 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). flashrom was built with LLVM Clang 16.0.0 (/var/tmp/portage/sys-devel/llvm-16.0_pre484197_p20230405-r7/work/llvm-16.0_pre484197_p20230405/clang 2916b99182752b1aece8cc4479d8d6a20b5e02da), little endian Command line (2 args): flashrom --wp-disable -V Using default programmer "internal" with arguments "". Acquiring lock (timeout=180 sec)... Opened file lock "/run/lock/firmware_utility_lock" Lock acquired. Initializing internal programmer /sys/class/mtd/mtd0 does not exist Found candidate at: 00000500-00000528 Found coreboot table at 0x00000500. Found candidate at: 00000000-000005cc Found coreboot table at 0x00000000. coreboot table found at 0x79b2a000. coreboot header(24) checksum: a42a table(1460) checksum: c446 entries: 45 Vendor ID: Google, part ID: Meep Using Internal DMI decoder. DMI string chassis-type: "Laptop" Laptop detected via DMI. DMI string system-manufacturer: "HP" DMI string system-product-name: "Meep" DMI string system-version: "rev7" DMI string baseboard-manufacturer: "HP" DMI string baseboard-product-name: "Meep" DMI string baseboard-version: "rev7" Found chipset "Intel Gemini Lake" with PCI ID 8086:3197. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... BIOS_SPI_BC = 0x9: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x0 (SPI) Top Swap: not enabled SPI Read Configuration: prefetching enabled, caching enabled, BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled SPIBAR = 0x00007bd11ce10000 (phys = 0xc1121000) 0x04: 0x6000 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=0, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0 Programming OPCODES... done 0x06: 0x020c (HSFC) HSFC: FGO=0, FCYCLE=2, FDBC=2, SME=0 0x0c: 0x00000000 (DLOCK) DLOCK: BMWAG_LOCKDN=0, BMRAG_LOCKDN=0, SBMWAG_LOCKDN=0, SBMRAG_LOCKDN=0, PR0_LOCKDN=0, PR1_LOCKDN=0, PR2_LOCKDN=0, PR3_LOCKDN=0, PR4_LOCKDN=0, SSEQ_LOCKDN=0 0x50: 0x000042c3 (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x42, BRRA 0xc3 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x0f7e0001 FREG1: BIOS region (0x00001000-0x00f7efff) is read-write. 0x68: 0x0fff0f7f FREG5: Device Expansion region (0x00f7f000-0x00ffffff) is locked. 0x7C: 0x7fff7fff FREG10: unknown region (0x07fff000-0x07ffffff) has unknown permissions. 0x80: 0x7fff7fff FREG11: unknown region (0x07fff000-0x07ffffff) has unknown permissions. 0xE0: 0x7fff7fff FREG12: unknown region (0x07fff000-0x07ffffff) has unknown permissions. 0xE4: 0x7fff7fff FREG13: unknown region (0x07fff000-0x07ffffff) has unknown permissions. 0xE8: 0x7fff7fff FREG14: unknown region (0x07fff000-0x07ffffff) has unknown permissions. 0xEC: 0x7fff7fff FREG15: unknown region (0x07fff000-0x07ffffff) has unknown permissions. Not all flash regions are freely accessible by flashrom. This is most likely due to an active ME. Please see https://flashrom.org/ME for details. At least some flash regions are read protected. You have to use a flash layout and include only accessible regions. For write operations, you'll additionally need the --noverify-all switch. See manpage for more details. 0xa0: 0xc0 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0xa1: 0xfe0000 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=6 0xa4: 0x5006 (PREOP) 0xa6: 0x463b (OPTYPE) 0xa8: 0x05200302 (OPMENU) 0xac: 0xc79f0190 (OPMENU+4) 0xc4: 0xb1d82024 (LVSCC) LVSCC: BES=0x0, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xc8: 0x00002000 (UVSCC) UVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x20 Enabling hardware sequencing by default for Apollo/Gemini/Jasper/Elkhart/Meteor Lake. OK. The following protocols are supported: Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Hardware sequencing reports 1 attached SPI flash chip with a density of 16384 kB. HSFC: FGO=1, FCYCLE=2, FDBC=2, SME=0 Chip identified: GD25LQ128C/GD25LQ128D/GD25LQ128E Added layout entry 00000000 - 00ffffff named complete flash Found GigaDevice flash chip "GD25LQ128C/GD25LQ128D/GD25LQ128E" (16384 kB, Programmer-specific) on internal. Found GigaDevice flash chip "GD25LQ128C/GD25LQ128D/GD25LQ128E" (16384 kB, Programmer-specific). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 Writing status register HSFC: FGO=1, FCYCLE=3, FDBC=0, SME=0 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Reading Status register HSFC: FGO=1, FCYCLE=0, FDBC=0, SME=0 write_wp_bits: wp_verify failed: reg:1 actual:0xb4 expected:0x34 ich_hwseq_read_status: only supports STATUS1 wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. Failed to apply new WP settings: unexpected WP configuration read back from chip Note: hardware status register protection is enabled. The chip's WP# pin must be set to an inactive voltage level to be able to change the WP settings. Restoring MMIO space at 0x7bd11ce10084 Restoring MMIO space at 0x7bd11ce100ac Restoring MMIO space at 0x7bd11ce100a8 Restoring MMIO space at 0x7bd11ce100a6 Restoring MMIO space at 0x7bd11ce100a4

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