January 2025 - flashrom - mail.coreboot.org

HP 11MK G9EE - M44236-001 - "W25Q64JW...M"
by Tim Tech Oct. 20, 2025

Oct. 20, 2025

Hello, attached are two text documents: output from --wp-disable and output from erase/write - let me know if any other information is needed. Chip in question is "W25Q64JW...M" Thanks, Tim

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Verification after write vs erase operations
by Anastasia Klimchuk Aug. 10, 2025

Aug. 10, 2025

Hello everyone, I want to bring into discussion a topic of verification of chip content which is performed after write or erase operations. Also for context prior discussion in this ticket: https://ticket.coreboot.org/issues/520 Currently we have a flag `-n` or `dont_verify_it` which is false by default. What the flag is doing is deciding whether verification needs to be performed after writing. The flag is false by default, so by default verification is happening after writing (which makes sense). Now the flag is only controlling write operation, and has no effect on erase operation. So for erase, the flag is ignored and verification is performed always. Just for context, it has always been like this. So for write operation we have a power option to say "ignore verification", and since it's false by default, the idea is, if you set it true then you know what you are doing. There is no such option for erase which seems a bit unfair. The two potential options to introduce equivalent option for erase are: 1) Add new flag `dont_verify_erase` (or some similar name) As a support for this option, it does not affect any existing use cases/scripts, and can be added any time. 2) Add coverage for erase operation under existing flag `-n` or `dont_verify_it` As a support for this option, erase operation can be seen as a variant of writing, since it does modify content of the chip, and so the fact it's not covered by the existing flag can be treated as a bug. What do people think about it? -- Anastasia.

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probing logic in command line vs libflashrom
by Anastasia Klimchuk Jan. 27, 2025

Jan. 27, 2025

Hello everyone, It turns out, flashrom has two different code paths for probing from command line vs probing with libflashrom. I think the logic should be the same, so as a goal I want to understand which approach is correct and use the same in both places. Have one piece of code and call it in two places. What is the difference: Command line keeps probing until the end of flashchips array, and as a result all matches will be found (no matter how many of them are). Currently code is on these lines: https://github.com/flashrom/flashrom/blob/main/cli_classic.c#L1211 Libflashrom only does probing twice, so at most two matches will be found. Currently code is on these lines: https://github.com/flashrom/flashrom/blob/main/libflashrom.c#L250 These two paths were initially introduced like this (>14 and >7yr ago). To me, command line's approach makes sense - because why stop at two matches? What if there are three matching chip definitions, and #3 is actually what the user has? So I am interested in what people think. A context how did this come up: I started working towards giving SFDP-detection more priority and this involves updating the probing logic, and that's how I came to this. -- Anastasia.

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HP Compaq 8300 Elite - NVMe BIOS Update Error
by Manuel del Rey Carral Jan. 23, 2025

Jan. 23, 2025

Dear flashroom.org friends. I am the owner of a HP Compact 8300 Elite Microtower and I tryed to follow the instructions of Paul Murana below, to modify the BIOS of my PC so that it allows the Start from a NVMe SSD. https://tachytelic.net/2022/01/hp-compaq-8300-nvme/ [https://tachytelic.net/wp-content/uploads/HP-Compaq-8300-Elite-NVMe.png]<https://tachytelic.net/2022/01/hp-compaq-8300-nvme/> Install and boot from an NVMe SSD on a HP Compaq Elite 8300 SFF - Tachytelic.net<https://tachytelic.net/2022/01/hp-compaq-8300-nvme/> Hola, intento implementar esto en un HP Z230 SFF, de momento no lo he probado, solo he encontrado las guías para poder hacerlo. Os adjunto 3 enlaces sobre como instalar NVMe M.2 pcie, reprogramando la bios por software (1 y 2) o, alternativamente, mediante un simple arranque alternativo del bios (3). tachytelic.net All good, but I've got an error in the very last step: flashing the corrected bin file (nvme.bin) . The error is: Error: Unknown chip 'MT25Q128' specified. The computer remainis ok, but the corrected BIOS could not be flashed. Any ideas of what migh have gone wrong? I previosly updated the BIOS to the version K01 v03 08 and installed a jumper cap into the FDO. You can find attached the outpot of the terminal log and below the Specs of my PC. I want to take the chance to give a big thanks to Pauli for his work and sharing his knowledge, and to you for yor kind sppport. Best Regards, Manuel dRC [cid:af5e4dfd-b870-4d4d-b9e7-c1a682be500f]

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fbsd 14.1, flashrom 1.3.0_3 (fbsd pkg)
by Kurt Jaeger Jan. 22, 2025

Jan. 22, 2025

Hi! flashrom-1.3.0_3 on FreeBSD 14.1 for pcengines APU1 seems to work with this command: flashrom -w apu1_v4.17.0.3.rom -c MX25L1605 -p internal:boardmismatch=force output: flashrom v1.3.0 on FreeBSD 14.1-RELEASE-p5 (amd64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 4, resolution: 70ns). coreboot table found at 0xdffdf000. Found chipset "AMD SB7x0/SB8x0/SB9x0". Enabling flash write... OK. Found Macronix flash chip "MX25L1605" (2048 kB, SPI) mapped at physical address 0x00000000ffe00000. === This flash part has status UNTESTED for operations: WP The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash chip. Please include the flashrom log file for all operations you tested (see the man page for details), and mention which mainboard or programmer you tested in the subject line. Thanks for your help! This coreboot image (PC Engines:apu1) does not appear to be correct for the detected mainboard (PC Engines:APU). Proceeding anyway because user forced us to. Reading old flash chip contents... done. Erasing and writing flash chip... FAILED at 0x00001000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x0000ffff: 0xe6f4 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. Erase/write done. Verifying flash... VERIFIED. But it needs a power-cycle 8-( -- MfG/Best regards, Kurt Jaeger Now what ? Dr.-Ing. Nepustil & Co. GmbH fon +49 7123 93006-0 pi(a)nepustil.net Rathausstr. 3 mob +49 171 3101372 72658 Bempflingen

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Bugreport: ASUS PRIME X370-A "internal" programmer, Flash not detected
by Markus Rudolf Jan. 9, 2025

Jan. 9, 2025

Hi, I have an ASUS PRIME X370-A and wanted to make a raw flash image of the BIOS chip, to no avail: root@ubuntu:~# flashrom -p internal flashrom unknown on Linux 6.8.0-41-generic (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Found chipset "AMD FP4". Enabling flash write... Disabling read write protection of flash addresses from 0xfc000000 to 0xfc05ffff failed. Disabling read write protection of flash addresses from 0xfd000000 to 0xfd05ffff failed. Disabling read write protection of flash addresses from 0xfe000000 to 0xfe05ffff failed. Disabling read write protection of flash addresses from 0xff000000 to 0xff05ffff failed. FCH device found but SMBus revision 0x61 does not match known values. Please report this to flashrom(a)flashrom.org and include this log and the output of lspci -nnvx, thanks!. Could not determine chipset generation.PROBLEMS, continuing anyway No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. See attached lspci dump! Seems to be a bug, hope it can be fixed, or is there something I overlooked? Markus

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FAILED: Swanky Baytrail
by Chris Andrew Jan. 9, 2025

Jan. 9, 2025

Hi, guys. I'm trying to update the firmware for my Toshiba Swanky. I've done this several times before, without issue, but have got an error, this time. Can you tell me what you may need, to help troubleshoot this? *My machine:* System: Host: swanky Kernel: 6.12.4-arch1-1 arch: x86_64 bits: 64 Desktop: Xfce v: 4.18.1 Distro: EndeavourOS Machine: Type: Laptop System: GOOGLE product: Swanky v: 1.0 serial: 5F239563C Mobo: GOOGLE model: Swanky v: 1.0 serial: N/A UEFI: coreboot v: MrChromebox-4.22.4 date: 04/16/2024 Battery: ID-1: BAT0 charge: 33.1 Wh (97.6%) condition: 33.9/44.2 Wh (76.7%) CPU: Info: dual core model: Intel Celeron N2840 bits: 64 type: MCP cache: L2: 1024 KiB *The command I used, today:* [chris@swanky ~]$ cd; curl -LO mrchromebox.tech/firmware-util.sh && sudo bash firmware-util.sh *Some of the output:* This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Skipping writeprotect-based unlocking for read/verify operations. Block protection is disabled. Reading ich descriptor... read_flash: region (00000000..0x7fffff) is readable, reading range (00000000..0x000fff). done. Assuming chipset 'Baytrail'. Added layout entry 00000000 - 00000fff named fd Added layout entry 00200000 - 007fffff named bios Added layout entry 00001000 - 001fffff named me Using region: "bios". coreboot last image size (not ROM size) is 8388608 bytes. Manufacturer: Google Mainboard ID: Swanky This coreboot image matches this mainboard. spi_read_register: read from register 2 not supported by programmer I hope this helps, Chris (chris_debian)

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Re: BIOS update fails on a Minix Z100-0db device
by Robert Jan. 7, 2025

Jan. 7, 2025

Thank you Alex, this is very useful info. So if I am on 0161 now, do I have to go 0171 then 0181 then 0191? One more question: how do I back up the product key exactly? I already tried to update to 0181 with flashrom, but that failed, then reverte to 0161 with flashrom that succeeded. I hope I did not erase the product key? regards, Robert On Mon, 2025-01-06 at 11:25 +0800, Alex Lui wrote: > Dear Robert, > > Many thanks for contacting us. > > What is the currently BIOS version (project version) on NEO Z100-0dB? > When booting, press the "DEL" key repeatedly to enter the BIOS > homepage. See attached pic. > > AD0J0151 or AD0J0161 cannot be directly updated to AD0J0181 or > AD0J0.191 in UEFI. It must be updated to AD0J0.171 first. > > AD0J0171 BIOS for Z100-0dB can be downloaded from link below: > https://mega.nz/file/fvRkSIgJ#riNMb_bjsuTePo_l0Co1aWsCLTZTVAbNAw1j3vQC5WQ > > File name: Z100-0dB-BIOS-171_UEFI.zip > File size: 18.4 MB > > AD0J0181 BIOS update under UEFI for Z100-0dB can be downloaded from > link below: > https://mega.nz/file/T64FwaDR#Ic4a69ntKaoF2RrXLDcMM94x1Gt1YYkezWPediBWXtY > > Please note: Please back up the product key when updating BIOS under > UEFI, as this will erase the product key stored in the BIOS. > > Look forward to hearing from you soon. > > Best Regards, > Alex Lui > > Minix Group Company Limited > Minix Forum: https://theminixforum.com > > > > -----Original Message----- > From: Robert [mailto:openbsd@openbsd.hu] > Sent: Sunday, January 5, 2025 2:44 AM > To: support(a)minix.com.hk; flashrom(a)flashrom.org > Cc: openbsd(a)openbsd.hu > Subject: BIOS update fails on a Minix Z100-0db device > > > Hi guys, > > I tried to update the BIOS on my Minix Z100-0db device so that I can > boot a Linux UEFI from the NVME disk. Pls. see below: > > 1. As per > https://theminixforum.com/index.php?threads/guide-updating-bios-uefi-using-… > I downloaded the newest image for Minix:AD0J0181.bin > (well download zip, decompress) > 2. I booted the device from an archlinux install USB and copied the > new image there so I can access it > 3. I installed flashrom to the arch install OS (pacman -S flashrom), > the version is 1.5.1-1, compiled Dec 20 2024 4. I made a backup of > the current version: flashrom -p internal -c > "Opaque flash chip" -r my_backup_bios_AD0J0161.bin ... so far so > good .. > 5. I attempted to upload the new binary: flashrom -p internal -c > "Opaque flash chip" -w my_backup_bios_AD0J0161.bin > > issue follows: > > Opened /dev/mtd0 successfully > Found programmer flash chip "Opaque flash chip" > linux_mtd_wp_read_cfg: ioctl Operation not supported Failed to unlock > flash status reg with wp support. > Reading old flash chip contents... done. > Updating flash chip contents... linux_mtd_erase: MEMERASE ioctl call > returned -, error: Input/output error Erase/write done from 0 to > ffffff Write Failed!Uh oh. Erase/write failed. Checking if anything > has changed. > Reading current flash chip contents... done. > Apparently at least some data has changed. > Your flash chip is in an unknown state. > Get help ... > > Retried with -f, which in turn again changed something, but same > outcome. > I did not try to put back the original image so far, it would > probably give me the same > > The device is still on sitting in the arch install shell, I increased > the install disk size and added a few packages to help with the > possible fix, since I believe if I would try to reboot, the device > would be lost, and I would likely have to replace it. > > I am a long time linux user, can try any workaround or optionally > even allow ssh access to the device. > Can someone please give me some hints about where to go from here. > > Appeciate your time, > Robert

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Intel Corporation 82599ES - read success
by Jared Mauch Jan. 7, 2025

Jan. 7, 2025

Had to boot kernel w/ iomem=relaxed for a read to work $ sudo builddir/flashrom -p nicintel_spi:pci=81:00.0 -r W25X40-81-00-0.bin --progress flashrom v1.6.0-devel (git:v1.5.0-10-g2e6b0510) on Linux 6.1.0-29-amd64 (x86_64) flashrom is free software, get the source code at https://flashrom.org === This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output to flashrom(a)flashrom.org if it works for you. Please add the name of your PCI device to the subject. Thank you for your help! === Found Winbond flash chip "W25X40" (512 kB, SPI) on nicintel_spi. === This flash part has status UNTESTED for operations: WP The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash chip. Please include the flashrom log file for all operations you tested (see the man page for details), and mention which mainboard or programmer you tested in the subject line. You can also try to follow the instructions here: https://www.flashrom.org/contrib_howtos/how_to_mark_chip_tested.html Thanks for your help! Reading flash... [READ: 100%]...done. 81:00.0 Ethernet controller: Intel Corporation 82599ES 10-Gigabit SFI/SFP+ Network Connection (rev 01) Subsystem: Super Micro Computer Inc AOC-STGN-i2S Physical Slot: 1 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 30 NUMA node: 1 IOMMU group: 13 Region 0: Memory at faf80000 (64-bit, prefetchable) [size=512K] Region 2: I/O ports at f020 [size=32] Region 4: Memory at fb404000 (64-bit, prefetchable) [size=16K] Expansion ROM at fbe80000 [disabled] [size=512K] Capabilities: <access denied> Kernel driver in use: ixgbe Kernel modules: ixgbe 81:00.1 Ethernet controller: Intel Corporation 82599ES 10-Gigabit SFI/SFP+ Network Connection (rev 01) Subsystem: Super Micro Computer Inc AOC-STGN-i2S Physical Slot: 1 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin B routed to IRQ 340 NUMA node: 1 IOMMU group: 14 Region 0: Memory at faf00000 (64-bit, prefetchable) [size=512K] Region 2: I/O ports at f000 [size=32] Region 4: Memory at fb400000 (64-bit, prefetchable) [size=16K] Expansion ROM at fbe00000 [disabled] [size=512K] Capabilities: <access denied> Kernel driver in use: ixgbe Kernel modules: ixgbe -- Jared Mauch | pgp key available via finger from jared(a)puck.nether.net clue++; | http://puck.nether.net/~jared/ My statements are only mine.

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BIOS update fails on a Minix Z100-0db device
by Robert Jan. 4, 2025

Jan. 4, 2025

Hi guys, I tried to update the BIOS on my Minix Z100-0db device so that I can boot a Linux UEFI from the NVME disk. Pls. see below: 1. As per https://theminixforum.com/index.php?threads/guide-updating-bios-uefi-using-… I downloaded the newest image for Minix:AD0J0181.bin (well download zip, decompress) 2. I booted the device from an archlinux install USB and copied the new image there so I can access it 3. I installed flashrom to the arch install OS (pacman -S flashrom), the version is 1.5.1-1, compiled Dec 20 2024 4. I made a backup of the current version: flashrom -p internal -c "Opaque flash chip" -r my_backup_bios_AD0J0161.bin ... so far so good .. 5. I attempted to upload the new binary: flashrom -p internal -c "Opaque flash chip" -w my_backup_bios_AD0J0161.bin issue follows: Opened /dev/mtd0 successfully Found programmer flash chip "Opaque flash chip" linux_mtd_wp_read_cfg: ioctl Operation not supported Failed to unlock flash status reg with wp support. Reading old flash chip contents... done. Updating flash chip contents... linux_mtd_erase: MEMERASE ioctl call returned -, error: Input/output error Erase/write done from 0 to ffffff Write Failed!Uh oh. Erase/write failed. Checking if anything has changed. Reading current flash chip contents... done. Apparently at least some data has changed. Your flash chip is in an unknown state. Get help ... Retried with -f, which in turn again changed something, but same outcome. I did not try to put back the original image so far, it would probably give me the same The device is still on sitting in the arch install shell, I increased the install disk size and added a few packages to help with the possible fix, since I believe if I would try to reboot, the device would be lost, and I would likely have to replace it. I am a long time linux user, can try any workaround or optionally even allow ssh access to the device. Can someone please give me some hints about where to go from here. Appeciate your time, Robert

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