Ron,
You may be well along this path anyway but this may be of some use.
So after wandering through the documentation abyss this is what I've gleaned so far:
From a product spec. in this case "Enterprise Server Group Intel N440BX
Server Technical Product Specification" (I think I saw a similar one for a 440gx based product ...) there is a BUD. They have a FLASH_PE_L GPO24 (General Purpose Output from the PIIX4) and DIS_NON_FLASH_SMI GPO25. If you look at the inputs to the BUD the DIS_NON_FLASH_SMI goes into pin 8 on the BUD and seems to control the secure FLASH programming. While looking there you can see that there is a EN_SMI_L line that goes into the BUD this enables SMI generation (you would want to disable this before trying to write to the FLASH again). The EN_SMI_L is driven by GPIO bit 9. Also on the BUD, pin 48 is driven by the FLASH_PE_L (if you don't disable SMI generation I suspect you just get another SMI...).
So it would seem that for THIS system once you are in the SMI interrupt that should be able to set various IO signals on the PIIX4 to disable SMI and enable writing to the Flash.
Now I would suspect that your motherboard would be similar to one like this but then this is Intel we're talking about ...
Wallace
-----Original Message----- From: Ronald G. Minnich [SMTP:rminnich@lanl.gov] Sent: Tuesday, February 08, 2000 12:09 PM To: 'openbios@freiburg.linux.de' Subject: RE: [OpenBIOS] l440gx+ nvram writing ...
On Tue, 8 Feb 2000, Wallace I. Kroeker wrote:
Ron, Have a look at this ( I had to do a search of all the intel site) but it does give a description of how their Flash works (flow charts etc). It also give references to source
code
but I'm not sure if this is freely available or not. Professional I/O Application Developer's Kit User's Manual August 1998
Yup, I've got that. It's worth getting. Where we're stopped at present is the BUD on the l440gx+, though.
thanks
ron
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