June 2011 - OpenBIOS - mail.coreboot.org

Re: [OpenBIOS] Solaris anyone?
by Nick Couchman Sept. 12, 2011

Sept. 12, 2011

> Hi Nick, > > Thanks again for testing this. The issue with Solaris not detecting the > disks is a known one - the following guide should point you in the right > direction: > > http://virtuallyfun.blogspot.com/2010/10/formatting-disks-for-solaris.html > > Also don't forget the "set scsi_options" part from Artyom's SPARC/QEMU > howto here: http://tyom.blogspot.com/2009/12/solaris-under-qemu-how-to.html > > I think it may actually be possible to come up with a patch for OpenBIOS > so that the scsi_options change isn't required - let me know how you get > on with the above links, and if it all seems to work I'll look at > creating the patch for you. > > Okay, I got passed the issue with formatting the root filesystem. Apparently there are some limitations on the C/H/S parameters you use for the disk that correspond with how UFS wants to format a new filesystem. I'm not sure what exactly those limitations are at this point, but, by adjusting a couple of the C/H/S settings when using format to set up the disk I was able to get it to work correctly. So, I now have Solaris 9 installed on qemu-system-sparc with OpenBIOS! I'll probably go back to Solaris 8 as that one has a free binary license while Solaris 9 is a commercial license, IIRC. I do own a Solaris 9 commercial license, but I like the free idea, better. Anyway, now I'm on to an issue with networking - I've used the following two qemu network parameter combinations: -net nic -net tap,ifname=tap0 -net nic -net user In the first instance, tap0 was configured on my Linux box and added to my bridge br0. In both cases the Solaris system is unable to obtain a DHCP address - the DHCP client times out. Not sure if I should be using a different parameter set, or if this is another area that needs some work either for OpenBIOS or qemu? -Nick -------- This e-mail may contain confidential and privileged material for the sole use of the intended recipient. If this email is not intended for you, or you are not responsible for the delivery of this message to the intended recipient, please note that this message may contain SEAKR Engineering (SEAKR) Privileged/Proprietary Information. In such a case, you are strictly prohibited from downloading, photocopying, distributing or otherwise using this message, its contents or attachments in any way. If you have received this message in error, please notify us immediately by replying to this e-mail and delete the message from your mailbox. Information contained in this message that does not relate to the business of SEAKR is neither endorsed by nor attributable to SEAKR.

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fcode rom loading
by Bob Breuer July 14, 2011

July 14, 2011

I'm trying to get the sparc32 OpenBIOS to load an fcode rom, but it's not working. After byte-load, it reports out of memory. Here's the steps I'm using to setup a simple rom which just sets the device name to "QEMU,test", and then trying to run it: fd000000 1000 l! 00000020 1004 l! 12095145 1008 l! 4d552c74 100c l! 65737401 1010 l! 1412046e 1014 l! 616d6501 1018 l! 10000000 101c l! cd /iommu/sbus " /iommu/sbus" select-dev new-device 1000 1 byte-load Here, OpenBIOS will report out of memory. Bob

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Re: [OpenBIOS] SS-10 and SS-20
by Brian Vandenberg June 20, 2011

June 20, 2011

I'm curious whether support exists for sparcstation's 10 & 20 yet. Any comments? -Brian

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[commit] r1043 - trunk/openbios-devel/arch/ppc/qemu
by repository service June 18, 2011

June 18, 2011

Author: agraf Date: Fri Jun 17 02:55:02 2011 New Revision: 1043 URL: http://tracker.coreboot.org/trac/openbios/changeset/1043 Log: ppc: fix mtmsr for SF setting When running openbios-ppc32 on a ppc64 VM, we need to unset SF on every interrupt to ensure that things still work. So far we've been using mtmsr for this operation, but according to the spec mtmsr doesn't set any bit above 32bit, so we were merely exploiting a bug in qemu before. This patch adds a runtime check on MSR_SF to see if we're running on a 64-bit capable CPU. If so, we use mtmsrd, which can set the high 32bits of MSR. CC: Andreas Färber <andreas.faerber(a)web.de> CC: Segher Boessenkool <segher(a)kernel.crashing.org> Signed-off-by: Alexander Graf <agraf(a)suse.de> --- v1 -> v2: - use segher's awesome MSR_SF detection Modified: trunk/openbios-devel/arch/ppc/qemu/start.S Modified: trunk/openbios-devel/arch/ppc/qemu/start.S ============================================================================== --- trunk/openbios-devel/arch/ppc/qemu/start.S Fri Jun 17 02:55:00 2011 (r1042) +++ trunk/openbios-devel/arch/ppc/qemu/start.S Fri Jun 17 02:55:02 2011 (r1043) @@ -37,9 +37,16 @@ #define EXCEPTION_PREAMBLE_TEMPLATE \ mtsprg1 r1 ; /* scratch */ \ + mfcr r1 ; \ + mtsprg2 r1 ; /* scratch */ \ + lis r1, 0x8000 ; /* r1=0x80000000 */ \ + add. r1,r1,r1 ; /* r1=r1+r1 (high 32bit !0) */ \ + beq 1f; \ + \ mfmsr r1 ; /* unset MSR_SF */ \ clrlwi r1,r1,0 ; \ - mtmsr r1 ; \ + mtmsrd r1 ; \ +1: \ mfsprg0 r1 ; /* exception stack in sprg0 */ \ .ifc ULONG_SIZE, 8 ; \ addi r1,r1,-(40 * ULONG_SIZE) ; /* push exception frame */ \ @@ -85,7 +92,7 @@ \ mflr r0 ; \ stl r0,(13 * ULONG_SIZE)(r1) ; \ - mfcr r0 ; \ + mfsprg2 r0 ; \ stl r0,(14 * ULONG_SIZE)(r1) ; \ mfctr r0 ; \ stl r0,(15 * ULONG_SIZE)(r1) ; \ @@ -301,14 +308,12 @@ ILLEGAL_VECTOR( 0x200 ) VECTOR( 0x300, "DSI" ): - EXCEPTION_PREAMBLE - b call_dsi_exception + b real_dsi ILLEGAL_VECTOR( 0x380 ) VECTOR( 0x400, "ISI" ): - EXCEPTION_PREAMBLE - b call_isi_exception + b real_isi ILLEGAL_VECTOR( 0x480 ) @@ -359,6 +364,14 @@ #endif +real_dsi: + EXCEPTION_PREAMBLE + b call_dsi_exception + +real_isi: + EXCEPTION_PREAMBLE + b call_isi_exception + GLOBL(__vectors_end): /************************************************************************/ @@ -368,10 +381,21 @@ GLOBL(_entry): #ifdef CONFIG_PPC_64BITSUPPORT - /* clear MSR, disable MMU */ - li r0,0 + + lis r3, 0x8000 /* r1=0x80000000 */ + add. r3,r3,r3 /* r1=r1+r1 (high 32bit !0) */ + beq no_64bit /* only true when !MSR_SF */ + + /* clear MSR, disable MMU, SF */ + mtmsrd r0 + b real_entry + +no_64bit: + /* clear MSR, disable MMU */ mtmsr r0 + +real_entry: #endif /* copy exception vectors */

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[commit] r1042 - trunk/openbios-devel/arch/ppc/qemu
by repository service June 17, 2011

June 17, 2011

Author: agraf Date: Fri Jun 17 02:55:00 2011 New Revision: 1042 URL: http://tracker.coreboot.org/trac/openbios/changeset/1042 Log: ppc: add POWER4 cpu description So far, we only supported the 970fx CPU type inside guests. Unfortunately, that CPU supports Altivec. Not all KVM capable host CPUs do have altivec though, so they're left out in the rain when running openbios in the guest. This patch adds POWER4 CPU description, allowing users to specify at least one CPU type that does not require Altivec, but is still 64-bit capable. Signed-off-by: Alexander Graf <agraf(a)suse.de> Modified: trunk/openbios-devel/arch/ppc/qemu/init.c Modified: trunk/openbios-devel/arch/ppc/qemu/init.c ============================================================================== --- trunk/openbios-devel/arch/ppc/qemu/init.c Mon May 23 00:29:33 2011 (r1041) +++ trunk/openbios-devel/arch/ppc/qemu/init.c Fri Jun 17 02:55:00 2011 (r1042) @@ -507,6 +507,18 @@ .clock_frequency = 0x1dcd6500, .initfn = cpu_970_init, }, + { + .iu_version = 0x00350000, + .name = "PowerPC,POWER4", + .icache_size = 0x10000, + .dcache_size = 0x8000, + .icache_sets = 0x100, + .dcache_sets = 0x40, + .icache_block_size = 0x80, + .dcache_block_size = 0x80, + .clock_frequency = 0x629b4940, + .initfn = cpu_970_init, + }, }; static const struct cpudef *

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[PATCH] ppc: fix mtmsr for SF setting
by Alexander Graf June 17, 2011

June 17, 2011

When running openbios-ppc32 on a ppc64 VM, we need to unset SF on every interrupt to ensure that things still work. So far we've been using mtmsr for this operation, but according to the spec mtmsr doesn't set any bit above 32bit, so we were merely exploiting a bug in qemu before. This patch adds a runtime check on PVR to see if we're running on a 64-bit capable CPU. If so, we use mtmsrd, which can set the high 32bits of MSR. CC: Andreas Färber <andreas.faerber(a)web.de> Signed-off-by: Alexander Graf <agraf(a)suse.de> --- arch/ppc/qemu/start.S | 50 +++++++++++++++++++++++++++++++++++++++++------- 1 files changed, 42 insertions(+), 8 deletions(-) diff --git a/arch/ppc/qemu/start.S b/arch/ppc/qemu/start.S index 0d64568..70a4f92 100644 --- a/arch/ppc/qemu/start.S +++ b/arch/ppc/qemu/start.S @@ -37,9 +37,21 @@ #define EXCEPTION_PREAMBLE_TEMPLATE \ mtsprg1 r1 ; /* scratch */ \ + mfcr r1 ; \ + mtsprg2 r1 ; /* scratch */ \ + mtsprg3 r2 ; /* scratch */ \ + mfpvr r1 ; \ + lis r2, 0x330000@h ; /* lowest 64-bit PVR */ \ + cmplw r1, r2 ; \ + blt 1f; \ + oris r2, r2, 0x70000000@h ; /* highest 64-bit PVR */ \ + cmplw r1, r2 ; \ + bge 1f; \ + \ mfmsr r1 ; /* unset MSR_SF */ \ clrlwi r1,r1,0 ; \ - mtmsr r1 ; \ + mtmsrd r1 ; \ +1: \ mfsprg0 r1 ; /* exception stack in sprg0 */ \ .ifc ULONG_SIZE, 8 ; \ addi r1,r1,-(40 * ULONG_SIZE) ; /* push exception frame */ \ @@ -50,6 +62,7 @@ stl r0,(0 * ULONG_SIZE)(r1) ; /* save r0 */ \ mfsprg1 r0 ; \ stl r0,(1 * ULONG_SIZE)(r1) ; /* save r1 */ \ + mfsprg3 r2 ; \ stl r2,(2 * ULONG_SIZE)(r1) ; /* save r2 */ \ stl r3,(3 * ULONG_SIZE)(r1) ; /* save r3 */ \ stl r4,(4 * ULONG_SIZE)(r1) ; \ @@ -85,7 +98,7 @@ \ mflr r0 ; \ stl r0,(13 * ULONG_SIZE)(r1) ; \ - mfcr r0 ; \ + mfsprg2 r0 ; \ stl r0,(14 * ULONG_SIZE)(r1) ; \ mfctr r0 ; \ stl r0,(15 * ULONG_SIZE)(r1) ; \ @@ -301,14 +314,12 @@ VECTOR( 0x100, "SRE" ): ILLEGAL_VECTOR( 0x200 ) VECTOR( 0x300, "DSI" ): - EXCEPTION_PREAMBLE - b call_dsi_exception + b real_dsi ILLEGAL_VECTOR( 0x380 ) VECTOR( 0x400, "ISI" ): - EXCEPTION_PREAMBLE - b call_isi_exception + b real_isi ILLEGAL_VECTOR( 0x480 ) @@ -359,6 +370,14 @@ VECTOR( 0x2200, "ISI_64" ): #endif +real_dsi: + EXCEPTION_PREAMBLE + b call_dsi_exception + +real_isi: + EXCEPTION_PREAMBLE + b call_isi_exception + GLOBL(__vectors_end): /************************************************************************/ @@ -368,10 +387,25 @@ GLOBL(__vectors_end): GLOBL(_entry): #ifdef CONFIG_PPC_64BITSUPPORT - /* clear MSR, disable MMU */ - li r0,0 + + mfpvr r3 + lis r4, 0x330000@h /* lowest 64-bit PVR */ + cmplw r3, r4 + blt no_64bit + oris r4, r4, 0x70000000@h /* highest 64-bit PVR */ + cmplw r3, r4 + bge no_64bit + + /* clear MSR, disable MMU, SF */ + mtmsrd r0 + b real_entry + +no_64bit: + /* clear MSR, disable MMU */ mtmsr r0 + +real_entry: #endif /* copy exception vectors */ -- 1.6.0.2

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[commit] r1044 - trunk/openbios-devel/arch/ppc/qemu
by repository service June 17, 2011

June 17, 2011

Author: agraf Date: Fri Jun 17 02:55:04 2011 New Revision: 1044 URL: http://tracker.coreboot.org/trac/openbios/changeset/1044 Log: ppc: only clear MSR_SF when clearing high MSR bits We are pretty aggressive now with how we clear the high MSR bits, clearing all of them when we find a 64-bit CPU. As Segher points out, this is not always a good idea though. There might be bits set that can be crucial for operation. Hence we should only clear MSR_SF, as that's the bit we're interested in. Reported-by: Segher Boessenkool <segher(a)kernel.crashing.org> Signed-off-by: Alexander Graf <agraf(a)suse.de> Modified: trunk/openbios-devel/arch/ppc/qemu/start.S Modified: trunk/openbios-devel/arch/ppc/qemu/start.S ============================================================================== --- trunk/openbios-devel/arch/ppc/qemu/start.S Fri Jun 17 02:55:02 2011 (r1043) +++ trunk/openbios-devel/arch/ppc/qemu/start.S Fri Jun 17 02:55:04 2011 (r1044) @@ -44,7 +44,7 @@ beq 1f; \ \ mfmsr r1 ; /* unset MSR_SF */ \ - clrlwi r1,r1,0 ; \ + clrldi r1,r1,1 ; \ mtmsrd r1 ; \ 1: \ mfsprg0 r1 ; /* exception stack in sprg0 */ \

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[PATCH] ppc: fix mtmsr for SF setting
by Alexander Graf June 17, 2011

June 17, 2011

When running openbios-ppc32 on a ppc64 VM, we need to unset SF on every interrupt to ensure that things still work. So far we've been using mtmsr for this operation, but according to the spec mtmsr doesn't set any bit above 32bit, so we were merely exploiting a bug in qemu before. This patch adds a runtime check on PVR to see if we're running on a 64-bit capable CPU. If so, we use mtmsrd, which can set the high 32bits of MSR. CC: Andreas Färber <andreas.faerber(a)web.de> Signed-off-by: Alexander Graf <agraf(a)suse.de> --- arch/ppc/qemu/start.S | 50 +++++++++++++++++++++++++++++++++++++++++------- 1 files changed, 42 insertions(+), 8 deletions(-) diff --git a/arch/ppc/qemu/start.S b/arch/ppc/qemu/start.S index 0d64568..70a4f92 100644 --- a/arch/ppc/qemu/start.S +++ b/arch/ppc/qemu/start.S @@ -37,9 +37,21 @@ #define EXCEPTION_PREAMBLE_TEMPLATE \ mtsprg1 r1 ; /* scratch */ \ + mfcr r1 ; \ + mtsprg2 r1 ; /* scratch */ \ + mtsprg3 r2 ; /* scratch */ \ + mfpvr r1 ; \ + lis r2, 0x330000@h ; /* lowest 64-bit PVR */ \ + cmplw r1, r2 ; \ + blt 1f; \ + oris r2, r2, 0x70000000@h ; /* highest 64-bit PVR */ \ + cmplw r1, r2 ; \ + bge 1f; \ + \ mfmsr r1 ; /* unset MSR_SF */ \ clrlwi r1,r1,0 ; \ - mtmsr r1 ; \ + mtmsrd r1 ; \ +1: \ mfsprg0 r1 ; /* exception stack in sprg0 */ \ .ifc ULONG_SIZE, 8 ; \ addi r1,r1,-(40 * ULONG_SIZE) ; /* push exception frame */ \ @@ -50,6 +62,7 @@ stl r0,(0 * ULONG_SIZE)(r1) ; /* save r0 */ \ mfsprg1 r0 ; \ stl r0,(1 * ULONG_SIZE)(r1) ; /* save r1 */ \ + mfsprg3 r2 ; \ stl r2,(2 * ULONG_SIZE)(r1) ; /* save r2 */ \ stl r3,(3 * ULONG_SIZE)(r1) ; /* save r3 */ \ stl r4,(4 * ULONG_SIZE)(r1) ; \ @@ -85,7 +98,7 @@ \ mflr r0 ; \ stl r0,(13 * ULONG_SIZE)(r1) ; \ - mfcr r0 ; \ + mfsprg2 r0 ; \ stl r0,(14 * ULONG_SIZE)(r1) ; \ mfctr r0 ; \ stl r0,(15 * ULONG_SIZE)(r1) ; \ @@ -301,14 +314,12 @@ VECTOR( 0x100, "SRE" ): ILLEGAL_VECTOR( 0x200 ) VECTOR( 0x300, "DSI" ): - EXCEPTION_PREAMBLE - b call_dsi_exception + b real_dsi ILLEGAL_VECTOR( 0x380 ) VECTOR( 0x400, "ISI" ): - EXCEPTION_PREAMBLE - b call_isi_exception + b real_isi ILLEGAL_VECTOR( 0x480 ) @@ -359,6 +370,14 @@ VECTOR( 0x2200, "ISI_64" ): #endif +real_dsi: + EXCEPTION_PREAMBLE + b call_dsi_exception + +real_isi: + EXCEPTION_PREAMBLE + b call_isi_exception + GLOBL(__vectors_end): /************************************************************************/ @@ -368,10 +387,25 @@ GLOBL(__vectors_end): GLOBL(_entry): #ifdef CONFIG_PPC_64BITSUPPORT - /* clear MSR, disable MMU */ - li r0,0 + + mfpvr r3 + lis r4, 0x330000@h /* lowest 64-bit PVR */ + cmplw r3, r4 + blt no_64bit + oris r4, r4, 0x70000000@h /* highest 64-bit PVR */ + cmplw r3, r4 + bge no_64bit + + /* clear MSR, disable MMU, SF */ + mtmsrd r0 + b real_entry + +no_64bit: + /* clear MSR, disable MMU */ mtmsr r0 + +real_entry: #endif /* copy exception vectors */ -- 1.6.0.2

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[PATCH] ppc: only clear MSR_SF when clearing high MSR bits
by Alexander Graf June 16, 2011

June 16, 2011

We are pretty aggressive now with how we clear the high MSR bits, clearing all of them when we find a 64-bit CPU. As Segher points out, this is not always a good idea though. There might be bits set that can be crucial for operation. Hence we should only clear MSR_SF, as that's the bit we're interested in. Reported-by: Segher Boessenkool <segher(a)kernel.crashing.org> Signed-off-by: Alexander Graf <agraf(a)suse.de> --- arch/ppc/qemu/start.S | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/ppc/qemu/start.S b/arch/ppc/qemu/start.S index f06f6d5..aa582e2 100644 --- a/arch/ppc/qemu/start.S +++ b/arch/ppc/qemu/start.S @@ -44,7 +44,7 @@ beq 1f; \ \ mfmsr r1 ; /* unset MSR_SF */ \ - clrlwi r1,r1,0 ; \ + clrldi r1,r1,1 ; \ mtmsrd r1 ; \ 1: \ mfsprg0 r1 ; /* exception stack in sprg0 */ \ -- 1.6.0.2

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Re: [OpenBIOS] Solaris anyone?
by Kenneth Salerno June 6, 2011

June 6, 2011

Really. Who has a sound card on a sparc server anyway? (I can feel the offended stares of the Sun Blade100 users)

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