OT: linux kernel problem
by Edwin Rhodes
when compiling my linux kernel i keep on recieving this message:
Warning: Clock Skew Detected Build May Be Incomplete
It seams to compile ok.
What does this error message mean?? and how can i fix it.
thanks
edwin
ps. I have only been getting this message since i upgraded to an AMD K6-2 500Mhz.
19 years, 6 months
- 4
- 3
L2 cache
by Ronald G Minnich
A quick run with lmbench shows we're not turning it on.
Any ideas?
ron
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19 years, 7 months
- 1
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IO-APIC
by James Hendricks
I don't think our IO-APIC is enabled.. We tell it to set its ID to 2,
but it continues to think its ID is F. Here is the kernel panic:
ENABLING IO-APIC IRQs.
...changing IO-APIC physical APIC ID to 2 ...
Kernel panic: could not set ID!.
.
In idle task - not syncing.
APIC error interrupt on CPU#0, should never happen..
... APIC ESR0: 00000000.
... APIC ESR1: 00000040.
... bit 6: Received Illegal Vector
Does anyone know how to setup the IO-APIC correctly and/or know where I
can find this information (Maciej, you wrote io_apic.c, right?)?
Any help would be greatly appreciated. Thanks.
- James
>>>>>> Here is the full boot so far:
Linux version 2.4.0-test1 (jimi@snaresland) (gcc version egcs-2.91.66 19990314/Linux (egcs-1.1.2 release)) #7 SMP Mon Jun 26 16:46:02 MDT 2000.
BIOS-provided physical RAM map:.
e820: 000000000009f000 @ 0000000000000000 (usable).
e820: 0000000003e00000 @ 0000000000100000 (usable).
Scan SMP from c0000000 for 1024 bytes..
found SMP MP-table at 00000000.
hm, page 00000000 reserved twice..
On node 0 totalpages: 16128.
zone(0): 4096 pages..
zone(1): 12032 pages..
zone(2): 0 pages..
Intel MultiProcessor Specification v1.4.
Virtual Wire compatibility mode..
Default MP configuration #5.
Processor #0 Pentium(tm) Pro APIC version 16.
Floating point unit present..
Machine Exception supported..
64 bit compare & exchange supported..
Internal APIC present..
Processor #1 Pentium(tm) Pro APIC version 16.
Floating point unit present..
Machine Exception supported..
64 bit compare & exchange supported..
Internal APIC present..
Bus #0 is ISA .
Bus #1 is PCI .
I/O APIC #2 Version 16 at 0xFEC00000..
Int: type 0, pol 0, trig 0, bus 0, IRQ 00, APIC ID 2, APIC INT 02.
Int: type 0, pol 0, trig 0, bus 0, IRQ 01, APIC ID 2, APIC INT 01.
Int: type 0, pol 0, trig 0, bus 0, IRQ 03, APIC ID 2, APIC INT 03.
Int: type 0, pol 0, trig 0, bus 0, IRQ 04, APIC ID 2, APIC INT 04.
Int: type 0, pol 0, trig 0, bus 0, IRQ 05, APIC ID 2, APIC INT 05.
Int: type 0, pol 0, trig 0, bus 0, IRQ 06, APIC ID 2, APIC INT 06.
Int: type 0, pol 0, trig 0, bus 0, IRQ 07, APIC ID 2, APIC INT 07.
Int: type 0, pol 0, trig 0, bus 0, IRQ 08, APIC ID 2, APIC INT 08.
Int: type 0, pol 0, trig 0, bus 0, IRQ 09, APIC ID 2, APIC INT 09.
Int: type 0, pol 0, trig 0, bus 0, IRQ 0a, APIC ID 2, APIC INT 0a.
Int: type 0, pol 0, trig 0, bus 0, IRQ 0b, APIC ID 2, APIC INT 0b.
Int: type 0, pol 0, trig 0, bus 0, IRQ 0c, APIC ID 2, APIC INT 0c.
Int: type 0, pol 0, trig 0, bus 0, IRQ 0d, APIC ID 2, APIC INT 0d.
Int: type 0, pol 0, trig 0, bus 0, IRQ 0e, APIC ID 2, APIC INT 0e.
Int: type 0, pol 0, trig 0, bus 0, IRQ 0f, APIC ID 2, APIC INT 0f.
Int: type 3, pol 0, trig 0, bus 0, IRQ 00, APIC ID 2, APIC INT 00.
Lint: type 3, pol 0, trig 0, bus 0, IRQ 00, APIC ID ff, APIC LINT 00.
Lint: type 1, pol 0, trig 0, bus 0, IRQ 00, APIC ID ff, APIC LINT 01.
Processors: 2.
mapped APIC to ffffe000 (fee00000).
James: boot_cpu_id being set to 2016 from APIC_ID.
mapped IOAPIC to ffffd000 (fec00000).
Enabling extended fast FPU save and restore ... done..
Enabling KNI unmasked exception support ... done..
Kernel command line: root=/dev/hda1 ide0=reset.
Initializing CPU#0.
Detected 497445265 Hz processor..
Calibrating delay loop... 992.87 BogoMIPS.
Memory: 61980k/64512k available (585k kernel code, 2144k reserved, 69k data, 156k init, 0k highmem).
Dentry-cache hash table entries: 8192 (order: 4, 65536 bytes).
Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes).
Page-cache hash table entries: 16384 (order: 4, 65536 bytes).
kmem_create: Poisoning requested, but con given - bdev_cache.
Inode-cache hash table entries: 4096 (order: 3, 32768 bytes).
kmem_create: Poisoning requested, but con given - inode_cache.
CPU serial number disabled..
Checking 386/387 coupling... OK, FPU using exception 16 error reporting..
Checking 'hlt' instruction... OK..
POSIX conformance testing by UNIFIX.
mtrr: v1.36 (20000221) Richard Gooch (rgooch(a)atnf.csiro.au).
CPU serial number disabled..
CPU0: Intel Pentium III (Katmai) stepping 03.
per-CPU timeslice cutoff: 0.00 usecs..
Getting VERSION: 40011.
Getting VERSION: 40011.
Getting LVT0: 700.
Getting LVT1: 400.
enabled ExtINT on CPU#0.
ESR value before enabling vector: 00000000.
ESR value after enabling vector: 00000000.
CPU present map: 3.
Booting processor 1/0 eip 2000.
Setting warm reset code and vector..
1..
2..
3..
Asserting INIT..
Waiting for send to finish....
+Deasserting INIT..
Waiting for send to finish....
+#startup loops: 2..
Sending STARTUP #1..
After apic_write..
Startup point 1..
Waiting for send to finish....
+Initializing CPU#1.
Sending STARTUP #2..
After apic_write..
Startup point 1..
CPU#1 (phys ID: 0) waiting for CALLOUT.
Waiting for send to finish....
+After Startup..
Before Callout 1..
After Callout 1..
CALLIN, before setup_local_APIC()..
masked ExtINT on CPU#1.
ESR value before enabling vector: 00000000.
ESR value after enabling vector: 00000000.
Calibrating delay loop... 992.87 BogoMIPS.
Stack at about c116dfbc.
CPU serial number disabled..
OK..
CPU1: Intel Pentium III (Katmai) stepping 03.
CPU has booted..
Before bogomips..
Total of 2 processors activated (1985.74 BogoMIPS)..
Before bogocount - setting activated=1..
Boot done..
ENABLING IO-APIC IRQs.
...changing IO-APIC physical APIC ID to 2 ...
Kernel panic: could not set ID!.
.
In idle task - not syncing.
APIC error interrupt on CPU#0, should never happen..
... APIC ESR0: 00000000.
... APIC ESR1: 00000040.
... bit 6: Received Illegal Vector
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19 years, 7 months
- 4
- 4
visitor
by ronnie-liu＠ali.com.tw
Hi:
I found the OpenBIOS web site when surfing the internet. I am
interesting in this topic. Is this project still going?
Ronnie
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19 years, 7 months
- 2
- 1
RE: [OpenBIOS] Finding FlashROM chips?
by Jessen, Per
www.questlink.com
regards,
Per Jessen, ENIDAN Technologies, London
> -----Original Message-----
> From: Jeff Garzik [mailto:jgarzik@mandrakesoft.com]
> Sent: 21 June 2000 16:06
> To: freebios-devel(a)sourceforge.net
> Cc: openbios(a)elvis.informatik.uni-freiburg.de
> Subject: [OpenBIOS] Finding FlashROM chips?
>
>
> Can anybody point to a source of flashrom chips on the web?
> Preferably
> a US supplier since I don't want to ship overseas if I can avoid it..
>
> Jeff
>
>
>
>
> --
> Jeff Garzik |
> Building 1024 | Free beer tomorrow.
> MandrakeSoft, Inc. |
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>
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19 years, 7 months
- 1
- 0
Re: Information on TIARA project
by Ollie Lho
"Larry G. Linde" wrote:
>
> We are working on a 540 design at present and need to start porting to the
> 540/950 chipset.
>
> However we have not been able to find any off the shelf MB's with the 540
> yet. If you could get
> Us the name of a existing 540 MB with the 950 that we could buy that would
> help a lot. Also
> And code/doc info in setup that required on the 540/950 would help as well.
>
> If you would like I will be in TW in about 2 weeks. I can stop by and say
> hello and show you
> What we are doing.
>
> -larry
First of all, it is amazing (from our point of view) that without official
support you could do such chip init stuff so clean, how did you do this ??
As you know we are working with FreeBIOS/LinuxBIOS project, we are also
intrested in any similiar projects too. We will provide any support we
can, we will provide you the necessary documents, BIOS source/pseudo code
and hardware demo boards. As posted by Jeff Garzik et. al. on freebios
list we think there is possibility to cooperate/merge these free bios
projects.
For 540+950 issue, there are two things to note. First is that, from
business point of view, it seems that 540 chipset will not in mass
production in the near future so it would be very difficult to find
a 540 M/B in the market. We are rather focusing on 630 and the upcomming
730 series. As far as I know there is only WinFast 5400MA avaliable in
Taiwan market.
The second is that, of course we want our whole product line fully supported.
I am personally planing to have full support (i.e. boot from cold power up
without BIOS) for the following combination in the end of August (possible ??)
630/540 single chip + 950 LPC
620/530 north + 5595 sourth + 6801 SuperIO
so we need somebody to "port" or try the current implementation on these
different platforms.
Finally, it glad that you are going to visit Taiwan. If you have time,
please arrange to visit SiS and demo your work. We can show you how/what
we have done on LinuxBIOS side.
Ollie
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19 years, 7 months
- 5
- 5
another free bios project
by gram wilson
I just came across this project at SourceForge:
Talkware TIARA, an Openbios/GRUB/PFORTH composite, BIOS replacement.
Boots an unmodifed linux kernel from an IDE drive or ethernet, using
only 128kb of flash. Works with INTEL/AMD K6/2-450, SiS 530/5595 and
8139 enet. VGA & Serial console supported.
and was wondering if anybody had heard of it?
It got me thinking that maybe all of the free bios developers (this
project, freebios, openbios, linuxbios) should get together and
collaborate on features. This way there would be more developers,
which could mean accelerated development, better features, and more
testing.
Also, I would like to thank all of the people who work on these
projects now, because a free/open source bios is something we all really
need.
-gram
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19 years, 7 months
- 5
- 5
TIARA URL
by Ed Dantes
Hi Joerg
The only URL for TIARA seems to be
http://sourceforge.net/projects/utcboot/
Have fun
Ed
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19 years, 7 months
- 1
- 0
Log_bufs
by James V Hendricks
OK. Another snapshot. What worries me is the per-cpu timeslice cutoff
being listed as 0 usecs. The 'kernel bug' means that either the APIC is
not on still or that we don't set boot_cpu_id correctly; the
line is:
if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_id)
BUG();
Furthermore, if I skip the check, I get the following message:
APIC error interrupt on CPU#0, should never happen..
... APIC ESR0: 00000080.
... APIC ESR1: 00000080.
... bit 7: Illegal Register Address..
APIC error interrupt on CPU#0, should never happen..
... APIC ESR0: 00000080.
... APIC ESR1: 00000080.
... bit 7: Illegal Register Address..
APIC error interrupt on CPU#0, should never happen..
... APIC ESR0: 00000080.
... APIC ESR1: 00000080.
... bit 7: Illegal
So here is where SMP boot is at now:
Linux version 2.3.99-pre5 (rminnich@mini) (gcc version egcs-2.91.66 19990314/Linux (egcs-1.1.2 release)) #57 SMP Mon Jun 19 17:40:30 MDT 2000.
initially ALT_MEM_K is 0xf800, EXT_MEM_K is 0x3c00, E820_MAP_NR is 0x0.
initially command line is root=/dev/hda1 ide0=reset.
ALT_MEM_K is 0xf800, EXT_MEM_K is 0x3c00, E820_MAP_NR is 0x0.
Scan SMP from c0000000 for 1024 bytes..
found SMP MP-table at 00000000.
hm, page 00000000 reserved twice..
On node 0 totalpages: 16128.
zone(0): 4096 pages..
zone(1): 12032 pages..
zone(2): 0 pages..
Intel MultiProcessor Specification v1.4.
Virtual Wire compatibility mode..
Default MP configuration #5.
Bus #0 is ISA.
Bus #1 is PCI.
Processors: 2.
mapped APIC to ffffe000 (fee00000).
mapped IOAPIC to ffffd000 (fec00000).
Initializing CPU#0.
Detected 497440714 Hz processor..
ide_setup: ide0=reset.
Console: colour VGA+ 80x25.
Calibrating delay loop... 989.59 BogoMIPS.
Memory: 61356k/64512k available (898k kernel code, 2768k reserved, 96k data, 84k init, 0k highmem).
Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes).
Page-cache hash table entries: 16384 (order: 4, 65536 bytes).
Pentium-III serial number disabled..
Checking 386/387 coupling... OK, FPU using exception 16 error reporting..
Checking 'hlt' instruction... OK..
POSIX conformance testing by UNIFIX.
mtrr: v1.36 (20000221) Richard Gooch (rgooch(a)atnf.csiro.au).
Pentium-III serial number disabled..
CPU0: Intel Pentium III (Katmai) stepping 03.
per-CPU timeslice cutoff: 0.00 usecs..
Getting VERSION: 40011.
Getting VERSION: 40011.
Getting LVT0: 700.
Getting LVT1: 400.
enabled ExtINT on CPU#0.
ESR value before enabling vector: 00000000.
ESR value after enabling vector: 00000000.
kernel BUG at smpboot.c:864!
- James
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19 years, 7 months
- 2
- 1
AW: [OpenBIOS] another free bios project
by Winter Jörg
> ----------
> Von: gram wilson[SMTP:kwyjibo@flashcom.net]
> Antwort an: openbios(a)freiburg.linux.de
> Gesendet: Dienstag, 20. Juni 2000 17:45
> An: openbios(a)elvis.informatik.uni-freiburg.de
> Betreff: [OpenBIOS] another free bios project
>
> I just came across this project at SourceForge:
>
> Talkware TIARA, an Openbios/GRUB/PFORTH composite, BIOS replacement.
...
I cant find TIARA on the net. Can you post the url please ?
Thanx.
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19 years, 7 months
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