February 2009 - OpenBIOS - mail.coreboot.org

Incorrect implementation of b?branch?
by Mark Cave-Ayland March 2, 2009

March 2, 2009

Hi everyone, I've been spending some time over the past few weeks trying to get a Sparc64/Solaris disk image to boot under qemu, and as far as I can tell, the first reason that the code terminates incorrectly is because b?branch doesn't work. This can be demonstrated fairly easily using the following couple of Fcode programs. Note that while I'm working on Sparc64, I see the same issue on x86 OpenBIOS too. Example 1: b?branch with -1 on stack: ignore branch & abort CC \ offset16 10 \ b(lit) FF FF FF FF \ (-1) 14 00 04 \ b?branch 02 16 \ if false, abort 9D \ if true, display stack 00 \ end 0 > true to ?fcode-verbose ok 0 > here CC10FFFFFFFF1400 /n allot over ! ok 1 > here 0402169D00000000 /n allot over ! drop ok 1 > 1 byte-load byte-load: evaluating fcode at 0xffd9d128 fcode-table at 0xffdb7f90 offset16 [ 0xcc ] b(lit) [ 0x10 ] b?branch [ 0x14 ] abort [ 0x216 ] byte-load: exception caught! ok Example 2: b?branch with 0 on stack: skip abort, display stack CC \ offset16 10 \ b(lit) 00 00 00 00 \ (0) 14 00 04 \ b?branch 02 16 \ if false, abort 9D \ if true, display stack 00 \ end 0 > true to ?fcode-verbose ok 0 > here CC10000000001400 /n allot over ! ok 1 > here 0402169D00000000 /n allot over ! drop ok 1 > 1 byte-load byte-load: evaluating fcode at 0xffd9d128 fcode-table at 0xffdb7f90 offset16 [ 0xcc ] b(lit) [ 0x10 ] b?branch [ 0x14 ] abort [ 0x216 ] byte-load: exception caught! ok Okay, so did anyone notice the difference?! This led me to look into the definition of b?branch in forth/device/fcode.fs: \ b?branch ( continue? -- ) \ Conditional branch FCode. Followed by FCode-offset. : b?branch ['] do?branch , fcode-offset 0< if \ if we jump backwards, we can forsee where it goes resolve-dest else here 0 , then ; immediate By adding some extra debugging into b?branch, I can see that for the above Fcode, do?branch is *never* called, although it correct takes the "else" branch listed above. I'm still reasonably new to Forth, but AIUI, all the code above does is allocate one cell to store the xt of do?branch, and in the case of a forward branch, push the here location onto the stack and then store 0 into another allocated cell. This agrees with my investigation that shows that do?branch is never actually called. Given that this code is also missing a section that will read and discard Fcode-offset-2 bytes for a forward branch, I'm inclined to think that this code is just wrong. Can anyone else with any experience with this code comment upon this? ATB, Mark. -- Mark Cave-Ayland Sirius Corporation - The Open Source Experts http://www.siriusit.co.uk T: +44 870 608 0063

4 9

[PATCH] PPC64: Make OpenBIOS interrupt handlers 64bit aware v2
by Alexander Graf Feb. 28, 2009

Feb. 28, 2009

While booting a 64bit kernel, there is a small timeframe where OF and the kernel communicate with each other. Within that timeframe, DSI/ISI interrupts may occur, because some memory is not mapped yet. Right now in case that happens, we jump into the DSI/ISI interrupt handler which clobbers the high 32 bits of the kernel's registers. In order to circumvent that, let's save/restore all 64 bits of all kernel registers when we get a DSI/ISI interrupt. This patch enables a PPC64 Linux kernel to boot up to the point where it tries to set up the SLB entries (slbmte), which is not yet implemented in qemu. v2 implements handling for the HIOR register, bringing interrupt handlers to RAM. Signed-off-by: Alexander Graf <alex(a)csgraf.de>

2 1

r462 - in openbios-devel: arch/ppc/qemu include/ppc
by svn＠openbios.org Feb. 28, 2009

Feb. 28, 2009

Author: blueswirl Date: 2009-02-28 19:38:55 +0100 (Sat, 28 Feb 2009) New Revision: 462 Modified: openbios-devel/arch/ppc/qemu/init.c openbios-devel/arch/ppc/qemu/start.S openbios-devel/include/ppc/processor.h Log: Make OpenBIOS interrupt handlers 64bit aware v2 While booting a 64bit kernel, there is a small timeframe where OF and the kernel communicate with each other. Within that timeframe, DSI/ISI interrupts may occur, because some memory is not mapped yet. Right now in case that happens, we jump into the DSI/ISI interrupt handler which clobbers the high 32 bits of the kernel's registers. In order to circumvent that, let's save/restore all 64 bits of all kernel registers when we get a DSI/ISI interrupt. This patch enables a PPC64 Linux kernel to boot up to the point where it tries to set up the SLB entries (slbmte), which is not yet implemented in qemu. v2 implements handling for the HIOR register, bringing interrupt handlers to RAM. Signed-off-by: Alexander Graf <alex(a)csgraf.de> Modified: openbios-devel/arch/ppc/qemu/init.c =================================================================== --- openbios-devel/arch/ppc/qemu/init.c 2009-02-27 22:13:34 UTC (rev 461) +++ openbios-devel/arch/ppc/qemu/init.c 2009-02-28 18:38:55 UTC (rev 462) @@ -32,6 +32,7 @@ #include "libc/vsprintf.h" #define NO_QEMU_PROTOS #include "openbios/fw_cfg.h" +#include "ppc/processor.h" #define UUID_FMT "%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x" @@ -238,7 +239,27 @@ fword("finish-device"); } +/* In order to get 64 bit aware handlers that rescue all our + GPRs from getting truncated to 32 bits, we need to patch the + existing handlers so they jump to our 64 bit aware ones. */ static void +ppc64_patch_handlers(void) +{ + uint32_t *dsi = (uint32_t *)0x300UL; + uint32_t *isi = (uint32_t *)0x400UL; + + // Patch the first DSI handler instruction to: ba 0x2000 + *dsi = 0x48002002; + + // Patch the first ISI handler instruction to: ba 0x2200 + *isi = 0x48002202; + + // Invalidate the cache lines + asm ( "icbi 0, %0" : : "r"(dsi) ); + asm ( "icbi 0, %0" : : "r"(isi) ); +} + +static void cpu_970_init(const struct cpudef *cpu) { cpu_generic_init(cpu); @@ -249,6 +270,15 @@ fword("property"); fword("finish-device"); + + /* The 970 is a PPC64 CPU, so we need to activate + * 64bit aware interrupt handlers */ + + ppc64_patch_handlers(); + + /* The 970 also implements the HIOR which we need to set to 0 */ + + mtspr(S_HIOR, 0); } static const struct cpudef ppc_defs[] = { Modified: openbios-devel/arch/ppc/qemu/start.S =================================================================== --- openbios-devel/arch/ppc/qemu/start.S 2009-02-27 22:13:34 UTC (rev 461) +++ openbios-devel/arch/ppc/qemu/start.S 2009-02-28 18:38:55 UTC (rev 462) @@ -24,39 +24,155 @@ #define ILLEGAL_VECTOR( v ) .org __vectors + v ; bl trap_error ; #define VECTOR( v, dummystr ) .org __vectors + v ; vector__##v -#define EXCEPTION_PREAMBLE \ - mtsprg1 r1 ; /* scratch */ \ - mfsprg0 r1 ; /* exception stack in sprg0 */ \ - addi r1,r1,-80 ; /* push exception frame */ \ +/* We're trying to use the same code for the ppc32 and ppc64 handlers here. + * On ppc32 we only save/restore the registers, C considers volatile. + * + * On ppc64 on the other hand, we have to save/restore all registers, because + * all OF code is 32 bits, which only saves/restores the low 32 bits of the + * registers it clobbers. + */ + +#define EXCEPTION_PREAMBLE_TEMPLATE \ + mtsprg1 r1 ; /* scratch */ \ + mfsprg0 r1 ; /* exception stack in sprg0 */ \ +.ifc ULONG_SIZE, 8 ; \ + addi r1,r1,-(40 * ULONG_SIZE) ; /* push exception frame */ \ +.else ; \ + addi r1,r1,-(20 * ULONG_SIZE) ; /* push exception frame */ \ +.endif ; \ \ - stw r0,0(r1) ; /* save r0 */ \ + stl r0,(0 * ULONG_SIZE)(r1) ; /* save r0 */ \ mfsprg1 r0 ; \ - stw r0,4(r1) ; /* save r1 */ \ - stw r2,8(r1) ; /* save r2 */ \ - stw r3,12(r1) ; /* save r3 */ \ - stw r4,16(r1) ; \ - stw r5,20(r1) ; \ - stw r6,24(r1) ; \ - stw r7,28(r1) ; \ - stw r8,32(r1) ; \ - stw r9,36(r1) ; \ - stw r10,40(r1) ; \ - stw r11,44(r1) ; \ - stw r12,48(r1) ; \ + stl r0,(1 * ULONG_SIZE)(r1) ; /* save r1 */ \ + stl r2,(2 * ULONG_SIZE)(r1) ; /* save r2 */ \ + stl r3,(3 * ULONG_SIZE)(r1) ; /* save r3 */ \ + stl r4,(4 * ULONG_SIZE)(r1) ; \ + stl r5,(5 * ULONG_SIZE)(r1) ; \ + stl r6,(6 * ULONG_SIZE)(r1) ; \ + stl r7,(7 * ULONG_SIZE)(r1) ; \ + stl r8,(8 * ULONG_SIZE)(r1) ; \ + stl r9,(9 * ULONG_SIZE)(r1) ; \ + stl r10,(10 * ULONG_SIZE)(r1) ; \ + stl r11,(11 * ULONG_SIZE)(r1) ; \ + stl r12,(12 * ULONG_SIZE)(r1) ; \ +.ifc ULONG_SIZE, 8 ; \ + stl r13,(17 * ULONG_SIZE)(r1) ; \ + stl r14,(18 * ULONG_SIZE)(r1) ; \ + stl r15,(19 * ULONG_SIZE)(r1) ; \ + stl r16,(20 * ULONG_SIZE)(r1) ; \ + stl r17,(21 * ULONG_SIZE)(r1) ; \ + stl r18,(22 * ULONG_SIZE)(r1) ; \ + stl r19,(23 * ULONG_SIZE)(r1) ; \ + stl r20,(24 * ULONG_SIZE)(r1) ; \ + stl r21,(25 * ULONG_SIZE)(r1) ; \ + stl r22,(26 * ULONG_SIZE)(r1) ; \ + stl r23,(27 * ULONG_SIZE)(r1) ; \ + stl r24,(28 * ULONG_SIZE)(r1) ; \ + stl r25,(29 * ULONG_SIZE)(r1) ; \ + stl r26,(30 * ULONG_SIZE)(r1) ; \ + stl r27,(31 * ULONG_SIZE)(r1) ; \ + stl r28,(32 * ULONG_SIZE)(r1) ; \ + stl r29,(33 * ULONG_SIZE)(r1) ; \ + stl r30,(34 * ULONG_SIZE)(r1) ; \ + stl r31,(35 * ULONG_SIZE)(r1) ; \ +.endif ; \ \ mflr r0 ; \ - stw r0,52(r1) ; \ + stl r0,(13 * ULONG_SIZE)(r1) ; \ mfcr r0 ; \ - stw r0,56(r1) ; \ + stl r0,(14 * ULONG_SIZE)(r1) ; \ mfctr r0 ; \ - stw r0,60(r1) ; \ + stl r0,(15 * ULONG_SIZE)(r1) ; \ mfxer r0 ; \ - stw r0,64(r1) ; \ + stl r0,(16 * ULONG_SIZE)(r1) ; \ \ /* 76(r1) unused */ \ - addi r1,r1,-16 ; /* call conventions uses 0(r1) and 4(r1)... */ + addi r1,r1,-16 ; /* C ABI uses 0(r1) and 4(r1)... */ +#define EXCEPTION_EPILOGUE_TEMPLATE \ + addi r1,r1,16 ; /* pop ABI frame */ \ +\ + ll r0,(13 * ULONG_SIZE)(r1) ; \ + mtlr r0 ; \ + ll r0,(14 * ULONG_SIZE)(r1) ; \ + mtcr r0 ; \ + ll r0,(15 * ULONG_SIZE)(r1) ; \ + mtctr r0 ; \ + ll r0,(16 * ULONG_SIZE)(r1) ; \ + mtxer r0 ; \ +\ + ll r0,(0 * ULONG_SIZE)(r1) ; \ + ll r2,(2 * ULONG_SIZE)(r1) ; \ + ll r3,(3 * ULONG_SIZE)(r1) ; \ + ll r4,(4 * ULONG_SIZE)(r1) ; \ + ll r5,(5 * ULONG_SIZE)(r1) ; \ + ll r6,(6 * ULONG_SIZE)(r1) ; \ + ll r7,(7 * ULONG_SIZE)(r1) ; \ + ll r8,(8 * ULONG_SIZE)(r1) ; \ + ll r9,(9 * ULONG_SIZE)(r1) ; \ + ll r10,(10 * ULONG_SIZE)(r1) ; \ + ll r11,(11 * ULONG_SIZE)(r1) ; \ + ll r12,(12 * ULONG_SIZE)(r1) ; \ +.ifc ULONG_SIZE, 8 ; \ + ll r13,(17 * ULONG_SIZE)(r1) ; \ + ll r14,(18 * ULONG_SIZE)(r1) ; \ + ll r15,(19 * ULONG_SIZE)(r1) ; \ + ll r16,(20 * ULONG_SIZE)(r1) ; \ + ll r17,(21 * ULONG_SIZE)(r1) ; \ + ll r18,(22 * ULONG_SIZE)(r1) ; \ + ll r19,(23 * ULONG_SIZE)(r1) ; \ + ll r20,(24 * ULONG_SIZE)(r1) ; \ + ll r21,(25 * ULONG_SIZE)(r1) ; \ + ll r22,(26 * ULONG_SIZE)(r1) ; \ + ll r23,(27 * ULONG_SIZE)(r1) ; \ + ll r24,(28 * ULONG_SIZE)(r1) ; \ + ll r25,(29 * ULONG_SIZE)(r1) ; \ + ll r26,(30 * ULONG_SIZE)(r1) ; \ + ll r27,(31 * ULONG_SIZE)(r1) ; \ + ll r28,(32 * ULONG_SIZE)(r1) ; \ + ll r29,(33 * ULONG_SIZE)(r1) ; \ + ll r30,(34 * ULONG_SIZE)(r1) ; \ + ll r31,(35 * ULONG_SIZE)(r1) ; \ +.endif ; \ + ll r1,(1 * ULONG_SIZE)(r1) ; /* restore stack at last */ \ + rfi +// PPC32 + +#define ULONG_SIZE 4 +#define stl stw +#define ll lwz + +.macro EXCEPTION_PREAMBLE + EXCEPTION_PREAMBLE_TEMPLATE +.endm + +.macro EXCEPTION_EPILOGUE + EXCEPTION_EPILOGUE_TEMPLATE +.endm + +#undef ULONG_SIZE +#undef stl +#undef ll + +// PPC64 + +#define ULONG_SIZE 8 +#define stl std +#define ll ld + +.macro EXCEPTION_PREAMBLE_64 + EXCEPTION_PREAMBLE_TEMPLATE +.endm + +.macro EXCEPTION_EPILOGUE_64 + EXCEPTION_EPILOGUE_TEMPLATE +.endm + +#undef ULONG_SIZE +#undef stl +#undef ll + /************************************************************************/ /* vectors */ /************************************************************************/ @@ -68,32 +184,8 @@ b 1b exception_return: - addi r1,r1,16 // pop ABI frame + EXCEPTION_EPILOGUE - lwz r0,52(r1) - mtlr r0 - lwz r0,56(r1) - mtcr r0 - lwz r0,60(r1) - mtctr r0 - lwz r0,64(r1) - mtxer r0 - - lwz r0,0(r1) // restore r0 - lwz r2,8(r1) // restore r2 - lwz r3,12(r1) // restore r3 - lwz r4,16(r1) - lwz r5,20(r1) - lwz r6,24(r1) - lwz r7,28(r1) - lwz r8,32(r1) - lwz r9,36(r1) - lwz r10,40(r1) - lwz r11,44(r1) - lwz r12,48(r1) - lwz r1,4(r1) // restore r1 - rfi - .globl __divide_error __divide_error: trap_error: @@ -150,6 +242,22 @@ ILLEGAL_VECTOR( 0x1600 ) ILLEGAL_VECTOR( 0x1700 ) +VECTOR( 0x2000, "DSI_64" ): + EXCEPTION_PREAMBLE_64 + lis r3,HA(dsi_exception) + addi r3,r3,LO(dsi_exception) + mtctr r3 + bctrl + EXCEPTION_EPILOGUE_64 + +VECTOR( 0x2200, "ISI_64" ): + EXCEPTION_PREAMBLE_64 + lis r3,HA(isi_exception) + addi r3,r3,LO(isi_exception) + mtctr r3 + bctrl + EXCEPTION_EPILOGUE_64 + GLOBL(__vectors_end): /************************************************************************/ Modified: openbios-devel/include/ppc/processor.h =================================================================== --- openbios-devel/include/ppc/processor.h 2009-02-27 22:13:34 UTC (rev 461) +++ openbios-devel/include/ppc/processor.h 2009-02-28 18:38:55 UTC (rev 462) @@ -92,6 +92,7 @@ #define S_TBWL 284 /* Time base Upper/Lower (Writing) */ #define S_TBWU 285 #define S_PVR 287 /* Processor Version Register */ +#define S_HIOR 311 /* Hardware Interrupt Offset Register */ #define S_IBAT0U 528 #define S_IBAT0L 529 #define S_IBAT1U 530 @@ -400,4 +401,10 @@ #define SPRNUM_FLIP( v ) ( (((v)>>5) & 0x1f) | (((v)<<5) & 0x3e0) ) +/* C helpers */ + +#define __stringify_1(x) #x +#define __stringify(x) __stringify_1(x) +#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v)) + #endif /* _H_PROCESSOR */

1 0

[PATCH] PPC64: Make OpenBIOS interrupt handlers 64bit aware
by Alexander Graf Feb. 28, 2009

Feb. 28, 2009

While booting a 64bit kernel, there is a small timeframe where OF and the kernel communicate with each other. Within that timeframe, DSI/ISI interrupts may occur, because some memory is not mapped yet. Right now in case that happens, we jump into the DSI/ISI interrupt handler which clobbers the high 32 bits of the kernel's registers. In order to circumvent that, let's save/restore all 64 bits of all kernel registers when we get a DSI/ISI interrupt. In order to make use of this patch in qemu, a separate patch is required that makes qemu not run the interrupt handlers from ROM, but from RAM. It will follow on the qemu list shortly. This patch enables a PPC64 Linux kernel to boot up to the point where it tries to set up the SLB entries (slbmte), which is not yet implemented in qemu. Signed-off-by: Alexander Graf <alex(a)csgraf.de>

1 0

[PATCH] Enable support for PPC64 on qemu target v2
by Alexander Graf Feb. 28, 2009

Feb. 28, 2009

This patch enables OpenBIOS to initialize on PPC64, enabling support for -cpu 970fx. It gets up to the boot prompt and works rather good so far, though I haven't been able to run a kernel yet. For more recent PowerPC CPUs the PTE layout has changed, so we need to take that into account and create PTEs according to the new layout and at the new physical positions. v2 takes Laurent's comments into account Signed-off-by: Alexander Graf <alex(a)csgraf.de>

3 6

r461 - in openbios-devel: arch/ppc/qemu include
by svn＠openbios.org Feb. 27, 2009

Feb. 27, 2009

Author: laurent Date: 2009-02-27 23:13:34 +0100 (Fri, 27 Feb 2009) New Revision: 461 Modified: openbios-devel/arch/ppc/qemu/init.c openbios-devel/arch/ppc/qemu/mmutypes.h openbios-devel/arch/ppc/qemu/ofmem.c openbios-devel/include/ofmem.h Log: This patch enables OpenBIOS to initialize on PPC64, enabling support for -cpu 970fx. It gets up to the boot prompt and works rather good so far, though I haven't been able to run a kernel yet. For more recent PowerPC CPUs the PTE layout has changed, so we need to take that into account and create PTEs according to the new layout and at the new physical positions. Signed-off-by: Alexander Graf <alex(a)csgraf.de> Signed-off-by: Laurent Vivier <Laurent(a)vivier.eu> Modified: openbios-devel/arch/ppc/qemu/init.c =================================================================== --- openbios-devel/arch/ppc/qemu/init.c 2009-02-27 21:04:01 UTC (rev 460) +++ openbios-devel/arch/ppc/qemu/init.c 2009-02-27 22:13:34 UTC (rev 461) @@ -238,6 +238,19 @@ fword("finish-device"); } +static void +cpu_970_init(const struct cpudef *cpu) +{ + cpu_generic_init(cpu); + + PUSH(0); + fword("encode-int"); + push_str("reg"); + fword("property"); + + fword("finish-device"); +} + static const struct cpudef ppc_defs[] = { { .iu_version = 0x00040000, @@ -359,6 +372,18 @@ .clock_frequency = 0x1dcd6500, .initfn = cpu_g4_init, }, + { // XXX find out real values + .iu_version = 0x003C0000, + .name = "PowerPC,970FX", + .icache_size = 0x8000, + .dcache_size = 0x8000, + .icache_sets = 0x80, + .dcache_sets = 0x80, + .icache_block_size = 0x80, + .dcache_block_size = 0x80, + .clock_frequency = 0x1dcd6500, + .initfn = cpu_970_init, + }, }; static const struct cpudef * Modified: openbios-devel/arch/ppc/qemu/mmutypes.h =================================================================== --- openbios-devel/arch/ppc/qemu/mmutypes.h 2009-02-27 21:04:01 UTC (rev 460) +++ openbios-devel/arch/ppc/qemu/mmutypes.h 2009-02-27 22:13:34 UTC (rev 461) @@ -38,7 +38,28 @@ unsigned long pp:2; /* Page protection */ } mPTE_t; +typedef struct mPTE_64 { + uint32_t avpn_low; /* Abbreviated Virtual Page Number (unused) */ + uint32_t avpn:25; /* Abbreviated Virtual Page Number */ + uint32_t sw:4; /* Software Use */ + uint32_t :1; /* Reserved */ + uint32_t h:1; /* Hash algorithm indicator */ + uint32_t v:1; /* Entry is valid */ + uint32_t rpn_low; /* Real (physical) page number (unused) */ + uint32_t rpn:20; /* Real (physical) page number */ + uint32_t :2; /* Reserved */ + uint32_t ac:1; /* Address Compare*/ + uint32_t r:1; /* Referenced */ + uint32_t c:1; /* Changed */ + uint32_t w:1; /* Write-thru cache mode */ + uint32_t i:1; /* Cache inhibited */ + uint32_t m:1; /* Memory coherence */ + uint32_t g:1; /* Guarded */ + uint32_t n:1; /* No-Execute */ + uint32_t pp:2; /* Page protection */ +} mPTE_64_t; + typedef struct _mBATU { /* Upper part of BAT (all except 601) */ unsigned long bepi:15; /* Effective page index (virtual address) */ unsigned long :4; /* Unused */ Modified: openbios-devel/arch/ppc/qemu/ofmem.c =================================================================== --- openbios-devel/arch/ppc/qemu/ofmem.c 2009-02-27 21:04:01 UTC (rev 460) +++ openbios-devel/arch/ppc/qemu/ofmem.c 2009-02-27 22:13:34 UTC (rev 461) @@ -621,9 +621,75 @@ } static void -hash_page( ulong ea, ulong phys, int mode ) +hash_page_64( ulong ea, ulong phys, int mode ) { static int next_grab_slot=0; + uint64_t vsid_mask, page_mask, pgidx, hash; + uint64_t htab_mask, mask, avpn; + ulong pgaddr; + int i, found; + unsigned int vsid, vsid_sh, sdr, sdr_sh, sdr_mask; + mPTE_64_t *pp; + + vsid = (ea >> 28) + SEGR_BASE; + vsid_sh = 7; + vsid_mask = 0x00003FFFFFFFFF80ULL; + asm ( "mfsdr1 %0" : "=r" (sdr) ); + sdr_sh = 18; + sdr_mask = 0x3FF80; + page_mask = 0x0FFFFFFF; // XXX correct? + pgidx = (ea & page_mask) >> PAGE_SHIFT; + avpn = (vsid << 12) | ((pgidx >> 4) & 0x0F80);; + + hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; + htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F)); + mask = (htab_mask << sdr_sh) | sdr_mask; + pgaddr = sdr | (hash & mask); + pp = (mPTE_64_t *)pgaddr; + + /* replace old translation */ + for( found=0, i=0; !found && i<8; i++ ) + if( pp[i].avpn == avpn ) + found=1; + + /* otherwise use a free slot */ + for( i=0; !found && i<8; i++ ) + if( !pp[i].v ) + found=1; + + /* out of slots, just evict one */ + if( !found ) { + i = next_grab_slot + 1; + next_grab_slot = (next_grab_slot + 1) % 8; + } + i--; + { + mPTE_64_t p = { + // .avpn_low = avpn, + .avpn = avpn >> 7, + .h = 0, + .v = 1, + + .rpn = (phys & ~0xfff) >> 12, + .r = mode & (1 << 8) ? 1 : 0, + .c = mode & (1 << 7) ? 1 : 0, + .w = mode & (1 << 6) ? 1 : 0, + .i = mode & (1 << 5) ? 1 : 0, + .m = mode & (1 << 4) ? 1 : 0, + .g = mode & (1 << 3) ? 1 : 0, + .n = mode & (1 << 2) ? 1 : 0, + .pp = mode & 3, + }; + pp[i] = p; + } + + asm volatile( "tlbie %0" :: "r"(ea) ); +} + +static void +hash_page_32( ulong ea, ulong phys, int mode ) +{ + static int next_grab_slot=0; ulong *upte, cmp, hash1; int i, vsid, found; mPTE_t *pp; @@ -660,6 +726,22 @@ asm volatile( "tlbie %0" :: "r"(ea) ); } +static int is_ppc64(void) +{ + unsigned int pvr; + asm volatile("mfspr %0, 0x11f" : "=r" (pvr) ); + + return ((pvr >= 0x330000) && (pvr < 0x70330000)); +} + +static void hash_page( ulong ea, ulong phys, int mode ) +{ + if ( is_ppc64() ) + hash_page_64(ea, phys, mode); + else + hash_page_32(ea, phys, mode); +} + void dsi_exception( void ) { @@ -699,6 +781,7 @@ ofmem_t *ofmem = OFMEM; ulong sdr1, sr_base, msr; ulong hash_base; + ulong hash_mask = 0xffff0000; int i; memset(ofmem, 0, sizeof(ofmem_t)); @@ -706,7 +789,10 @@ /* SDR1: Storage Description Register 1 */ - hash_base = (ramsize - 0x00100000 - HASH_SIZE) & 0xffff0000; + if(is_ppc64()) + hash_mask = 0xfff00000; + + hash_base = (ramsize - 0x00100000 - HASH_SIZE) & hash_mask; memset((void *)hash_base, 0, HASH_SIZE); sdr1 = hash_base | ((HASH_SIZE-1) >> 16); asm volatile("mtsdr1 %0" :: "r" (sdr1) ); Modified: openbios-devel/include/ofmem.h =================================================================== --- openbios-devel/include/ofmem.h 2009-02-27 21:04:01 UTC (rev 460) +++ openbios-devel/include/ofmem.h 2009-02-27 22:13:34 UTC (rev 461) @@ -30,6 +30,8 @@ extern ulong ofmem_translate( ulong virt, int *ret_mode ); #ifdef CONFIG_PPC +#define PAGE_SHIFT 12 + ulong get_ram_size( void ); ulong get_ram_top( void ); ulong get_ram_bottom( void ); @@ -39,9 +41,6 @@ void ofmem_register( phandle_t ph ); #elif defined(CONFIG_SPARC32) #define PAGE_SHIFT 12 -#define PAGE_SIZE (1 << PAGE_SHIFT) -#define PAGE_MASK (~(PAGE_SIZE - 1)) -#define PAGE_ALIGN(addr) (((addr) + PAGE_SIZE - 1) & PAGE_MASK) /* arch/sparc32/lib.c */ struct mem; @@ -53,4 +52,10 @@ void *map_io(uint64_t pa, int size); #endif +#ifdef PAGE_SHIFT +#define PAGE_SIZE (1 << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE - 1)) +#define PAGE_ALIGN(addr) (((addr) + PAGE_SIZE - 1) & PAGE_MASK) +#endif + #endif /* _H_OFMEM */

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Re: [OpenBIOS] [Qemu-devel] How are we looking for a release?
by Blue Swirl Feb. 27, 2009

Feb. 27, 2009

On 2/27/09, Anthony Liguori <anthony(a)codemonkey.ws> wrote: > Hi, > > I wanted to see how we look from a release perspective. For x86, I think > things are looking pretty good. There are a couple outstanding patches that > need more review (like the CVE fix) but I think we'll be ready in a few > days. > > How are the other architectures looking? Are there any major bug fixes > people are working on? PPC is now fully converted to OpenBIOS, right? Yes, except for PREP. There are recent patches to make PPC64 work that should be committed in the coming days. That would be a nice addition but not critical. We have also discussed about making also an OpenBIOS (1.0) release, the previous release candidate (1.0RC1) is more than year old. It would be great to release Qemu with 1.0 OpenBIOS. Overall, there should be an update of the OpenBIOS images, otherwise Sparc32 and I think PPC32 are ready. Sparc64 will not be without major miracles in any case. PPC64 case may be interesting.

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r460 - openbios-devel/forth/device
by svn＠openbios.org Feb. 27, 2009

Feb. 27, 2009

Author: blueswirl Date: 2009-02-27 22:04:01 +0100 (Fri, 27 Feb 2009) New Revision: 460 Modified: openbios-devel/forth/device/fcode.fs Log: Fix fcode-offset sign extension problem (Mark Cave-Ayland) Modified: openbios-devel/forth/device/fcode.fs =================================================================== --- openbios-devel/forth/device/fcode.fs 2009-02-21 17:13:41 UTC (rev 459) +++ openbios-devel/forth/device/fcode.fs 2009-02-27 21:04:01 UTC (rev 460) @@ -80,6 +80,16 @@ fcode-c@ ; +\ fcode-num8-signed ( -- c ) ( F: c -- ) +\ get 8bit signed from FCode stream + +: fcode-num8-signed + fcode-num8 + dup 80 and 0> if + ff invert or + then + ; + \ fcode-num16 \ get 16bit from FCode stream @@ -87,6 +97,16 @@ fcode-num8 fcode-num8 swap bwjoin ; +\ fcode-num16-signed ( -- c ) ( F: c -- ) +\ get 16bit signed from FCode stream + +: fcode-num16-signed + fcode-num16 + dup 8000 and 0> if + ffff invert or + then + ; + \ fcode-num32 \ get 32bit from FCode stream @@ -111,9 +131,9 @@ : fcode-offset ( -- offset ) ?fcode-offset16 if - fcode-num16 + fcode-num16-signed else - fcode-num8 + fcode-num8-signed then ;

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[PATCH] Enable support for PPC64 on qemu target
by Alexander Graf Feb. 26, 2009

Feb. 26, 2009

This patch enables OpenBIOS to initialize on PPC64, enabling support for -cpu 970fx. It gets up to the boot prompt and works rather good so far, though I haven't been able to run a kernel yet. For more recent PowerPC CPUs the PTE layout has changed, so we need to take that into account and create PTEs according to the new layout and at the new physical positions. Signed-off-by: Alexander Graf <alex(a)csgraf.de>

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Re: [OpenBIOS] [Qemu-devel] building openbios-qemu.elf?
by Hollis Blanchard Feb. 26, 2009

Feb. 26, 2009

On Tue, 2009-02-24 at 22:27 +0200, Blue Swirl wrote: > > Would this patch fix the problem? Doesn't look like it. After patching and make clean, I see the same warning from strip, and basically the same output: # tail obj-ppc/build.log [...] powerpc-440-linux-gnu-ld --warn-common -N -T ../arch/ppc/qemu/ldscript target/arch/ppc/qemu/start.o target/arch/ppc/timebase.o libqemu.a libbootstrap.a libdrivers.a libmodules.a liblibc.a libfs.a libgcc.a -o openbios-qemu.elf powerpc-440-linux-gnu-nm openbios-qemu.elf | sort > ./openbios-qemu.syms cp openbios-qemu.elf openbios-qemu.elf.nostrip powerpc-440-linux-gnu-strip openbios-qemu.elf BFD: stzD2J6q: warning: allocated section `.bss' not in segment BFD: stzD2J6q: warning: allocated section `.sbss' not in segment # readelf -l obj-ppc/openbios-qemu.elf* File: obj-ppc/openbios-qemu.elf Elf file type is EXEC (Executable file) Entry point 0xfff08000 There are 3 program headers, starting at offset 52 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000094 0xfff00000 0xfff00000 0x100000 0x100000 RWE 0x4 LOAD 0x100094 0xfffffffc 0xfffffffc 0x00004 0x00004 R E 0x1 GNU_STACK 0x000000 0x00000000 0x00000000 0x00000 0x00000 RWE 0x4 Section to Segment mapping: Segment Sections... 00 .text.vectors .text .rodata .data .bss .sbss 01 .romentry 02 File: obj-ppc/openbios-qemu.elf.nostrip Elf file type is EXEC (Executable file) Entry point 0xfff08000 There are 3 program headers, starting at offset 52 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000094 0xfff00000 0xfff00000 0x42044 0x4bcb4 RWE 0x4 LOAD 0x0420d8 0xfffffffc 0xfffffffc 0x00004 0x00004 R E 0x1 GNU_STACK 0x000000 0x00000000 0x00000000 0x00000 0x00000 RWE 0x4 Section to Segment mapping: Segment Sections... 00 .text.vectors .text .rodata .data 01 .romentry 02 -- Hollis Blanchard IBM Linux Technology Center

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