RE: [OpenBIOS] l440gx+ nvram writing ... the BUD

[Wallace I. Kroeker]

Ron,

You may be well along this path anyway but this may be of some use.

So after wandering through the documentation abyss this is what I've gleaned
so far:
> From a product spec. in this case "Enterprise Server Group Intel N440BX

Server Technical Product Specification" (I think I saw 	a similar one for a
440gx based product ...) there is a BUD.  They have a FLASH_PE_L GPO24
(General Purpose Output from the PIIX4) and DIS_NON_FLASH_SMI GPO25.  If you
look at the inputs to the BUD the DIS_NON_FLASH_SMI goes into pin 8 on the
BUD and seems to control the secure FLASH programming.  While looking there
you can see that there is a EN_SMI_L line that goes into the BUD this
enables SMI generation (you would want to disable this before trying to
write to the FLASH again).  The EN_SMI_L is driven by GPIO bit 9.  Also on
the BUD, pin 48 is driven by the FLASH_PE_L  (if you don't disable SMI
generation I suspect you just get another SMI...).

So it would seem that for THIS system once you are in the SMI interrupt that
should be able to set various IO signals on the PIIX4 to disable SMI and
enable writing to the Flash.

Now I would suspect that your motherboard would be similar to one like this
but then this is Intel we're talking about ...

Wallace
> -----Original Message-----
> From:	Ronald G. Minnich [SMTP:[e-mail]]
> Sent:	Tuesday, February 08, 2000 12:09 PM
> To:	'[e-mail]'
> Subject:	RE: [OpenBIOS] l440gx+ nvram writing ...
>
> On Tue, 8 Feb 2000, Wallace I. Kroeker wrote:
> > Ron,
> > Have a look at this ( I had to do a search of all the intel site) but it
> > does give a description of how
> > their Flash works (flow charts etc).  It also give references to source
>
> code
> > but I'm not sure if this is freely available or not.
> > Professional I/O Application
> > Developer's Kit
> > User's Manual
> > August 1998
>
> Yup, I've got that. It's worth getting. Where we're stopped at present is
> the BUD on the l440gx+, though.
>
> thanks
>
> ron
>
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> with 'unsubscribe openbios' in the body of the message

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l440gx+ nvram writing ... the BUD

[Ronald G. Minnich]

Thanks for the info. I'm wondering ... you can enable flash writing in the
PIIX4e. It's just one lousy bit. So is the sum total of the work involved
getting the BUD to NOT interrupt when you write? that would be
interesting.

Another data point. I am trying to run Intel's own IFLASH utility. Guess
what ... it can't write flash either!

This is a mess!

ron

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l440gx+ nvram writing ... the BUD

[Steve and Sue]

Ron,

this may be veering in the wrong direction, but I've been thinking this one
over and I can't help thinking there must be some way to bypass the BUD
logic (after all, it's only there to stop rogue software updating the flash,
not determined hardware hackers).

Is it possible to lift a pin (pins) on the BUD that is driven by the PIIX4
and connect this through to the appropriate, lifted pin (pins) on the Flash?

Sorry but I'm not up on the hardware side and you seem to have some
technical docs. that may help with this (I don't have the chipset data with
me). I have to update Flash memory through the PIIX4 as a day-to-day
activity and for my board the process is not as involved as on your
motherboard - hence the bypass idea.

Steve

----- Original Message -----
From: Ronald G. Minnich 
To: '[e-mail]' 
Sent: 08 February 2000 23:33
Subject: RE: [OpenBIOS] l440gx+ nvram writing ... the BUD
> Thanks for the info. I'm wondering ... you can enable flash writing in the
> PIIX4e. It's just one lousy bit. So is the sum total of the work involved
> getting the BUD to NOT interrupt when you write? that would be
> interesting.
>
> Another data point. I am trying to run Intel's own IFLASH utility. Guess
> what ... it can't write flash either!
>
> This is a mess!
>
> ron
>
> To unsubscribe: send mail to [e-mail]
> with 'unsubscribe openbios' in the body of the message

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l440gx+ nvram writing ... the BUD

[Ronald G. Minnich]

On Wed, 9 Feb 2000, Steve and Sue wrote:
> Is it possible to lift a pin (pins) on the BUD that is driven by the PIIX4
> and connect this through to the appropriate, lifted pin (pins) on the Flash?

not doable, we have 128 of these now and will soon have lots more. The
PIIX4 is a micro Ball Grid Array package, which makes it much worse.
> me). I have to update Flash memory through the PIIX4 as a day-to-day
> activity and for my board the process is not as involved as on your
> motherboard - hence the bypass idea.

What tool are you using for this?

Anyways I'm getting closer ...

ron

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l440gx+ nvram writing ... the BUD

[Steve and Sue]

----- Original Message -----
From: Ronald G. Minnich 
To: 
Sent: 10 February 2000 15:15
Subject: Re: [OpenBIOS] l440gx+ nvram writing ... the BUD
> What tool are you using for this?

It's a home-spun flash writer, nothing special and certainly not using SMI.
The hardware is designed by the company I work for and has no special
hardware protection - just throw the write-protect bit in the PIIX and go.

Steve.

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