Am 11.10.2010 um 11:16 schrieb Alexander Graf:
Andreas Färber wrote:
Am 11.10.2010 um 04:53 schrieb Segher Boessenkool:
- mfpvr r14 /* check if ppc64 */
- li r15, 4
- srw r14, r14, r15 /* >> 4 */
srwi 14,14,4
but you actually want to shift 16, not 4.
Oops!
- cmplwi r14, 0x33
- blt 1f
- cmplwi r14, 0x7033
- bge 1f
This is too simplistic.
Are you saying the original is_ppc64() function I transformed into assembler code is wrong, too?
static int is_ppc64(void) { unsigned int pvr; asm volatile("mfspr %0, 0x11f" : "=r" (pvr) );
return ((pvr >= 0x330000) && (pvr < 0x70330000)); }
In here we don't know if SF=1 because we forcefully disable it always.
Ah! You mean this?
li r0, 0 mtmsr r0
That would mean I don't need a 64-bit RTAS unless AIX sets SF=1. :)
Here's something that detects whether the CPU is currently in 64-bit mode, without using 64-bit-only instructions:
lis 3,0x4000 add 3,3,3 addc 3,3,3 adde 3,3,3 cmplwi 3,0 beq 64bit bne 32bit
Thanks! I'll give it a try.
Anyway, can't you always align to 128 bytes, and create one frame for the 64-bit ABI? Or do you really want to save those few bytes...
As for "those few bytes", I guess I mixed up bits and hexadecimal digits once again. An example:
-m 1024
RAM 0..0x40000000 OpenBIOS @ 0x3ff00000 Hash table @ 0x3fef0000 vs. 0x3fe00000
We'd be wasting 960 KiB. If that's acceptable, it'll simplify the code a little of course.
I'd personally say go for simplicity.
On second thoughts, unfortunately I don't think 32-bit CPUs can handle clrrdi, so we'd still need the distinction here since we're subtracting from RAM size.
Or better, we'd need a distinction at the original setup of r1, so that it fits into the low 32 or 31 bits in the first place. Currently everything over -m 2048 would overlap with ISA and at some point PCI and fw_cfg. Memory would probably have to become non-contiguous then, breaking some more assumptions...
Andreas