Author: wmb Date: 2007-04-28 00:21:41 +0200 (Sat, 28 Apr 2007) New Revision: 332
Modified: cpu/x86/pc/olpc/chipinit.fth cpu/x86/pc/olpc/romreset.bth cpu/x86/pc/olpc/vsapci.fth Log: OLPC - Increased the size of the frame buffer from 8M to 16M for the LX version, because 2M is used for the graphics command buffer and the remaining 6M is not enough for the pixmaps.
Modified: cpu/x86/pc/olpc/chipinit.fth =================================================================== --- cpu/x86/pc/olpc/chipinit.fth 2007-04-27 22:18:48 UTC (rev 331) +++ cpu/x86/pc/olpc/chipinit.fth 2007-04-27 22:21:41 UTC (rev 332) @@ -634,7 +634,7 @@ \ write_vg_32(DC_DV_CTL, mVal.high);
\ The base address of the frame buffer in physical memory - 1030 pl@ 4 and if h# 77e.0000 else h# f7e.0000 then + h# 1808 msr@ drop 4 lshift h# fff invert and ( fb-pa ) h# 88 dc-base + l! \ DV_CTL register, undocumented
\ hw_fb_map_init(PCI_FB_BASE);
Modified: cpu/x86/pc/olpc/romreset.bth =================================================================== --- cpu/x86/pc/olpc/romreset.bth 2007-04-27 22:18:48 UTC (rev 331) +++ cpu/x86/pc/olpc/romreset.bth 2007-04-27 22:21:41 UTC (rev 332) @@ -124,12 +124,12 @@ \ sdram_set_spdregisters(),auto.c
\ The LX devel board has only 512M ROM, but assigning 1M of address space is harmless - 25fff002.10f80000. 1808 set-msr \ 1M ROM at fff0.0000, system RAM limit at 0f80.0000 - 2000000f.7ff00100. 10000028 set-msr \ Top of memory at 0f7f.ffff - 212800fd.7fffd000. 10000029 set-msr \ Frame buffer at PA fd00.0000 maps to RAM at 0f80.0000 + 25fff002.10f00000. 1808 set-msr \ 1M ROM at fff0.0000, system RAM limit at 0f00.0000 + 2000000e.fff00100. 10000028 set-msr \ Top of memory at 0eff.ffff + 212000fd.ffffd000. 10000029 set-msr \ Frame buffer at PA fd00.0000 maps to RAM at 0f00.0000 10076013.00005040. 20000018 set-msr \ DIMM1 empty, DIMM0 256 MB, 1 module bank, 8K pages - 2000000f.7ff00100. 4000002c set-msr \ DMA to memory from 1M to RAM limit at 0f80.0000 - 0f7ff000.00100130. 50002019 set-msr \ PCI DMA to memory from 1M to RAM limit at 0f80.0000 + 2000000e.fff00100. 4000002c set-msr \ DMA to memory from 1M to RAM limit at 0f00.0000 + 0efff000.00100130. 50002019 set-msr \ PCI DMA to memory from 1M to RAM limit at 0f00.0000
\ 20000019 rmsr \ SDRAM timing and mode program 00000000.2814d352. 00001981 set-msr \ Memory delay values
Modified: cpu/x86/pc/olpc/vsapci.fth =================================================================== --- cpu/x86/pc/olpc/vsapci.fth 2007-04-27 22:18:48 UTC (rev 331) +++ cpu/x86/pc/olpc/vsapci.fth 2007-04-27 22:21:41 UTC (rev 332) @@ -199,6 +199,7 @@ \ Amend the fake PCI headers for the LX settings h# 281022 nb-hdr h# 20 + l! \ Vendor/device ID - AMD
+ h# ff000000 gxfb-hdr h# 0 + l! \ BAR0 MASK - FB h# ffffc000 gxfb-hdr h# 10 + l! \ BAR4 MASK - VIP h# 20811022 gxfb-hdr h# 20 + l! \ Vendor/device ID - AMD h# fe00c000 gxfb-hdr h# 40 + l! \ BAR4 address - VIP