Milax (OpenSolaris) checks to see if this is the case, and panics on boot if the E bit isn't set for PROM mappings.
Signed-off-by: Mark Cave-Ayland mark.cave-ayland@ilande.co.uk --- arch/sparc64/entry.S | 6 +++--- arch/sparc64/ofmem_sparc64.c | 2 +- arch/sparc64/spitfire.h | 1 + 3 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/sparc64/entry.S b/arch/sparc64/entry.S index 47d1139..224a53b 100644 --- a/arch/sparc64/entry.S +++ b/arch/sparc64/entry.S @@ -148,7 +148,7 @@ entry: srlx %g5, 19, %g6 ! %g6 = # of 512k .bss pages set 0xc0000000, %g3 sllx %g3, 32, %g3 - or %g3, 0x76, %g3 + or %g3, 0x7e, %g3 ! valid, 512k, locked, cacheable(I/E/C), priv, writable set 48, %g7 1: stxa %g4, [%g7] ASI_DMMU ! vaddr = _data + N * 0x80000, ctx=0 @@ -173,7 +173,7 @@ entry: 1: stxa %g4, [%g7] ASI_DMMU ! vaddr = _rodata, ctx=0 set 0xc0000000, %g3 sllx %g3, 32, %g3 - or %g3, 0x74, %g3 + or %g3, 0x7c, %g3 or %l2, %g3, %g3 ! valid, 512k, locked, cacheable(I/E/C), priv ! paddr = _rodata + N * 0x10000 @@ -197,7 +197,7 @@ entry: 1: stxa %g4, [%g7] ASI_IMMU ! vaddr = _start, ctx=0 set 0xc0000000, %g3 sllx %g3, 32, %g3 - or %g3, 0x74, %g3 + or %g3, 0x7c, %g3 or %l2, %g3, %g3 ! valid, 512k, locked, cacheable(I/E/C), priv ! paddr = _start + N * 0x80000 diff --git a/arch/sparc64/ofmem_sparc64.c b/arch/sparc64/ofmem_sparc64.c index ba4a053..06a16b1 100644 --- a/arch/sparc64/ofmem_sparc64.c +++ b/arch/sparc64/ofmem_sparc64.c @@ -215,7 +215,7 @@ ucell ofmem_arch_default_translation_mode( phys_addr_t phys ) ucell ofmem_arch_io_translation_mode( phys_addr_t phys ) { /* Writable, privileged and not locked */ - return SPITFIRE_TTE_CV | SPITFIRE_TTE_WRITABLE | SPITFIRE_TTE_PRIVILEGED; + return SPITFIRE_TTE_CV | SPITFIRE_TTE_WRITABLE | SPITFIRE_TTE_PRIVILEGED | SPITFIRE_TTE_EFFECT; }
/* Architecture-specific OFMEM helpers */ diff --git a/arch/sparc64/spitfire.h b/arch/sparc64/spitfire.h index 4a951b1..15dc378 100644 --- a/arch/sparc64/spitfire.h +++ b/arch/sparc64/spitfire.h @@ -38,6 +38,7 @@ /* translation table entry bits */ #define SPITFIRE_TTE_WRITABLE 0x02 #define SPITFIRE_TTE_PRIVILEGED 0x04 +#define SPITFIRE_TTE_EFFECT 0x08 #define SPITFIRE_TTE_CV 0x10 #define SPITFIRE_TTE_CP 0x20 #define SPITFIRE_TTE_LOCKED 0x40