OpenBIOS May 2014

openbios@openbios.org

10 participants
35 discussions

[commit] r1306 - in trunk/openbios-devel: arch/ppc/qemu drivers
by repository service 30 May '14

30 May '14

Author: agraf Date: Fri May 30 14:11:44 2014 New Revision: 1306 URL: http://tracker.coreboot.org/trac/openbios/changeset/1306 Log: PPC: Pass real tbfreq to udelay The IDE code waits for some operations to finish within a certain amount of time. That waiting code delays based on the timebase, but doesn't know about the frequency of the timebase. In cases where we know the frequency - like via QEMU's fwcfg interface - base the calculation on that frequency value. This fixes issues where … [View More]

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[PATCH] arch/ppc/qemu: Moved exception handlers from beginning of RAM
by BALATON Zoltan 29 May '14

29 May '14

Do not put exception handler routines between 0x00-0xff as some OSes use this area for their own purposes and can corrupt them. (In particular MorphOS writes to 0x80 during boot). This patch frees up this area by moving the routines that were there higher. Signed-off-by: BALATON Zoltan <balaton(a)eik.bme.hu> --- This replaces my previous attempt (Use exception vectors from ROM instead of copying them to page zero) as that relied on the MSR[IP] bit that was found not to be generally … [View More]

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Re: [OpenBIOS] [PATCH] Use exception vectors from ROM instead of copying them to page zero
by BALATON Zoltan 28 May '14

28 May '14

On Mon, 26 May 2014, Mark Cave-Ayland wrote: > Just as a general comment: I know that some OSs using Sun's PROM expect > to be able to write to the trap table (which is why it is copied to RAM) > so you'd need to check this thoroughly. Or, if MSR_IP uses virtual > addresses you could do some MMU twiddling so that the virtual address > actually points into a safe area of RAM rather than ROM. As far as I understand MSR_IP just selects between exception vectors at 0x0 or … [View More]

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Re: [OpenBIOS] [PATCH 2/2] arch/ppc/qemu: simplify MMU exception handlers
by Alexander Graf 28 May '14

28 May '14

On 28.05.14 21:07, BALATON Zoltan wrote: > Remove duplicated code from the handlers for DSI and ISI exceptions. > > Signed-off-by: BALATON Zoltan <balaton(a)eik.bme.hu> I can't say I'm a big fan of this patch. Jumping from one handler into another is a big red flag to me. If you really think it's worth to consolidate these 3 instructions, please create a separate call_exception_handler function that you call from the DSI and ISI handler. Alex > --- > openbios-devel/… [View More]

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Re: [OpenBIOS] [PATCH 1/2] arch/ppc/qemu: Moved exception handlers from beginning of RAM
by Alexander Graf 28 May '14

28 May '14

On 28.05.14 21:03, BALATON Zoltan wrote: > Do not put exception handler routines between 0x00-0xff as some OSes > use this area for their own purposes and can corrupt them. (In > particular MorphOS writes to 0x80 during boot). This patch frees up > this area by moving the routines that were there higher. > > Signed-off-by: BALATON Zoltan <balaton(a)eik.bme.hu> Thanks, applied to OpenBIOS. Alex

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[commit] r1305 - trunk/openbios-devel/arch/ppc/qemu
by repository service 28 May '14

28 May '14

Author: agraf Date: Thu May 29 00:15:33 2014 New Revision: 1305 URL: http://tracker.coreboot.org/trac/openbios/changeset/1305 Log: arch/ppc/qemu: Moved exception handlers from beginning of RAM Do not put exception handler routines between 0x00-0xff as some OSes use this area for their own purposes and can corrupt them. (In particular MorphOS writes to 0x80 during boot). This patch frees up this area by moving the routines that were there higher. Signed-off-by: BALATON Zoltan <balaton(a)… [View More]

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[PATCH] Use exception vectors from ROM instead of copying them to page zero
by BALATON Zoltan 28 May '14

28 May '14

Instead of copying the exception vectors from ROM to page zero use the Interrupt Prefix bit of the CPU to use the vectors at the ROM address. This simplifies the startup routine a little bit and avoids using addresses that can be overwritten by clients. In particular MorphOS writes to address 0x80 during boot which corrupted the exception return code causing a crash. Signed-off-by: BALATON Zoltan <balaton(a)eik.bme.hu> --- Index: openbios-devel/arch/ppc/qemu/start.S =====================… [View More]

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[PATCH 2/2] arch/ppc/qemu: simplify MMU exception handlers
by BALATON Zoltan 28 May '14

28 May '14

Remove duplicated code from the handlers for DSI and ISI exceptions. Signed-off-by: BALATON Zoltan <balaton(a)eik.bme.hu> --- openbios-devel/arch/ppc/qemu/start.S | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/openbios-devel/arch/ppc/qemu/start.S b/openbios-devel/arch/ppc/qemu/start.S index ae2fd53..5aa8c62 100644 --- a/openbios-devel/arch/ppc/qemu/start.S +++ b/openbios-devel/arch/ppc/qemu/start.S @@ -359,18 +359,14 @@ VECTOR( 0x2200, "ISI_64" ): real_dsi: … [View More]

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[PATCH 1/2] arch/ppc/qemu: Moved exception handlers from beginning of RAM
by BALATON Zoltan 28 May '14

28 May '14

Do not put exception handler routines between 0x00-0xff as some OSes use this area for their own purposes and can corrupt them. (In particular MorphOS writes to 0x80 during boot). This patch frees up this area by moving the routines that were there higher. Signed-off-by: BALATON Zoltan <balaton(a)eik.bme.hu> --- openbios-devel/arch/ppc/qemu/start.S | 32 +++++++++++++------------------- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/openbios-devel/arch/ppc/qemu/start.S … [View More]

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[PATCH v2] arch/ppc/qemu: Clean up and add more cpu infos
by BALATON Zoltan 25 May '14

25 May '14

Removed unused clock_frequency member from struct cpudef which is get from FW_CFG and added bus-frequency property to complete the frequency properties. Also added tlb infos to cpudef (with values only for G4 currently as I have no data for other CPUs). Signed-off-by: BALATON Zoltan <balaton(a)eik.bme.hu> --- v2: Get bus-frequency from FW_CFG similarly to clock-frequency and tb-frequency (corresponding patch submitted to QEMU) --- Index: openbios-devel/arch/ppc/qemu/init.c =========… [View More]========================================================== --- openbios-devel/arch/ppc/qemu/init.c (revision 1286) +++ openbios-devel/arch/ppc/qemu/init.c (working copy) @@ -44,7 +44,7 @@ int icache_size, dcache_size; int icache_sets, dcache_sets; int icache_block_size, dcache_block_size; - int clock_frequency; + int tlb_sets, tlb_size; void (*initfn)(const struct cpudef *cpu); }; @@ -269,6 +269,18 @@ push_str("i-cache-block-size"); fword("property"); + if(cpu->tlb_size) { + PUSH(cpu->tlb_sets); + fword("encode-int"); + push_str("tlb-sets"); + fword("property"); + + PUSH(cpu->tlb_size); + fword("encode-int"); + push_str("tlb-size"); + fword("property"); + } + PUSH(fw_cfg_read_i32(FW_CFG_PPC_TBFREQ)); fword("encode-int"); push_str("timebase-frequency"); @@ -279,6 +291,11 @@ push_str("clock-frequency"); fword("property"); + PUSH(fw_cfg_read_i32(FW_CFG_PPC_BUSFREQ)); + fword("encode-int"); + push_str("bus-frequency"); + fword("property"); + push_str("running"); fword("encode-string"); push_str("state"); @@ -391,7 +408,8 @@ .dcache_sets = 0x80, .icache_block_size = 0x20, .dcache_block_size = 0x20, - .clock_frequency = 0x07de2900, + .tlb_sets = 0x00, + .tlb_size = 0x00, .initfn = cpu_604_init, }, { // XXX find out real values @@ -403,7 +421,8 @@ .dcache_sets = 0x80, .icache_block_size = 0x20, .dcache_block_size = 0x20, - .clock_frequency = 0x07de2900, + .tlb_sets = 0x00, + .tlb_size = 0x00, .initfn = cpu_604_init, }, { // XXX find out real values @@ -415,7 +434,8 @@ .dcache_sets = 0x80, .icache_block_size = 0x20, .dcache_block_size = 0x20, - .clock_frequency = 0x07de2900, + .tlb_sets = 0x00, + .tlb_size = 0x00, .initfn = cpu_604_init, }, { // XXX find out real values @@ -427,7 +447,8 @@ .dcache_sets = 0x80, .icache_block_size = 0x20, .dcache_block_size = 0x20, - .clock_frequency = 0x14dc9380, + .tlb_sets = 0x00, + .tlb_size = 0x00, .initfn = cpu_750_init, }, { @@ -439,7 +460,8 @@ .dcache_sets = 0x80, .icache_block_size = 0x20, .dcache_block_size = 0x20, - .clock_frequency = 0x14dc9380, + .tlb_sets = 0x00, + .tlb_size = 0x00, .initfn = cpu_750_init, }, { // XXX find out real values @@ -451,7 +473,8 @@ .dcache_sets = 0x80, .icache_block_size = 0x20, .dcache_block_size = 0x20, - .clock_frequency = 0x14dc9380, + .tlb_sets = 0x00, + .tlb_size = 0x00, .initfn = cpu_750_init, }, { // XXX find out real values @@ -463,7 +486,8 @@ .dcache_sets = 0x80, .icache_block_size = 0x20, .dcache_block_size = 0x20, - .clock_frequency = 0x14dc9380, + .tlb_sets = 0x00, + .tlb_size = 0x00, .initfn = cpu_750_init, }, { // XXX find out real values @@ -475,7 +499,8 @@ .dcache_sets = 0x80, .icache_block_size = 0x20, .dcache_block_size = 0x20, - .clock_frequency = 0x14dc9380, + .tlb_sets = 0x00, + .tlb_size = 0x00, .initfn = cpu_750_init, }, { // XXX find out real values @@ -487,7 +512,8 @@ .dcache_sets = 0x80, .icache_block_size = 0x20, .dcache_block_size = 0x20, - .clock_frequency = 0x14dc9380, + .tlb_sets = 0x00, + .tlb_size = 0x00, .initfn = cpu_750_init, }, { @@ -499,7 +525,8 @@ .dcache_sets = 0x80, .icache_block_size = 0x20, .dcache_block_size = 0x20, - .clock_frequency = 0x1dcd6500, + .tlb_sets = 0x40, + .tlb_size = 0x80, .initfn = cpu_g4_init, }, { @@ -511,7 +538,8 @@ .dcache_sets = 0x80, .icache_block_size = 0x80, .dcache_block_size = 0x80, - .clock_frequency = 0x5f5e1000, + .tlb_sets = 0x00, + .tlb_size = 0x00, .initfn = cpu_970_init, }, { // XXX find out real values @@ -523,7 +551,8 @@ .dcache_sets = 0x80, .icache_block_size = 0x80, .dcache_block_size = 0x80, - .clock_frequency = 0x1dcd6500, + .tlb_sets = 0x00, + .tlb_size = 0x00, .initfn = cpu_970_init, }, { @@ -535,7 +564,8 @@ .dcache_sets = 0x40, .icache_block_size = 0x80, .dcache_block_size = 0x80, - .clock_frequency = 0x629b4940, + .tlb_sets = 0x00, + .tlb_size = 0x00, .initfn = cpu_970_init, }, }; [View Less]

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