SerialICE November 2012

serialice@serialice.com

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41 discussions

Patch merged into serialice/master: a600475 Add APIC memory spaces
by gerrit＠coreboot.org 07 Nov '12

07 Nov '12

the following patch was just integrated into master: commit a6004751a3adba257833e581b20cdafd1f6e5787 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 28 11:54:51 2012 +0200 Add APIC memory spaces To be precise, the base addresses of APICs are actually configurable in either PCI config space or an MSR. For now, this decodes at the commonly used and fixed base address for both IOAPIC and LAPIC. For LAPIC, Startup-IPI is replaced with INIT IPI to prevent AP CPUs from attempting to execute code from Flash. Change-Id: Icdbb8cd460bba440b466860f7e92f8a83cdb9d00 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/1648 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Sun Oct 28 22:40:57 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Nov 6 22:05:45 2012, giving +2 See http://review.coreboot.org/1648 for details. -gerrit

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Patch merged into serialice/master: e4517d1 Add superio filtering
by gerrit＠coreboot.org 07 Nov '12

07 Nov '12

the following patch was just integrated into master: commit e4517d19a4c9c411895a93cc7f224ef5e438f9e2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 28 11:32:48 2012 +0200 Add superio filtering Decoder is able to pretty-print the config cycles to port 0x2e/0x4e and activate new IO regions. One should provide a map of LDN functions with the size of each IO region as part of the mainboard script. Change-Id: I976f43818b43a30db97b4e679de04e399f691b97 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/1647 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Sun Oct 28 22:29:42 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Nov 6 22:05:23 2012, giving +2 See http://review.coreboot.org/1647 for details. -gerrit

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Patch merged into serialice/master: 7ffaf4e Add legacy PC80 devices in IO space
by gerrit＠coreboot.org 07 Nov '12

07 Nov '12

the following patch was just integrated into master: commit 7ffaf4e5e938b45c70fd0a397870dcf19e941d0a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 28 11:13:35 2012 +0200 Add legacy PC80 devices in IO space These devices appear at fixed IO addresses and are mostly implemented in the southbridge chip. Change-Id: I4a20058e0cbc31f1b5777fe99966c0499909a553 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/1646 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Sun Oct 28 22:18:59 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Nov 6 22:04:55 2012, giving +2 See http://review.coreboot.org/1646 for details. -gerrit

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Patch merged into serialice/master: e0776f4 Add PCI config register filters
by gerrit＠coreboot.org 07 Nov '12

07 Nov '12

the following patch was just integrated into master: commit e0776f44771c1b60ce4aed23f23723319737eed2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 28 11:02:01 2012 +0200 Add PCI config register filters Config register decoding is enabled by default for IO 0xcf8-0xcff access only. To enable decode of MMIO style access, it is necessary to add chipset-specific hook to set base of PCI MMIO config space. At the moment modifying transactions is limited to conditionally dropping a write before it reaches target. Change-Id: Ib4241701dcbd5d617749f1223141171eb8093000 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/1645 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Sun Oct 28 22:08:15 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Nov 6 22:04:18 2012, giving +2 See http://review.coreboot.org/1645 for details. -gerrit

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Patch merged into serialice/master: 1ec778e Add log replayer
by gerrit＠coreboot.org 07 Nov '12

07 Nov '12

the following patch was just integrated into master: commit 1ec778e734ae77e2a4dae674cb1e1a2470e5b898 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 28 11:01:47 2012 +0200 Add log replayer If you create the log from serialice with log_everything=true, you can modify the filters and pipe the logfile through the replayer without having to run Qemu again. This mostly works with old logfiles created with the single-file script too. $ cat qemu_logfile.txt | lua replay.lua Change-Id: I80f94f6cdb13b1f52188f4b9560ec040fb831fe8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/1644 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Sun Oct 28 21:57:08 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Nov 6 22:03:47 2012, giving +2 See http://review.coreboot.org/1644 for details. -gerrit

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Patch merged into serialice/master: f9b8d14 Add CPUID and CPU MSR filters
by gerrit＠coreboot.org 07 Nov '12

07 Nov '12

the following patch was just integrated into master: commit f9b8d14473975767502db8abea191aae736f1f65 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 28 14:00:19 2012 +0200 Add CPUID and CPU MSR filters MSR filter prevents microcode update on the target. CPUID filter fakes CPU is single-core. Change-Id: I26479bae215dafe0b1bc114951e04c927423759e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/1643 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Sun Oct 28 21:45:56 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Nov 6 22:03:16 2012, giving +2 See http://review.coreboot.org/1643 for details. -gerrit

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Patch merged into serialice/master: adac109 Add simba, modular filtering
by gerrit＠coreboot.org 07 Nov '12

07 Nov '12

the following patch was just integrated into master: commit adac109864b82309ee041fe53b76a6dcb86dea00 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 28 10:41:54 2012 +0200 Add simba, modular filtering This implement the core interface of IO and memory operations between Qemu and SerialICE LUA filter scripts. Change-Id: I116fa45597c321155c7e24bb20e497c3e93640b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/1642 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Sun Oct 28 21:34:22 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Nov 6 22:02:54 2012, giving +2 See http://review.coreboot.org/1642 for details. -gerrit

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Patch merged into serialice/master: 2bb6d50 LUA interface change for Qemu
by gerrit＠coreboot.org 07 Nov '12

07 Nov '12

the following patch was just integrated into master: commit 2bb6d500812a15cac9463ac20a41dac9f770265a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon May 7 20:31:52 2012 +0300 LUA interface change for Qemu This changes interface between Qemu and LUA to support modular scripting system. Single-file serialice.lua script is deleted, New modular scripts will require lua >= 5.2 with integrated bitlib. Change-Id: I7c4678ab6313857d81233aadfb6a44b7e7ca4ed0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/1641 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Sun Oct 28 21:23:06 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Nov 6 22:00:00 2012, giving +2 See http://review.coreboot.org/1641 for details. -gerrit

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New patch to review for serialice: 7e24501 Add config option for LPC/PCI POST card
by Rudolf Marek 04 Nov '12

04 Nov '12

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1682 -gerrit commit 7e24501758cbcfbc514b7d8fb627add73604dbda Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Nov 4 15:47:33 2012 +0100 Add config option for LPC/PCI POST card It turns out that first works POST card than serial port. Make it a nice Kconfig option and convert #if 0 existing code to use it. While at it add support for SBxxx. Change-Id: I38af84211d686484deabcec0002d7d261993e4d6 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- SerialICE/Kconfig | 15 +++++++++++++ SerialICE/mainboard/intel_d945gclf.c | 3 ++- SerialICE/mainboard/roda_rk886ex.c | 4 +++- SerialICE/southbridge/amd-sbxxx.c | 43 +++++++++++++++++++++++++++++++++++- SerialICE/southbridge/intel-ich7.c | 4 +++- 5 files changed, 65 insertions(+), 4 deletions(-) diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig index 5a4c073..f1f3d8e 100644 --- a/SerialICE/Kconfig +++ b/SerialICE/Kconfig @@ -319,6 +319,21 @@ config EXPERIMENTAL We do not make any guarantees about anything that is marked as EXPERIMENTAL! You have been warned! +choice + prompt "POST card" + default POST_NONE + +config POST_NONE + boolean "None" + +config POST_PCI + boolean "PCI POST card" + +config POST_LPC + boolean "LPC POST card" + +endchoice + config EXPERT bool "Expert mode" help diff --git a/SerialICE/mainboard/intel_d945gclf.c b/SerialICE/mainboard/intel_d945gclf.c index c78f3bc..85d4d82 100644 --- a/SerialICE/mainboard/intel_d945gclf.c +++ b/SerialICE/mainboard/intel_d945gclf.c @@ -18,6 +18,7 @@ */ /* This is a chipset init file for the Intel D945GCLF mainboard */ +#include "config.h" const char boardname[33]="Intel D945GCLF "; @@ -35,7 +36,7 @@ static void southbridge_init(void) // Set up RCBA pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1); -#if 0 +#if defined(CONFIG_POST_LPC) // port80 writes go to LPC: reg32 = RCBA32(GCS); reg32 = reg32 & ~0x04; diff --git a/SerialICE/mainboard/roda_rk886ex.c b/SerialICE/mainboard/roda_rk886ex.c index e3e02c1..b54fd79 100644 --- a/SerialICE/mainboard/roda_rk886ex.c +++ b/SerialICE/mainboard/roda_rk886ex.c @@ -20,6 +20,8 @@ /* * This is an example chipset init file for the Roda RK886EX (Rocky 3+) */ +#include "config.h" + const char boardname[33]="Roda RK886EX (Rocky III+) "; /* Hardware specific functions */ @@ -36,7 +38,7 @@ static void southbridge_init(void) // Set up RCBA pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1); -#if 0 +#if defined(CONFIG_POST_LPC) // port80 writes go to LPC: reg32 = RCBA32(GCS); reg32 = reg32 & ~0x04; diff --git a/SerialICE/southbridge/amd-sbxxx.c b/SerialICE/southbridge/amd-sbxxx.c index 86f1278..37dca92 100644 --- a/SerialICE/southbridge/amd-sbxxx.c +++ b/SerialICE/southbridge/amd-sbxxx.c @@ -23,6 +23,8 @@ * o enables POST card (see #if 0) */ +#include "config.h" + #define MMIO_NON_POSTED_START 0xfed00000 #define MMIO_NON_POSTED_END 0xfedfffff #define SB_MMIO 0xFED80000 @@ -44,7 +46,7 @@ static void sbxxx_enable_48mhzout(void) static void southbridge_init(void) { - u16 reg16; + u8 reg8; u32 reg32; /* route FED00000 - FEDFFFFF as non-posted to SB */ @@ -65,4 +67,43 @@ static void southbridge_init(void) /* Enable LPC decoding of 0x2e/0x2f, 0x4e/0x4f 0x3f8 */ pci_write_config8(PCI_ADDR(0, 0x14, 3, 0x44), (1<<6)); pci_write_config8(PCI_ADDR(0, 0x14, 3, 0x48), (1 << 1) | (1 << 0)); + +#if defined(CONFIG_POST_PCI) + /* Chip Control: Enable subtractive decoding */ + reg8 = pci_read_config8(PCI_ADDR(0, 0x14, 4, 0x40)); + reg8 |= 1 << 5; + pci_write_config8(PCI_ADDR(0, 0x14, 4, 0x40), reg8); + + /* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */ + reg8 = pci_read_config8(PCI_ADDR(0, 0x14, 4, 0x4b)); + reg8 |= 1 << 7; + pci_write_config8(PCI_ADDR(0, 0x14, 4, 0x4b), reg8); + + /* The same IO Base and IO Limit here is meaningful because we set the + * bridge to be subtractive. During early setup stage, we have to make + * sure that data can go through port 0x80. + */ + /* IO Base: 0xf000 */ + reg8 = pci_read_config8(PCI_ADDR(0, 0x14, 4, 0x1c)); + reg8 |= 0xf << 4; + pci_write_config8(PCI_ADDR(0, 0x14, 4, 0x1c), reg8); + + /* IO Limit: 0xf000 */ + reg8 = pci_read_config8(PCI_ADDR(0, 0x14, 4, 0x1d)); + reg8 |= 0xf << 4; + pci_write_config8(PCI_ADDR(0, 0x14, 4, 0x1d), reg8); + + /* PCI Command: Enable IO response */ + reg8 = pci_read_config8(PCI_ADDR(0, 0x14, 4, 0x4)); + reg8 |= 1 << 0; + pci_write_config8(PCI_ADDR(0, 0x14, 4, 0x4) , reg8); + + reg8 = pci_read_config8(PCI_ADDR(0, 0x14, 3, 0x4a)); + reg8 &= ~(1 << 5); /* disable lpc port 80 */ + pci_write_config8(PCI_ADDR(0, 0x14, 3, 0x4a), reg8); +#elif defined(CONFIG_POST_LPC) + reg8 = pci_read_config8(PCI_ADDR(0, 0x14, 3, 0x4a)); + reg8 |= (1 << 5); /* enable lpc port 80 */ + pci_write_config8(PCI_ADDR(0, 0x14, 3, 0x4a), reg8); +#endif } diff --git a/SerialICE/southbridge/intel-ich7.c b/SerialICE/southbridge/intel-ich7.c index 3688084..c58aca1 100644 --- a/SerialICE/southbridge/intel-ich7.c +++ b/SerialICE/southbridge/intel-ich7.c @@ -23,6 +23,8 @@ * o the watchdog is turned off */ +#include "config.h" + #define RCBA 0xfed1c000 #define GCS 0x3410 #define RCBA32(x) *((volatile u32 *)(RCBA + x)) @@ -35,7 +37,7 @@ static void southbridge_init(void) // Set up RCBA pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1); -#if 0 +#if defined(CONFIG_POST_LPC) // port80 writes go to LPC: reg32 = RCBA32(GCS); reg32 = reg32 & ~0x04;

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Patch set updated for serialice: a2dea87 Add the Asus F2A85-M
by Rudolf Marek 04 Nov '12

04 Nov '12

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1680 -gerrit commit a2dea87820ce5a52425bb3f088bd8590ced362f6 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Nov 4 12:26:03 2012 +0100 Add the Asus F2A85-M Add the Asus F2A85-M, while at it, add also SBxxx specific snippets which may be used by future boards. It contains handy stuff to enable the LPC decodes and also it enables clock output if SB clockchip is used. Change-Id: Ieb782bdb35831568d61fd57c7c956bf4cc9747c7 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- SerialICE/Kconfig | 6 ++++ SerialICE/mainboard/asus_f2a85-m.c | 50 ++++++++++++++++++++++++++++ SerialICE/southbridge/amd-sbxxx.c | 68 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 124 insertions(+) diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig index 7199453..5a4c073 100644 --- a/SerialICE/Kconfig +++ b/SerialICE/Kconfig @@ -45,6 +45,10 @@ config BOARD_INTEL_D945GCLF config BOARD_DELL_S1850 bool "Dell PowerEdge S1850" +config BOARD_ASUS_F2A85_M + bool "ASUS F2A85-M" + select BUILD_XMMSTACK + config BOARD_ASUS_M2V_MX_SE bool "ASUS M2V-MX SE" select VIA_ROMSTRAP @@ -121,6 +125,7 @@ config BOARD_INIT default "roda_rk886ex.c" if BOARD_RODA_RK886EX default "intel_d945gclf.c" if BOARD_INTEL_D945GCLF default "dell_s1850.c" if BOARD_DELL_S1850 + default "asus_f2a85-m.c" if BOARD_ASUS_F2A85_M default "asus_m2v-mx_se.c" if BOARD_ASUS_M2V_MX_SE default "asus_k8v-x.c" if BOARD_ASUS_K8V_X default "msi_ms6178.c" if BOARD_MSI_MS6178 @@ -144,6 +149,7 @@ config BOARD_INIT config SOUTHBRIDGE_INIT string default "southbridge/intel-ich7.c" if BOARD_KONTRON_986LCD_M + default "southbridge/amd-sbxxx.c" if BOARD_ASUS_F2A85_M config SUPERIO_INIT string diff --git a/SerialICE/mainboard/asus_f2a85-m.c b/SerialICE/mainboard/asus_f2a85-m.c new file mode 100644 index 0000000..532421d --- /dev/null +++ b/SerialICE/mainboard/asus_f2a85-m.c @@ -0,0 +1,50 @@ +/* + * SerialICE + * + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +const char boardname[33]="Asus F2A85-M "; + +#define SUPERIO_CONFIG_PORT 0x2e + +static void superio_init(void) +{ + u8 byte; + pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + + /* Disable the watchdog. */ + pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7); + pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00); + + /* Enable the serial port. */ + pnp_set_logical_device(SUPERIO_CONFIG_PORT, 1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + + pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT); +} + + +static void chipset_init(void) +{ + southbridge_init(); + sbxxx_enable_48mhzout(); + superio_init(); +} diff --git a/SerialICE/southbridge/amd-sbxxx.c b/SerialICE/southbridge/amd-sbxxx.c new file mode 100644 index 0000000..86f1278 --- /dev/null +++ b/SerialICE/southbridge/amd-sbxxx.c @@ -0,0 +1,68 @@ +/* + * SerialICE + * + * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This initializes AMD SBxx that + * o Ports 0x2e/0x2f 0x4e/0x4f and 0x3f8 are routed to superio + * o the MMIO regs of SB are accesible + * o enables POST card (see #if 0) + */ + +#define MMIO_NON_POSTED_START 0xfed00000 +#define MMIO_NON_POSTED_END 0xfedfffff +#define SB_MMIO 0xFED80000 +#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x)) + +static void sbxxx_enable_48mhzout(void) +{ + /* most likely programming to 48MHz out signal */ + u32 reg32; + reg32 = SB_MMIO_MISC32(0x28); + reg32 &= 0xffc7ffff; + reg32 |= 0x00100000; + SB_MMIO_MISC32(0x28) = reg32; + + reg32 = SB_MMIO_MISC32(0x40); + reg32 &= ~0x80u; + SB_MMIO_MISC32(0x40) = reg32; +} + +static void southbridge_init(void) +{ + u16 reg16; + u32 reg32; + + /* route FED00000 - FEDFFFFF as non-posted to SB */ + pci_write_config32(PCI_ADDR(0, 0x18, 1, 0x84), + (((MMIO_NON_POSTED_END & ~0xffffu) >> 8) | (1 << 7))); + /* lowest NP address is HPET at FED00000 */ + pci_write_config32(PCI_ADDR(0, 0x18, 1, 0x80), + (MMIO_NON_POSTED_START >> 8) | 3); + + /* Send all IO (0000-FFFF) to southbridge. */ + pci_write_config32(PCI_ADDR(0, 0x18, 1, 0xc4), 0x0000f000); + pci_write_config32(PCI_ADDR(0, 0x18, 1, 0xc0), 0x00000003); + + /* SB MMIO range decode enable */ + outb(0x24, 0xcd6); + outb(0x1, 0xcd7); + + /* Enable LPC decoding of 0x2e/0x2f, 0x4e/0x4f 0x3f8 */ + pci_write_config8(PCI_ADDR(0, 0x14, 3, 0x44), (1<<6)); + pci_write_config8(PCI_ADDR(0, 0x14, 3, 0x48), (1 << 1) | (1 << 0)); +}

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SerialICE November 2012