November 2012 - SerialICE - mail.coreboot.org

Patch set updated for serialice: 2c510be Make the CPU microcode filter generic(not CPU model specific).
by Denis Carikli Nov. 30, 2012

Nov. 30, 2012

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1948 -gerrit commit 2c510be67a536375a06776d96bc0337e9edb767d Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri Nov 30 12:35:51 2012 +0100 Make the CPU microcode filter generic(not CPU model specific). The microcode updating filter can be used this way: For AMD: -------- In your mainboard file add something like that: microcode_patchlevel_eax = 0x010000b7 function do_mainboard_setup() [...] enable_hook(cpumsr_hooks, filter_amd_microcode) end 0x010000b7 is what corresponds to the microcode patch level. For Intel: ---------- In your mainboard file add something like that: microcode_patchlevel_edx = 0xc7 function do_mainboard_setup() [...] enable_hook(cpumsr_hooks, filter_intel_microcode) end Change-Id: I370b80a341820ab070f97cc578eb43d5aca192ad Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- SerialICE/simba/cpu.lua | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/SerialICE/simba/cpu.lua b/SerialICE/simba/cpu.lua index c440b4b..9c2c72b 100644 --- a/SerialICE/simba/cpu.lua +++ b/SerialICE/simba/cpu.lua @@ -57,6 +57,9 @@ filter_cpumsr_fallback = { -- ********************************************************** -- CPUID filters +microcode_patchlevel_eax = 0 +microcode_patchlevel_edx = 0 + function cpuid_pre(f, action) return handle_action(f, action) end @@ -116,8 +119,8 @@ end -- Fakes microcode revision of my 0x6f6 Core 2 Duo Mobile function intel_microcode_post(f, action) if action.rin.ecx == 0x8b then - action.rout.edx = 0xc7 - action.rout.eax = 0 + action.rout.edx = microcode_patchlevel_edx + action.rout.eax = microcode_patchlevel_eax return fake_action(f, action, 0) end return skip_filter(f, action) @@ -145,7 +148,8 @@ end -- Fakes microcode revision. function amd_microcode_post(f, action) if action.rin.ecx == 0x8b then - action.rout.eax = 0x010000b7 + action.rout.eax = microcode_patchlevel_eax + action.rout.edx = microcode_patchlevel_edx return fake_action(f, action, 0) end return skip_filter(f, action)

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Patch set updated for serialice: b1eaa83 Add AMD microcode updating filter.
by Denis Carikli Nov. 30, 2012

Nov. 30, 2012

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1945 -gerrit commit b1eaa8310990174ab7b1efb287e8419ffacb56ad Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu Nov 29 22:25:35 2012 +0100 Add AMD microcode updating filter. 0x010000b7 is what corresponds to the microcode patch level of my CPU. Change-Id: If6d72bfdbd9b9f78cd5774db82c401b638f35046 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- SerialICE/simba/cpu.lua | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/SerialICE/simba/cpu.lua b/SerialICE/simba/cpu.lua index be04825..c440b4b 100644 --- a/SerialICE/simba/cpu.lua +++ b/SerialICE/simba/cpu.lua @@ -129,3 +129,31 @@ filter_intel_microcode = { pre = intel_microcode_pre, post = intel_microcode_post, } + +-- AMD CPU microcode update +function amd_microcode_pre(f, action) + if action.rin.ecx == 0xc0010020 then + --action.dropped = true + --action.rout.edx = 0 + --action.rout.eax = 0xffff0000 + return drop_action(f, action) + end + return skip_filter(f, action) +end + +-- AMD CPU microcode revision check +-- Fakes microcode revision. +function amd_microcode_post(f, action) + if action.rin.ecx == 0x8b then + action.rout.eax = 0x010000b7 + return fake_action(f, action, 0) + end + return skip_filter(f, action) +end + +filter_amd_microcode = { + id = -1, + name = "Microcode Update", + pre = amd_microcode_pre, + post = amd_microcode_post, +}

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New patch to review for serialice: 0de2769 Make the CPU microcode filter generic(not CPU model specific).
by Denis Carikli Nov. 30, 2012

Nov. 30, 2012

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1948 -gerrit commit 0de27696025d59463d660eb78fc68956a1190525 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri Nov 30 12:35:51 2012 +0100 Make the CPU microcode filter generic(not CPU model specific). The microcode updating filter can be used this way: For AMD: -------- In your mainboard file add something like that: microcode_patchlevel_eax = 0x010000b7 function do_mainboard_setup() [...] enable_hook(cpumsr_hooks, filter_amd_microcode) end 0x010000b7 is what corresponds to the microcode patch level. For Intel: ---------- In your mainboard file add something like that: microcode_patchlevel_edx = 0xc7 function do_mainboard_setup() [...] enable_hook(cpumsr_hooks, filter_intel_microcode) end Change-Id: I370b80a341820ab070f97cc578eb43d5aca192ad Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- SerialICE/simba/cpu.lua | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/SerialICE/simba/cpu.lua b/SerialICE/simba/cpu.lua index 40f21a6..bd80d0e 100644 --- a/SerialICE/simba/cpu.lua +++ b/SerialICE/simba/cpu.lua @@ -57,6 +57,9 @@ filter_cpumsr_fallback = { -- ********************************************************** -- CPUID filters +microcode_patchlevel_eax = 0 +microcode_patchlevel_edx = 0 + function cpuid_pre(f, action) return handle_action(f, action) end @@ -116,7 +119,7 @@ end -- Fakes microcode revision of my 0x6f6 Core 2 Duo Mobile function intel_microcode_post(f, action) if action.rin.ecx == 0x8b then - action.rout.edx = 0xc7 + action.rout.edx = microcode_patchlevel_edx action.rout.eax = 0 return fake_action(f, action, 0) end @@ -145,7 +148,7 @@ end -- Fakes microcode revision. function amd_microcode_post(f, action) if action.rin.ecx == 0x8b then - action.rout.eax = 0x010000b7 + action.rout.eax = microcode_patchlevel_eax return fake_action(f, action, 0) end return skip_filter(f, action)

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Patch set updated for serialice: 340eb10 Add AMD microcode updating filter.
by Denis Carikli Nov. 30, 2012

Nov. 30, 2012

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1945 -gerrit commit 340eb10c1e6dd8664d71dc465a2f0df431007734 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu Nov 29 22:25:35 2012 +0100 Add AMD microcode updating filter. 0x010000b7 is what corresponds to the microcode patch level of my CPU. Change-Id: If6d72bfdbd9b9f78cd5774db82c401b638f35046 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- SerialICE/simba/cpu.lua | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/SerialICE/simba/cpu.lua b/SerialICE/simba/cpu.lua index be04825..40f21a6 100644 --- a/SerialICE/simba/cpu.lua +++ b/SerialICE/simba/cpu.lua @@ -129,3 +129,31 @@ filter_intel_microcode = { pre = intel_microcode_pre, post = intel_microcode_post, } + +-- AMD CPU microcode update +function amd_microcode_pre(f, action) + if action.rin.ecx == 0xc0010020 then + --action.dropped = true + --action.rout.edx = 0 + --action.rout.eax = 0xffff0000 + return drop_action(f, action) + end + return skip_filter(f, action) +end + +-- AMD CPU microcode revision check +-- Fakes microcode revision. +function amd_microcode_post(f, action) + if action.rin.ecx == 0x8b then + action.rout.eax = 0x010000b7 + return fake_action(f, action, 0) + end + return skip_filter(f, action) +end + +filter_amd_microcode = { + id = -1, + name = "Microcode Update", + pre = amd_microcode_pre, + post = amd_microcode_post, +}

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New patch to review for serialice: bb8620b Add AMD microcode updating filter.
by Denis Carikli Nov. 29, 2012

Nov. 29, 2012

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1945 -gerrit commit bb8620bf4279503a53cde60aefccfa4974e5c422 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu Nov 29 22:25:35 2012 +0100 Add AMD microcode updating filter. The microcode updating filter can be used this way: In your mainboard file add something like that: fake_microcode_value = 0x010000b7 function do_mainboard_setup() [...] enable_hook(cpumsr_hooks, filter_amd_microcode) end 0x010000b7 is what corresponds to the microcode patch level. Change-Id: If6d72bfdbd9b9f78cd5774db82c401b638f35046 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- SerialICE/simba/cpu.lua | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/SerialICE/simba/cpu.lua b/SerialICE/simba/cpu.lua index be04825..43a1e42 100644 --- a/SerialICE/simba/cpu.lua +++ b/SerialICE/simba/cpu.lua @@ -129,3 +129,31 @@ filter_intel_microcode = { pre = intel_microcode_pre, post = intel_microcode_post, } + +-- AMD CPU microcode update +function amd_microcode_pre(f, action) + if action.rin.ecx == 0xc0010020 then + --action.dropped = true + --action.rout.edx = 0 + --action.rout.eax = 0xffff0000 + return drop_action(f, action) + end + return skip_filter(f, action) +end + +-- AMD CPU microcode revision check +-- Fakes microcode revision. +function amd_microcode_post(f, action) + if action.rin.ecx == 0x8b then + action.rout.eax = fake_microcode_value + return fake_action(f, action, 0) + end + return skip_filter(f, action) +end + +filter_amd_microcode = { + id = -1, + name = "Microcode Update", + pre = amd_microcode_pre, + post = amd_microcode_post, +}

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Patch set updated for serialice: 7b39191 Add support for extended PCI config space via 0xcf8
by Rudolf Marek Nov. 25, 2012

Nov. 25, 2012

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1912 -gerrit commit 7b391912b225d3d0d657164623a4e14d050533fa Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Nov 25 19:55:01 2012 +0100 Add support for extended PCI config space via 0xcf8 Some chipsets allows on request an access to extended PCI config space 0 - 4096. Lets add them to the decoder. There is no generic limitation for number of busses, but this mechanism is used as the backdoor to chipset extended PCI regs. Change-Id: Ie446104c86916f719bc0230d5e9ce2f8a49cceb1 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- SerialICE/simba/pci_cfg.lua | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/SerialICE/simba/pci_cfg.lua b/SerialICE/simba/pci_cfg.lua index 88ea266..47a061d 100644 --- a/SerialICE/simba/pci_cfg.lua +++ b/SerialICE/simba/pci_cfg.lua @@ -151,7 +151,7 @@ function pci_cfg_print(f, action, bdfr) dir_str = "<=" end - printk(f, action, "%x:%02x.%x [%02x] %s %s\n", + printk(f, action, "%x:%02x.%x [%03x] %s %s\n", bit32.band(0xff,bit32.rshift(bdfr, 20)), bit32.band(0x1f,bit32.rshift(bdfr, 15)), bit32.band(0x7,bit32.rshift(bdfr, 12)), bit32.band(0xfff,bdfr), dir_str, size_data(action.size, action.data)) @@ -239,8 +239,14 @@ function pci_io_cfg_pre(f, action) new_parent_action() end local bdfr = 0 + -- BDFR is like normal BDF but reg has 12 bits to cover all extended space + -- Copy bus/device/function bdfr = bit32.lshift(action.data, 4) - bdfr = bit32.band(bdfr, 0xfffff000) + bdfr = bit32.band(bdfr, 0x0ffff000) + -- Some chipsets allows (on request) performing extended register space access + -- Usually using bits 27:24, copy that to right place + bdfr = bit32.bor(bdfr, bit32.band(0xf00, bit32.rshift(action.data, 24 - 8))) + -- Add the classic PCI register bdfr = bit32.bor(bdfr, bit32.band(action.data, 0xfc)) pci_cfg_select(f, bdfr) end

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New patch to review for serialice: e989a9c Parse error on mainboard script is fatal
by Kyösti Mälkki Nov. 25, 2012

Nov. 25, 2012

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1913 -gerrit commit e989a9c7aff122404dedcddc0ce5be57d12e6453 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Nov 25 21:15:31 2012 +0200 Parse error on mainboard script is fatal If there is a parse error in mainboard script, abort execution. Previous behaviour incorrectly indicated a "file not found" error and continued execution with default/minimal profile. Change-Id: If69b1394b2ab8b77d7514b600dddb0c19963b440 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- SerialICE/simba/serialice.lua | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/SerialICE/simba/serialice.lua b/SerialICE/simba/serialice.lua index 9eb287d..406c900 100644 --- a/SerialICE/simba/serialice.lua +++ b/SerialICE/simba/serialice.lua @@ -92,8 +92,11 @@ function do_default_setup() end mainboard_file = string.format("%s.lua", string.lower(string.gsub(SerialICE_mainboard, "[ -]", "_"))) -local mainboard_lua = loadfile(mainboard_file) -if (mainboard_lua) then +local mainboard_lua, ferr = loadfile(mainboard_file) +local mainboard_script = io.open(mainboard_file) +if mainboard_script then + io.close(mainboard_script) + assert(mainboard_lua, ferr) mainboard_lua() printks(froot, "Mainboard script %s initialized.\n", mainboard_file) do_minimal_setup()

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New patch to review for serialice: 8f214c9 Add support for extended PCI config space via 0xcf8
by Rudolf Marek Nov. 25, 2012

Nov. 25, 2012

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1912 -gerrit commit 8f214c98525a553f82caf3b775cec0e33a42674d Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Nov 25 19:55:01 2012 +0100 Add support for extended PCI config space via 0xcf8 Some chipsets allows on request an access to extended PCI config space 0 - 4096. Lets add them to the decoder. Change-Id: Ie446104c86916f719bc0230d5e9ce2f8a49cceb1 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- SerialICE/simba/pci_cfg.lua | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/SerialICE/simba/pci_cfg.lua b/SerialICE/simba/pci_cfg.lua index 88ea266..82a5171 100644 --- a/SerialICE/simba/pci_cfg.lua +++ b/SerialICE/simba/pci_cfg.lua @@ -151,7 +151,7 @@ function pci_cfg_print(f, action, bdfr) dir_str = "<=" end - printk(f, action, "%x:%02x.%x [%02x] %s %s\n", + printk(f, action, "%x:%02x.%x [%03x] %s %s\n", bit32.band(0xff,bit32.rshift(bdfr, 20)), bit32.band(0x1f,bit32.rshift(bdfr, 15)), bit32.band(0x7,bit32.rshift(bdfr, 12)), bit32.band(0xfff,bdfr), dir_str, size_data(action.size, action.data)) @@ -239,8 +239,14 @@ function pci_io_cfg_pre(f, action) new_parent_action() end local bdfr = 0 + -- BDFR is like normal BDF but reg has 12 bits to cover all extended space + -- Copy bus/device bdfr = bit32.lshift(action.data, 4) - bdfr = bit32.band(bdfr, 0xfffff000) + bdfr = bit32.band(bdfr, 0x0ffff000) + -- Some chipsets allows (on request) performing extended register space access + -- Usually using bits 27:24, copy that to right place + bdfr = bit32.bor(bdfr, bit32.band(0xf00, bit32.rshift(action.data, 24 - 8))) + -- Add the clasic PCI register bdfr = bit32.bor(bdfr, bit32.band(action.data, 0xfc)) pci_cfg_select(f, bdfr) end

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Getting started with new SerialICE scripts
by Kyösti Mälkki Nov. 23, 2012

Nov. 23, 2012

Hello all SerialICE folks ! You may have noticed the new filter system Simba has been merged for SerialICE. Written in LUA, as its predecessor, the new scripting system has greatly improved in terms of the log readability. I am sort of hoping someone of the few people recently playing around with the updated SerialICE would give a helping hand here and coordinate what to do with the existing documentation at serialice.org. Also don't destroy your existing logs, I could probably use some more nice sample runs. This is a very very brief introduction, I hope this answers some of the questions that have come up on #coreboot. Maybe SerialICE wiki is the way to go? 1. Target system setup People have contributed some new boards but essentially nothing has changed here. There is a menuconfig option to set the size of the Flash chip you are going to use, this information wasn't on the website "Getting Started" section. You should try with picocom/minicom that your target responses with a single SerialICE prompt. If you get many, there might be some watchdog that repeatedly triggers reset on the target. 2. Host system setup You need to build Qemu from the SerialICE git tree. Take note that LUA library version >= 5.2 must be installed. To run Qemu session on a 32bit host, you will need to build LUA from source with the patches under serialice/SerialICE/patches applied. The patch is to extend LUA's (signed) integer to 64bits, since we need to handle addresses close to 2^32. Fetch source... ~$ git clone http://review.coreboot.org/p/serialice and build: ~$ cd serialice/qemu-0.15.x ~serialice/qemu-0.15.x$ . ./build.sh To contribute to project, same guidelines apply to SerialICE as to coreboot. 3. Firing up SerialICE session The commandline to invoke a SerialICE session should look something like this: ~/serialice/qemu-0.15.x/i386-softmmu/qemu -machine serialice --serialice /dev/ttyUSB0 -L ./mb_vendor_bios/ You should then see the serialice output start rolling on your console. 4. The mainboard script In contrary to the single-file filter script "serialice.lua" the new filter implementation is split to several files under SerialICE/simba/. This new file layout does not even try to be an all-in-one filter supporting every existing mainboard --- you need to add a file that describes the chipset on your target mainboard. This 'mainboard script' file has a pre-defined name and you see it printed at the beginning of the console output when SerialICE session is started. A SerialICE session can run without a mainboard script file, but it can decode only those IO operations that have "default" or "semi-standard" locations in x86 architecture. To get started, you could copy some of the existing mainboard files as the basis for your setup. Further development besides selecting from the already implemented chipset parts takes more in-depth understanding of the filter setup. 5. Filter stack in brief An IO/MEM operation will first match a filter that claims the particular IO/MEM region. Active filters/regions are listed as RESOURCE lines in the log. Writes to PCI config space BAR registers will activate new RESOURCE entries. A filter claiming the IO/MEM operation decides if the operation executes on the real target hardware, the QEMU platform, or neither. A filter optionally appends and/or removes lines in the output log. What is said about IO/MEM operations here also applies to CPUID, RDMSR/WRMSR and PCI config space accesses. Any comments are welcome. I'll continue with writing a tutorial that should explain the filter anatomy and how it is supposed to work. Regards, Kyösti

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Patch merged into serialice/master: aa9a50b Drop lua 5.1.4 patches
by gerrit＠coreboot.org Nov. 20, 2012

Nov. 20, 2012

the following patch was just integrated into master: commit aa9a50b597ad5bb4824933b999a30fb5ed5e13a6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Nov 19 09:45:25 2012 +0200 Drop lua 5.1.4 patches Change-Id: I63c131fafa9d816f5f52ae3309e629920bf0f1ea Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/1881 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Mon Nov 19 15:24:17 2012, giving +2 See http://review.coreboot.org/1881 for details. -gerrit

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