December 2012 - SerialICE - mail.coreboot.org

Patch merged into serialice/master: 9eb497c Make the CPU microcode filter generic (not CPU model specific).

by gerrit＠coreboot.org

the following patch was just integrated into master: commit 9eb497c8718d6e5538570884def2b3e723e145c5 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri Nov 30 12:35:51 2012 +0100 Make the CPU microcode filter generic (not CPU model specific). The microcode updating filter can be used this way: For AMD: -------- In your mainboard file add something like that: microcode_patchlevel_eax = 0x010000b7 function do_mainboard_setup() [...] enable_hook(cpumsr_hooks, filter_amd_microcode) end 0x010000b7 is what corresponds to the microcode patch level. For Intel: ---------- In your mainboard file add something like that: microcode_patchlevel_edx = 0xc7 function do_mainboard_setup() [...] enable_hook(cpumsr_hooks, filter_intel_microcode) end Change-Id: I370b80a341820ab070f97cc578eb43d5aca192ad Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Reviewed-on: http://review.coreboot.org/1948 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Dec 1 12:39:10 2012, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Thu Dec 13 10:36:10 2012, giving +2 See http://review.coreboot.org/1948 for details. -gerrit

6 years, 10 months

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Patch merged into serialice/master: 2b4155e Add AMD microcode updating filter.

by gerrit＠coreboot.org

the following patch was just integrated into master: commit 2b4155ee2fea4a72bde6125ea66c607f3fd2f2a4 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu Nov 29 22:25:35 2012 +0100 Add AMD microcode updating filter. 0x010000b7 is what corresponds to the microcode patch level of my CPU. Change-Id: If6d72bfdbd9b9f78cd5774db82c401b638f35046 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Reviewed-on: http://review.coreboot.org/1945 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Nov 30 16:12:00 2012, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Thu Dec 13 10:21:51 2012, giving +2 See http://review.coreboot.org/1945 for details. -gerrit

6 years, 10 months

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Patch merged into serialice/master: c95bfbd Add support for extended PCI config space via 0xcf8

by gerrit＠coreboot.org

the following patch was just integrated into master: commit c95bfbd09fa2b2483fe8f48dc99848084207b9b3 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Nov 25 19:55:01 2012 +0100 Add support for extended PCI config space via 0xcf8 Some chipsets allows on request an access to extended PCI config space 0 - 4096. Lets add them to the decoder. There is no generic limitation for number of busses, but this mechanism is used as the backdoor to chipset extended PCI regs. Change-Id: Ie446104c86916f719bc0230d5e9ce2f8a49cceb1 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Reviewed-on: http://review.coreboot.org/1912 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov(a)gmail.com> Build-Tested: build bot (Jenkins) at Sun Nov 25 21:25:19 2012, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Tue Dec 4 14:03:47 2012, giving +2 See http://review.coreboot.org/1912 for details. -gerrit

6 years, 10 months

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Patch set updated for serialice: 7577517 Make the CPU microcode filter generic (not CPU model specific).

by Denis Carikli

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1948 -gerrit commit 757751745141a9d906cb3c669bdcde7e67745a41 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri Nov 30 12:35:51 2012 +0100 Make the CPU microcode filter generic (not CPU model specific). The microcode updating filter can be used this way: For AMD: -------- In your mainboard file add something like that: microcode_patchlevel_eax = 0x010000b7 function do_mainboard_setup() [...] enable_hook(cpumsr_hooks, filter_amd_microcode) end 0x010000b7 is what corresponds to the microcode patch level. For Intel: ---------- In your mainboard file add something like that: microcode_patchlevel_edx = 0xc7 function do_mainboard_setup() [...] enable_hook(cpumsr_hooks, filter_intel_microcode) end Change-Id: I370b80a341820ab070f97cc578eb43d5aca192ad Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- SerialICE/simba/cpu.lua | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/SerialICE/simba/cpu.lua b/SerialICE/simba/cpu.lua index c440b4b..9c2c72b 100644 --- a/SerialICE/simba/cpu.lua +++ b/SerialICE/simba/cpu.lua @@ -57,6 +57,9 @@ filter_cpumsr_fallback = { -- ********************************************************** -- CPUID filters +microcode_patchlevel_eax = 0 +microcode_patchlevel_edx = 0 + function cpuid_pre(f, action) return handle_action(f, action) end @@ -116,8 +119,8 @@ end -- Fakes microcode revision of my 0x6f6 Core 2 Duo Mobile function intel_microcode_post(f, action) if action.rin.ecx == 0x8b then - action.rout.edx = 0xc7 - action.rout.eax = 0 + action.rout.edx = microcode_patchlevel_edx + action.rout.eax = microcode_patchlevel_eax return fake_action(f, action, 0) end return skip_filter(f, action) @@ -145,7 +148,8 @@ end -- Fakes microcode revision. function amd_microcode_post(f, action) if action.rin.ecx == 0x8b then - action.rout.eax = 0x010000b7 + action.rout.eax = microcode_patchlevel_eax + action.rout.edx = microcode_patchlevel_edx return fake_action(f, action, 0) end return skip_filter(f, action)

6 years, 10 months

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SerialICE December 2012