SerialICE

Download

serialice@serialice.com

August 2014

1 participants
1 discussions

Patch set updated for serialice: c1b99dd Add new board NEC 945G-M4
by HAOUAS Elyes Aug. 7, 2014

Aug. 7, 2014

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6107 -gerrit commit c1b99dd349b768c06601c5edf930adea12d677c5 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Jun 26 18:20:39 2014 +0200 Add new board NEC 945G-M4 Please do not merge. The fan still not working Here is the log : https://www.dropbox.com/s/0qsjhrkrcxdkcky/2ndLog08072014-lua.txt Change-Id: Iaea13e51658d1729a31414938b7a70252b10723a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- SerialICE/Kconfig | 4 ++ SerialICE/mainboard/nec_945g-m4.c | 95 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 99 insertions(+) diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig index b384928..ee04980 100644 --- a/SerialICE/Kconfig +++ b/SerialICE/Kconfig @@ -107,6 +107,9 @@ config BOARD_MSI_MS6178 config BOARD_MSI_MS7133 bool "MSI MS-7133" +config BOARD_NEC_945G_M4 + bool "NEC 945g-m4" + config BOARD_RCA_RM4100 bool "RCA RM4100" @@ -172,6 +175,7 @@ config BOARD_INIT default "asrock_775i65g.c" if BOARD_ASROCK_775I65G default "commell_lv_672.c" if BOARD_COMMELL_LV_672 default "jetway_nf81_t56n_lf.c" if BOARD_JETWAY_NF81_T56N_LF + default "nec_945g-m4.c" if BOARD_NEC_945G_M4 config SOUTHBRIDGE_INIT string diff --git a/SerialICE/mainboard/nec_945g-m4.c b/SerialICE/mainboard/nec_945g-m4.c new file mode 100644 index 0000000..c8b06e5 --- /dev/null +++ b/SerialICE/mainboard/nec_945g-m4.c @@ -0,0 +1,95 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include "config.h" + +const char boardname[33]="945G M4 "; + +/* Hardware specific functions */ + +#define RCBA 0xfed1c000 +#define GCS 0x3410 +#define RCBA32(x) *((volatile u32 *)(RCBA + x)) + +static void southbridge_init(void) +{ + u16 reg16; + u32 reg32; + + // Set up RCBA + pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1); + +#if defined(CONFIG_POST_LPC) + // port80 writes go to LPC: + reg32 = RCBA32(GCS); + reg32 = reg32 & ~0x04; + RCBA32(GCS) = reg32; + outb(0x23, 0x80); +#endif + + // Enable Serial IRQ + pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x64), 0xd0); + // Set COM1 decode range + pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x80), 0x0010); + // Enable COM1 + pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x82), 0x340f); + // Enable SIO PM Events at 0x0a00 + pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x84), 0x00fc0a01); + + // Disable watchdog +#define PMBASE 0x500 +#define TCOBASE (PMBASE + 0x60) + pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x40), PMBASE | 1); + pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x44), 0x80); + reg16 = inw(TCOBASE + 0x08); + reg16 |= (1 << 11); + outw(reg16, TCOBASE + 0x08); + outw(0x0008, TCOBASE + 0x04); + outw(0x0002, TCOBASE + 0x06); +} + +static void superio_init(u8 cfg_port, u8 com_port, u8 pm) +{ + pnp_enter_ext_func_mode_alt(cfg_port); + + pnp_set_logical_device(cfg_port, com_port); + pnp_set_enable(cfg_port, 0); + pnp_set_iobase0(cfg_port, 0x3f8); + pnp_set_irq0(cfg_port, 4); + pnp_set_enable(cfg_port, 1); + + if (pm != 0) { + pnp_set_logical_device(cfg_port, pm); + pnp_set_enable(cfg_port, 0); + pnp_set_iobase0(cfg_port, 0x0a00); + pnp_set_irq0(cfg_port, 3); + pnp_set_enable(cfg_port, 1); + } + + pnp_exit_ext_func_mode(cfg_port); +} + +static void chipset_init(void) +{ + southbridge_init(); + superio_init(0x2e, 2, 11); + +} +

1 0