the following patch was just integrated into master:
commit b98badcf108f3241cdda306fbafb7e11b11e7be8
Author: Idwer Vollering <vidwer(a)gmail.com>
Date: Sun Nov 6 01:05:40 2011 +0100
Add SerialICE support for ASUS P4P800-VM.
Change-Id: I0ce304c7be28f24c5612603720ae470353a4a3cb
Signed-off-by: Idwer Vollering <vidwer(a)gmail.com>
Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Dec 23 10:16:11 2011, giving +2
See http://review.coreboot.org/418 for details.
-gerrit
Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/418
-gerrit
commit b98badcf108f3241cdda306fbafb7e11b11e7be8
Author: Idwer Vollering <vidwer(a)gmail.com>
Date: Sun Nov 6 01:05:40 2011 +0100
Add SerialICE support for ASUS P4P800-VM.
Change-Id: I0ce304c7be28f24c5612603720ae470353a4a3cb
Signed-off-by: Idwer Vollering <vidwer(a)gmail.com>
---
SerialICE/Kconfig | 4 ++
SerialICE/mainboard/asus_p4p800-vm.c | 57 ++++++++++++++++++++++++++++++++++
2 files changed, 61 insertions(+), 0 deletions(-)
diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig
index 48d43b7..ac53de1 100644
--- a/SerialICE/Kconfig
+++ b/SerialICE/Kconfig
@@ -99,6 +99,9 @@ config BOARD_WYSE_S50
config BOARD_ASROCK_P4I65GV
bool "ASRock P4i65GV"
+config BOARD_ASUS_P4P800_VM
+ bool "ASUS P4P800-VM"
+
endchoice
config BOARD_INIT
@@ -124,6 +127,7 @@ config BOARD_INIT
default "hp_dl165_g6.c" if BOARD_HP_DL165_G6
default "wyse_s50.c" if BOARD_WYSE_S50
default "asrock_p4i65gv.c" if BOARD_ASROCK_P4I65GV
+ default "asus_p4p800-vm.c" if BOARD_ASUS_P4P800_VM
config SOUTHBRIDGE_INIT
string
diff --git a/SerialICE/mainboard/asus_p4p800-vm.c b/SerialICE/mainboard/asus_p4p800-vm.c
new file mode 100644
index 0000000..4109bc0
--- /dev/null
+++ b/SerialICE/mainboard/asus_p4p800-vm.c
@@ -0,0 +1,57 @@
+/*
+ * SerialICE
+ *
+ * Copyright (C) 2011 Idwer Vollering <vidwer(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+const char boardname[33]="ASUS P4P800-VM ";
+
+#define SUPERIO_CONFIG_PORT 0x2e
+
+/* Hardware specific functions */
+static void mainboard_set_ich5(void)
+{
+ /* COM_DEC */ /* COMA at 0x3f8, COMB at 0x3f8 */
+ pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0xe0), 0x0);
+ /* LPC_EN */ /* FDD_LPC_EN=1, KBC_LPC_EN=1, CNF1_LPC_EN=1 */
+ pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0xe6), 0x1408);
+ /* FB_DEC_EN1 */ /* FN_F8_EN=1, decode two 512 kilobyte flash ranges */
+ pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0xe3), 0x80);
+ /* FB_DEC_EN2 */ /* don't decode two 1 megabyte ranges */
+ pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0xf0), 0x0);
+ /* FUNC_DIS */ /* D31_F6_DISABLE=1 (AC97 modem) */
+ pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0xf2), 0x0040);
+}
+
+/* Winbond W83627THF */
+static void superio_init(void)
+{
+ pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT);
+ /* Set the clock to 48MHz */
+ pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0x42);
+ pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2);
+ pnp_set_enable(SUPERIO_CONFIG_PORT, 0);
+ pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8);
+ pnp_set_irq0(SUPERIO_CONFIG_PORT, 4);
+ pnp_set_enable(SUPERIO_CONFIG_PORT, 1);
+ pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT);
+}
+
+static void chipset_init(void)
+{
+ mainboard_set_ich5();
+ superio_init();
+}
Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/466
-gerrit
commit cfdb9f2a627c83e644719c85ebf58300bde1dfab
Author: Patrick Georgi <patrick.georgi(a)secunet.com>
Date: Thu Dec 1 15:09:08 2011 +0100
Make ROM size more easily configurable
Change-Id: I683ebcb59c17b2460c797d6e94f3c15384d26407
Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com>
---
SerialICE/scripts/serialice.lua | 9 ++++++---
1 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/SerialICE/scripts/serialice.lua b/SerialICE/scripts/serialice.lua
index 7346046..3a8bf74 100644
--- a/SerialICE/scripts/serialice.lua
+++ b/SerialICE/scripts/serialice.lua
@@ -209,6 +209,9 @@ ip_logging = false
SerialICE_pci_device = 0
+rom_size = 4 * 1024 * 1024
+rom_base = 0x100000000 - rom_size
+
-- SerialICE_io_read_filter is the filter function for IO reads.
--
-- Parameters:
@@ -456,7 +459,7 @@ function SerialICE_memory_read_filter(addr, size)
return false, true, 0
end
- if addr >= 0xfff00000 and addr <= 0xffffffff then
+ if addr >= rom_base and addr <= 0xffffffff then
-- ROM accesses go to Qemu only
return false, true, 0
elseif addr >= PCIe_bar and addr <= (PCIe_bar + PCIe_size) then
@@ -532,7 +535,7 @@ function SerialICE_memory_write_filter(addr, size, data)
return false, true, data
end
- if addr >= 0xfff00000 and addr <= 0xffffffff then
+ if addr >= rom_base and addr <= 0xffffffff then
printf("\nWARNING: write access to ROM?\n")
-- ROM accesses go to Qemu only
return false, true, data
@@ -671,7 +674,7 @@ function SerialICE_memory_read_log(addr, size, data, target)
if addr >= 0xe0000 and addr <= 0xfffff and not log_rom_access then
return
end
- if addr >= 0xfff00000 and addr <= 0xffffffff and not log_rom_access then
+ if addr >= rom_base and addr <= 0xffffffff and not log_rom_access then
return
end
Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/464
-gerrit
commit cd58c70459fff16fe46fe501e54728aa7ac50b78
Author: Patrick Georgi <patrick.georgi(a)secunet.com>
Date: Thu Dec 1 14:00:41 2011 +0100
Refactor CAR region code
Change-Id: If7c4cff1690c4d48cca50d03d75ec533b26c8d9f
Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com>
---
SerialICE/scripts/serialice.lua | 56 ++++++++++++++++++++++++++------------
1 files changed, 38 insertions(+), 18 deletions(-)
diff --git a/SerialICE/scripts/serialice.lua b/SerialICE/scripts/serialice.lua
index a41988a..2472b49 100644
--- a/SerialICE/scripts/serialice.lua
+++ b/SerialICE/scripts/serialice.lua
@@ -54,6 +54,27 @@ function pci_bdf(bus, dev, func, reg)
return 0x80000000 + bus*65536 + dev*2048 + func*256 + reg
end
+car_regions = { list = nil }
+
+function new_car_region(start, size)
+ car_regions.list = { next = car_regions.list, start = start, size = size }
+ SerialICE_register_physical(start, size)
+end
+
+function is_car(addr)
+ if car_regions.list == nil then
+ return false
+ end
+ local l = car_regions.list
+ while l do
+ if addr >= l.start and addr < l.start + l.size then
+ return true
+ end
+ l = l.next
+ end
+ return false
+end
+
function new_list()
return { list = nil }
end
@@ -389,6 +410,12 @@ function SerialICE_memory_read_filter(addr, size)
-- return false, false, 0x23232323
-- end
+ -- Cache-As-RAM is exclusively
+ -- handled by Qemu (RAM backed)
+ if is_car(addr) then
+ return false, true, 0
+ end
+
if addr >= 0xfff00000 and addr <= 0xffffffff then
-- ROM accesses go to Qemu only
return false, true, 0
@@ -401,14 +428,6 @@ function SerialICE_memory_read_filter(addr, size)
-- Intel chipset BARs are exclusively
-- handled by the SerialICE target
return true, false, 0
- elseif addr >= 0xffd80000 and addr <= 0xffdfffff then
- -- coreboot Cache-As-RAM is exclusively
- -- handled by Qemu (RAM backed)
- return false, true, 0
- elseif addr >= 0xffbc0000 and addr <= 0xffbfffff then
- -- AMI Cache-As-RAM is exclusively
- -- handled by Qemu (RAM backed)
- return false, true, 0
elseif addr >= 0xfee00000 and addr <= 0xfeefffff then
-- Local APIC.. Hm, not sure what to do here.
-- We should avoid that someone wakes up cores
@@ -467,6 +486,12 @@ end
-- result Data to be written (may be changed in filter)
function SerialICE_memory_write_filter(addr, size, data)
+ -- Cache-As-RAM is exclusively
+ -- handled by Qemu (RAM backed)
+ if is_car(addr) then
+ return false, true, data
+ end
+
if addr >= 0xfff00000 and addr <= 0xffffffff then
printf("\nWARNING: write access to ROM?\n")
-- ROM accesses go to Qemu only
@@ -480,14 +505,6 @@ function SerialICE_memory_write_filter(addr, size, data)
-- Intel chipset BARs are exclusively
-- handled by the SerialICE target
return true, false, data
- elseif addr >= 0xffd80000 and addr <= 0xffdfffff then
- -- coreboot Cache-As-RAM is exclusively
- -- handled by Qemu (RAM backed)
- return false, true, data
- elseif addr >= 0xffbc0000 and addr <= 0xffbfffff then
- -- AMI Cache-As-RAM is exclusively
- -- handled by Qemu (RAM backed)
- return false, true, data
elseif addr >= 0xfee00000 and addr <= 0xfeefffff then
-- Local APIC.. Hm, not sure what to do here.
-- We should avoid that someone wakes up cores
@@ -707,11 +724,14 @@ printf("SerialICE: Registering physical memory areas for Cache-As-Ram:\n")
-- Register Phoenix BIOS Cache as RAM area as normal RAM
-- 0xffd80000 - 0xffdfffff
-SerialICE_register_physical(0xffd80000, 0x80000)
+new_car_region(0xffd80000, 0x80000)
-- Register AMI BIOS Cache as RAM area as normal RAM
-- 0xffbc0000 - 0xffbfffff
-SerialICE_register_physical(0xffbc0000, 0x40000)
+new_car_region(0xffbc0000, 0x40000)
+
+-- current Phoenix BIOS
+new_car_region(0xde000, 0x2000)
printf("SerialICE: LUA script initialized.\n")
Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/463
-gerrit
commit 5ff3917a00d0157b4cb6a4d99bce5c99f08e34cc
Author: Patrick Georgi <patrick.georgi(a)secunet.com>
Date: Thu Dec 1 13:43:36 2011 +0100
Make PCIe handling a bit more generic
Change-Id: I1099969ed14debfd30f00f5efd10a9a6f3198d22
Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com>
---
SerialICE/scripts/serialice.lua | 41 ++++++++++++++++++++++++++++++--------
1 files changed, 32 insertions(+), 9 deletions(-)
diff --git a/SerialICE/scripts/serialice.lua b/SerialICE/scripts/serialice.lua
index 535cb0b..a41988a 100644
--- a/SerialICE/scripts/serialice.lua
+++ b/SerialICE/scripts/serialice.lua
@@ -50,6 +50,10 @@ function size_data(size, data)
end
end
+function pci_bdf(bus, dev, func, reg)
+ return 0x80000000 + bus*65536 + dev*2048 + func*256 + reg
+end
+
function new_list()
return { list = nil }
end
@@ -72,6 +76,7 @@ function walk_list(list, ...)
return false
end
+io_write_hooks = new_list()
msr_write_hooks = new_list()
msr_read_hooks = new_list()
@@ -102,6 +107,27 @@ function(addr, hi, lo, filtered)
return false
end)
+function trim (s)
+ return (string.gsub(s, "^%s*(.-)%s*$", "%1"))
+end
+
+mainboard = trim(SerialICE_mainboard)
+
+if northbridge == "intel-i945" then
+ prepend_to_list(io_write_hooks, function(port, size, data, filter)
+ if port == 0xcfc then
+ -- Catch PCIe base address
+ if SerialICE_pci_device == pci_bdf(0,0,0,0x48) then
+ PCIe_bar = bit.band(0xfc000000,data) % 0x100000000
+ PCIe_size = 64 * 1024 -- hard coded for now.
+ printf("PCIe BAR set up: 0x%08x\n", PCIe_bar)
+ return true
+ end
+ end
+ return false
+ end)
+end
+
-- In the beginning, during RAM initialization, it is essential that
-- all DRAM accesses are handled by the target, or RAM will not work
-- correctly. After RAM initialization, RAM access has no "special"
@@ -187,6 +213,10 @@ PCIe_size = 0
-- data Value returned if the write was *not* intercepted
function SerialICE_io_write_filter(port, size, data)
+ filter = { filter = false, data = data }
+ if walk_list(io_write_hooks, port, size, data, filter) then
+ return filter.filter, filter.data
+ end
-- **********************************************************
--
-- PCI config space handling
@@ -205,13 +235,6 @@ function SerialICE_io_write_filter(port, size, data)
return true, data
end
- -- Catch PCIe base address
- if SerialICE_pci_device == 0x80000048 then
- PCIe_bar = bit.band(0xfc000000,data)
- PCIe_size = 64 * 1024 -- hard coded for now.
- printf("PCIe BAR set up: 0x%08x\n", PCIe_bar)
- end
-
return false, data
end
@@ -369,7 +392,7 @@ function SerialICE_memory_read_filter(addr, size)
if addr >= 0xfff00000 and addr <= 0xffffffff then
-- ROM accesses go to Qemu only
return false, true, 0
- elseif addr >= 0xf0000000 and addr <= 0xf3ffffff then
+ elseif addr >= PCIe_bar and addr <= (PCIe_bar + PCIe_size) then
-- PCIe MMIO config space accesses are
-- exclusively handled by the SerialICE
-- target
@@ -448,7 +471,7 @@ function SerialICE_memory_write_filter(addr, size, data)
printf("\nWARNING: write access to ROM?\n")
-- ROM accesses go to Qemu only
return false, true, data
- elseif addr >= 0xf0000000 and addr <= 0xf3ffffff then
+ elseif addr >= PCIe_bar and addr <= (PCIe_bar + PCIe_size) then
-- PCIe MMIO config space accesses are
-- exclusively handled by the SerialICE
-- target
Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/462
-gerrit
commit f0397353c71561aa4eb203b9f04f45af02e19a24
Author: Patrick Georgi <patrick.georgi(a)secunet.com>
Date: Thu Dec 1 13:03:30 2011 +0100
Add hooking mechanism to provide for special parsers
Right now the code hardcodes a lot of special handling.
The idea is to move these into functions that are run until
one is successful, or use a standard routine if none claimed
responsibility.
Later-on, these handlers could be chipset specific and enabled
automatically to provide a better view of what's going on.
Change-Id: I10cf9debd718cf5f60a652d071dcb9356ac79a03
Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com>
---
SerialICE/scripts/serialice.lua | 60 +++++++++++++++++++++++++++++++++++++-
1 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/SerialICE/scripts/serialice.lua b/SerialICE/scripts/serialice.lua
index ef77488..535cb0b 100644
--- a/SerialICE/scripts/serialice.lua
+++ b/SerialICE/scripts/serialice.lua
@@ -50,6 +50,58 @@ function size_data(size, data)
end
end
+function new_list()
+ return { list = nil }
+end
+
+function prepend_to_list(list, value)
+ list.list = { next = list.list, value = value }
+end
+
+function walk_list(list, ...)
+ if list == nil or list.list == nil then
+ return false
+ end
+ local l = list.list
+ while l do
+ if l.value(...) then
+ return true
+ end
+ l = l.next
+ end
+ return false
+end
+
+msr_write_hooks = new_list()
+msr_read_hooks = new_list()
+
+-- handle MTRRs
+prepend_to_list(msr_write_hooks,
+function(addr, hi, lo, filtered)
+ if addr >= 0x200 and addr < 0x210 then
+ if addr % 2 == 0 then
+ mt = lo % 0x100
+ if mt == 0 then memtype = "Uncacheable"
+ elseif mt == 1 then memtype = "Write-Combine"
+ elseif mt == 4 then memtype = "Write-Through"
+ elseif mt == 5 then memtype = "Write-Protect"
+ elseif mt == 6 then memtype = "Write-Back"
+ else memtype = "Unknown"
+ end
+ printf("CPU: Set MTRR %x base to %08x.%08x (%s)\n", (addr - 0x200) / 2, hi, bit.band(lo, 0xffffff00), memtype)
+ else
+ if bit.band(lo, 0x800) == 0x800 then
+ valid = "valid"
+ else
+ valid = "disabled"
+ end
+ printf("CPU: Set MTRR %x mask to %08x.%08x (%s)\n", (addr - 0x200) / 2, hi, bit.band(lo, 0xfffff000), valid)
+ end
+ return true
+ end
+ return false
+end)
+
-- In the beginning, during RAM initialization, it is essential that
-- all DRAM accesses are handled by the target, or RAM will not work
-- correctly. After RAM initialization, RAM access has no "special"
@@ -606,12 +658,16 @@ end
function SerialICE_msr_write_log(addr, hi, lo, filtered)
log_cs_ip()
- printf("CPU: wrmsr %08x <= %08x.%08x\n", addr, hi, lo)
+ if not walk_list(msr_write_hooks, addr, hi, lo, filtered) then
+ printf("CPU: wrmsr %08x <= %08x.%08x\n", addr, hi, lo)
+ end
end
function SerialICE_msr_read_log(addr, hi, lo, filtered)
log_cs_ip()
- printf("CPU: rdmsr %08x => %08x.%08x\n", addr, hi, lo)
+ if not walk_list(msr_write_hooks, addr, hi, lo, filtered) then
+ printf("CPU: rdmsr %08x => %08x.%08x\n", addr, hi, lo)
+ end
end
function SerialICE_cpuid_log(in_eax, in_ecx, out_eax, out_ebx, out_ecx, out_edx, filtered)
the following patch was just integrated into master:
commit d51fc6feb10e755ad2b9d38502b3088d6167f240
Author: Patrick Georgi <patrick.georgi(a)secunet.com>
Date: Thu Dec 1 12:09:56 2011 +0100
Reorganize code to support "high speed" serial transfers
This requires some chipset specific handling in case transfers
faster than 115200bps are used. Due to that, the build must be
reorganized a bit.
This change doesn't actually add high speed support code, but
does the reorganization only.
As an example, Kontron 986LCD-M was converted to "new-style":
southbridge code now resides in southbridge/intel-ich7.c,
superio code in superio/winbond-w83627thg.c, both pointed at
using Kconfig.
Other boards using this southbridge or superio can reuse the files,
reducing duplication.
Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com>
Change-Id: I5a36e939a15fea9ed58bf25dbcb322d0e6aa7c5a
See http://review.coreboot.org/460 for details.
-gerrit
