Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/466
-gerrit
commit 01417da079989be1558551e404022480a7e7230b
Author: Patrick Georgi <patrick.georgi(a)secunet.com>
Date: Thu Dec 1 15:09:08 2011 +0100
Make ROM size more easily configurable
Change-Id: I683ebcb59c17b2460c797d6e94f3c15384d26407
Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com>
---
SerialICE/scripts/serialice.lua | 9 ++++++---
1 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/SerialICE/scripts/serialice.lua b/SerialICE/scripts/serialice.lua
index 7346046..3a8bf74 100644
--- a/SerialICE/scripts/serialice.lua
+++ b/SerialICE/scripts/serialice.lua
@@ -209,6 +209,9 @@ ip_logging = false
SerialICE_pci_device = 0
+rom_size = 4 * 1024 * 1024
+rom_base = 0x100000000 - rom_size
+
-- SerialICE_io_read_filter is the filter function for IO reads.
--
-- Parameters:
@@ -456,7 +459,7 @@ function SerialICE_memory_read_filter(addr, size)
return false, true, 0
end
- if addr >= 0xfff00000 and addr <= 0xffffffff then
+ if addr >= rom_base and addr <= 0xffffffff then
-- ROM accesses go to Qemu only
return false, true, 0
elseif addr >= PCIe_bar and addr <= (PCIe_bar + PCIe_size) then
@@ -532,7 +535,7 @@ function SerialICE_memory_write_filter(addr, size, data)
return false, true, data
end
- if addr >= 0xfff00000 and addr <= 0xffffffff then
+ if addr >= rom_base and addr <= 0xffffffff then
printf("\nWARNING: write access to ROM?\n")
-- ROM accesses go to Qemu only
return false, true, data
@@ -671,7 +674,7 @@ function SerialICE_memory_read_log(addr, size, data, target)
if addr >= 0xe0000 and addr <= 0xfffff and not log_rom_access then
return
end
- if addr >= 0xfff00000 and addr <= 0xffffffff and not log_rom_access then
+ if addr >= rom_base and addr <= 0xffffffff and not log_rom_access then
return
end
Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/464
-gerrit
commit 93094522ace3e7b7f508f4d41f3550de660a3be9
Author: Patrick Georgi <patrick.georgi(a)secunet.com>
Date: Thu Dec 1 14:00:41 2011 +0100
Refactor CAR region code
Change-Id: If7c4cff1690c4d48cca50d03d75ec533b26c8d9f
Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com>
---
SerialICE/scripts/serialice.lua | 56 ++++++++++++++++++++++++++------------
1 files changed, 38 insertions(+), 18 deletions(-)
diff --git a/SerialICE/scripts/serialice.lua b/SerialICE/scripts/serialice.lua
index a41988a..2472b49 100644
--- a/SerialICE/scripts/serialice.lua
+++ b/SerialICE/scripts/serialice.lua
@@ -54,6 +54,27 @@ function pci_bdf(bus, dev, func, reg)
return 0x80000000 + bus*65536 + dev*2048 + func*256 + reg
end
+car_regions = { list = nil }
+
+function new_car_region(start, size)
+ car_regions.list = { next = car_regions.list, start = start, size = size }
+ SerialICE_register_physical(start, size)
+end
+
+function is_car(addr)
+ if car_regions.list == nil then
+ return false
+ end
+ local l = car_regions.list
+ while l do
+ if addr >= l.start and addr < l.start + l.size then
+ return true
+ end
+ l = l.next
+ end
+ return false
+end
+
function new_list()
return { list = nil }
end
@@ -389,6 +410,12 @@ function SerialICE_memory_read_filter(addr, size)
-- return false, false, 0x23232323
-- end
+ -- Cache-As-RAM is exclusively
+ -- handled by Qemu (RAM backed)
+ if is_car(addr) then
+ return false, true, 0
+ end
+
if addr >= 0xfff00000 and addr <= 0xffffffff then
-- ROM accesses go to Qemu only
return false, true, 0
@@ -401,14 +428,6 @@ function SerialICE_memory_read_filter(addr, size)
-- Intel chipset BARs are exclusively
-- handled by the SerialICE target
return true, false, 0
- elseif addr >= 0xffd80000 and addr <= 0xffdfffff then
- -- coreboot Cache-As-RAM is exclusively
- -- handled by Qemu (RAM backed)
- return false, true, 0
- elseif addr >= 0xffbc0000 and addr <= 0xffbfffff then
- -- AMI Cache-As-RAM is exclusively
- -- handled by Qemu (RAM backed)
- return false, true, 0
elseif addr >= 0xfee00000 and addr <= 0xfeefffff then
-- Local APIC.. Hm, not sure what to do here.
-- We should avoid that someone wakes up cores
@@ -467,6 +486,12 @@ end
-- result Data to be written (may be changed in filter)
function SerialICE_memory_write_filter(addr, size, data)
+ -- Cache-As-RAM is exclusively
+ -- handled by Qemu (RAM backed)
+ if is_car(addr) then
+ return false, true, data
+ end
+
if addr >= 0xfff00000 and addr <= 0xffffffff then
printf("\nWARNING: write access to ROM?\n")
-- ROM accesses go to Qemu only
@@ -480,14 +505,6 @@ function SerialICE_memory_write_filter(addr, size, data)
-- Intel chipset BARs are exclusively
-- handled by the SerialICE target
return true, false, data
- elseif addr >= 0xffd80000 and addr <= 0xffdfffff then
- -- coreboot Cache-As-RAM is exclusively
- -- handled by Qemu (RAM backed)
- return false, true, data
- elseif addr >= 0xffbc0000 and addr <= 0xffbfffff then
- -- AMI Cache-As-RAM is exclusively
- -- handled by Qemu (RAM backed)
- return false, true, data
elseif addr >= 0xfee00000 and addr <= 0xfeefffff then
-- Local APIC.. Hm, not sure what to do here.
-- We should avoid that someone wakes up cores
@@ -707,11 +724,14 @@ printf("SerialICE: Registering physical memory areas for Cache-As-Ram:\n")
-- Register Phoenix BIOS Cache as RAM area as normal RAM
-- 0xffd80000 - 0xffdfffff
-SerialICE_register_physical(0xffd80000, 0x80000)
+new_car_region(0xffd80000, 0x80000)
-- Register AMI BIOS Cache as RAM area as normal RAM
-- 0xffbc0000 - 0xffbfffff
-SerialICE_register_physical(0xffbc0000, 0x40000)
+new_car_region(0xffbc0000, 0x40000)
+
+-- current Phoenix BIOS
+new_car_region(0xde000, 0x2000)
printf("SerialICE: LUA script initialized.\n")
Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/463
-gerrit
commit f91e38b253917c3dc505ea8dc2f8f8f4029fdd03
Author: Patrick Georgi <patrick.georgi(a)secunet.com>
Date: Thu Dec 1 13:43:36 2011 +0100
Make PCIe handling a bit more generic
Change-Id: I1099969ed14debfd30f00f5efd10a9a6f3198d22
Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com>
---
SerialICE/scripts/serialice.lua | 41 ++++++++++++++++++++++++++++++--------
1 files changed, 32 insertions(+), 9 deletions(-)
diff --git a/SerialICE/scripts/serialice.lua b/SerialICE/scripts/serialice.lua
index 535cb0b..a41988a 100644
--- a/SerialICE/scripts/serialice.lua
+++ b/SerialICE/scripts/serialice.lua
@@ -50,6 +50,10 @@ function size_data(size, data)
end
end
+function pci_bdf(bus, dev, func, reg)
+ return 0x80000000 + bus*65536 + dev*2048 + func*256 + reg
+end
+
function new_list()
return { list = nil }
end
@@ -72,6 +76,7 @@ function walk_list(list, ...)
return false
end
+io_write_hooks = new_list()
msr_write_hooks = new_list()
msr_read_hooks = new_list()
@@ -102,6 +107,27 @@ function(addr, hi, lo, filtered)
return false
end)
+function trim (s)
+ return (string.gsub(s, "^%s*(.-)%s*$", "%1"))
+end
+
+mainboard = trim(SerialICE_mainboard)
+
+if northbridge == "intel-i945" then
+ prepend_to_list(io_write_hooks, function(port, size, data, filter)
+ if port == 0xcfc then
+ -- Catch PCIe base address
+ if SerialICE_pci_device == pci_bdf(0,0,0,0x48) then
+ PCIe_bar = bit.band(0xfc000000,data) % 0x100000000
+ PCIe_size = 64 * 1024 -- hard coded for now.
+ printf("PCIe BAR set up: 0x%08x\n", PCIe_bar)
+ return true
+ end
+ end
+ return false
+ end)
+end
+
-- In the beginning, during RAM initialization, it is essential that
-- all DRAM accesses are handled by the target, or RAM will not work
-- correctly. After RAM initialization, RAM access has no "special"
@@ -187,6 +213,10 @@ PCIe_size = 0
-- data Value returned if the write was *not* intercepted
function SerialICE_io_write_filter(port, size, data)
+ filter = { filter = false, data = data }
+ if walk_list(io_write_hooks, port, size, data, filter) then
+ return filter.filter, filter.data
+ end
-- **********************************************************
--
-- PCI config space handling
@@ -205,13 +235,6 @@ function SerialICE_io_write_filter(port, size, data)
return true, data
end
- -- Catch PCIe base address
- if SerialICE_pci_device == 0x80000048 then
- PCIe_bar = bit.band(0xfc000000,data)
- PCIe_size = 64 * 1024 -- hard coded for now.
- printf("PCIe BAR set up: 0x%08x\n", PCIe_bar)
- end
-
return false, data
end
@@ -369,7 +392,7 @@ function SerialICE_memory_read_filter(addr, size)
if addr >= 0xfff00000 and addr <= 0xffffffff then
-- ROM accesses go to Qemu only
return false, true, 0
- elseif addr >= 0xf0000000 and addr <= 0xf3ffffff then
+ elseif addr >= PCIe_bar and addr <= (PCIe_bar + PCIe_size) then
-- PCIe MMIO config space accesses are
-- exclusively handled by the SerialICE
-- target
@@ -448,7 +471,7 @@ function SerialICE_memory_write_filter(addr, size, data)
printf("\nWARNING: write access to ROM?\n")
-- ROM accesses go to Qemu only
return false, true, data
- elseif addr >= 0xf0000000 and addr <= 0xf3ffffff then
+ elseif addr >= PCIe_bar and addr <= (PCIe_bar + PCIe_size) then
-- PCIe MMIO config space accesses are
-- exclusively handled by the SerialICE
-- target
Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/462
-gerrit
commit 953698142a9a0ac17af089b89d82b03cac409262
Author: Patrick Georgi <patrick.georgi(a)secunet.com>
Date: Thu Dec 1 13:03:30 2011 +0100
Add hooking mechanism to provide for special parsers
Right now the code hardcodes a lot of special handling.
The idea is to move these into functions that are run until
one is successful, or use a standard routine if none claimed
responsibility.
Later-on, these handlers could be chipset specific and enabled
automatically to provide a better view of what's going on.
Change-Id: I10cf9debd718cf5f60a652d071dcb9356ac79a03
Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com>
---
SerialICE/scripts/serialice.lua | 60 +++++++++++++++++++++++++++++++++++++-
1 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/SerialICE/scripts/serialice.lua b/SerialICE/scripts/serialice.lua
index ef77488..535cb0b 100644
--- a/SerialICE/scripts/serialice.lua
+++ b/SerialICE/scripts/serialice.lua
@@ -50,6 +50,58 @@ function size_data(size, data)
end
end
+function new_list()
+ return { list = nil }
+end
+
+function prepend_to_list(list, value)
+ list.list = { next = list.list, value = value }
+end
+
+function walk_list(list, ...)
+ if list == nil or list.list == nil then
+ return false
+ end
+ local l = list.list
+ while l do
+ if l.value(...) then
+ return true
+ end
+ l = l.next
+ end
+ return false
+end
+
+msr_write_hooks = new_list()
+msr_read_hooks = new_list()
+
+-- handle MTRRs
+prepend_to_list(msr_write_hooks,
+function(addr, hi, lo, filtered)
+ if addr >= 0x200 and addr < 0x210 then
+ if addr % 2 == 0 then
+ mt = lo % 0x100
+ if mt == 0 then memtype = "Uncacheable"
+ elseif mt == 1 then memtype = "Write-Combine"
+ elseif mt == 4 then memtype = "Write-Through"
+ elseif mt == 5 then memtype = "Write-Protect"
+ elseif mt == 6 then memtype = "Write-Back"
+ else memtype = "Unknown"
+ end
+ printf("CPU: Set MTRR %x base to %08x.%08x (%s)\n", (addr - 0x200) / 2, hi, bit.band(lo, 0xffffff00), memtype)
+ else
+ if bit.band(lo, 0x800) == 0x800 then
+ valid = "valid"
+ else
+ valid = "disabled"
+ end
+ printf("CPU: Set MTRR %x mask to %08x.%08x (%s)\n", (addr - 0x200) / 2, hi, bit.band(lo, 0xfffff000), valid)
+ end
+ return true
+ end
+ return false
+end)
+
-- In the beginning, during RAM initialization, it is essential that
-- all DRAM accesses are handled by the target, or RAM will not work
-- correctly. After RAM initialization, RAM access has no "special"
@@ -606,12 +658,16 @@ end
function SerialICE_msr_write_log(addr, hi, lo, filtered)
log_cs_ip()
- printf("CPU: wrmsr %08x <= %08x.%08x\n", addr, hi, lo)
+ if not walk_list(msr_write_hooks, addr, hi, lo, filtered) then
+ printf("CPU: wrmsr %08x <= %08x.%08x\n", addr, hi, lo)
+ end
end
function SerialICE_msr_read_log(addr, hi, lo, filtered)
log_cs_ip()
- printf("CPU: rdmsr %08x => %08x.%08x\n", addr, hi, lo)
+ if not walk_list(msr_write_hooks, addr, hi, lo, filtered) then
+ printf("CPU: rdmsr %08x => %08x.%08x\n", addr, hi, lo)
+ end
end
function SerialICE_cpuid_log(in_eax, in_ecx, out_eax, out_ebx, out_ecx, out_edx, filtered)