December 2011 - SerialICE - mail.coreboot.org

Patch set updated for serialice: d51fc6f Reorganize code to support "high speed" serial transfers
by Patrick Georgi Dec. 3, 2011

Dec. 3, 2011

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/460 -gerrit commit d51fc6feb10e755ad2b9d38502b3088d6167f240 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Dec 1 12:09:56 2011 +0100 Reorganize code to support "high speed" serial transfers This requires some chipset specific handling in case transfers faster than 115200bps are used. Due to that, the build must be reorganized a bit. This change doesn't actually add high speed support code, but does the reorganization only. As an example, Kontron 986LCD-M was converted to "new-style": southbridge code now resides in southbridge/intel-ich7.c, superio code in superio/winbond-w83627thg.c, both pointed at using Kconfig. Other boards using this southbridge or superio can reuse the files, reducing duplication. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Change-Id: I5a36e939a15fea9ed58bf25dbcb322d0e6aa7c5a --- SerialICE/Kconfig | 22 ++++++++ SerialICE/Makefile | 2 +- SerialICE/chipset.c | 9 +++ SerialICE/mainboard/kontron_986lcd-m.c | 86 -------------------------------- SerialICE/serial.c | 10 ++++ SerialICE/serialice.c | 6 +- SerialICE/southbridge/intel-ich7.c | 73 +++++++++++++++++++++++++++ SerialICE/superio/winbond-w83627thg.c | 58 +++++++++++++++++++++ 8 files changed, 176 insertions(+), 90 deletions(-) diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig index a28b4c5..48d43b7 100644 --- a/SerialICE/Kconfig +++ b/SerialICE/Kconfig @@ -124,6 +124,16 @@ config BOARD_INIT default "hp_dl165_g6.c" if BOARD_HP_DL165_G6 default "wyse_s50.c" if BOARD_WYSE_S50 default "asrock_p4i65gv.c" if BOARD_ASROCK_P4I65GV + +config SOUTHBRIDGE_INIT + string + default "southbridge/intel-ich7.c" if BOARD_KONTRON_986LCD_M + +config SUPERIO_INIT + string + default "superio/winbond-w83627thg.c" if BOARD_KONTRON_986LCD_M + + choice prompt "Target communication" @@ -192,6 +202,16 @@ choice default SERIAL_115200 depends on SERIAL +config SERIAL_460800 + bool "460800 bps" + help + Set serial port speed to 460800 bps. + +config SERIAL_230400 + bool "230400 bps" + help + Set serial port speed to 230400 bps. + config SERIAL_115200 bool "115200 bps" help @@ -221,6 +241,8 @@ endchoice config SERIAL_BAUDRATE int + default 460800 if SERIAL_460800 + default 230400 if SERIAL_230400 default 115200 if SERIAL_115200 default 57600 if SERIAL_57600 default 38400 if SERIAL_38400 diff --git a/SerialICE/Makefile b/SerialICE/Makefile index 2fce4cc..102be31 100644 --- a/SerialICE/Makefile +++ b/SerialICE/Makefile @@ -120,7 +120,7 @@ $(obj)/serialice.elf: $(obj)/serialice.o $(obj)/start.o $(src)/serialice.ld $(obj)/serialice.S: $(SOURCES) $(obj)/romcc $(Q)printf " ROMCC $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(obj)/romcc -mcpu=i386 $(INCLUDES) -I. -Imainboard -DVERSION=\"$(VERSION)\" -o $@.tmp $< + $(Q)$(obj)/romcc -mcpu=i386 $(INCLUDES) -I. -Imainboard -Isouthbridge -Isuperio -DVERSION=\"$(VERSION)\" -o $@.tmp $< $(Q)printf ".section \".rom.text\"\n.globl main\nmain:\n" > $@ $(Q)cat $@.tmp >> $@ $(Q)rm $@.tmp diff --git a/SerialICE/chipset.c b/SerialICE/chipset.c index 97d0cbb..8ab4515 100644 --- a/SerialICE/chipset.c +++ b/SerialICE/chipset.c @@ -123,5 +123,14 @@ static void pnp_exit_ext_func_mode_ite(u16 port) pnp_write_register(port, 0x02, 0x02); } +#ifndef CONFIG_SOUTHBRIDGE_INIT +#define CONFIG_SOUTHBRIDGE_INIT "types.h" +#endif +#include CONFIG_SOUTHBRIDGE_INIT + +#ifndef CONFIG_SUPERIO_INIT +#define CONFIG_SUPERIO_INIT "types.h" +#endif +#include CONFIG_SUPERIO_INIT #include MAINBOARD diff --git a/SerialICE/mainboard/kontron_986lcd-m.c b/SerialICE/mainboard/kontron_986lcd-m.c index 53a7de0..62d8c46 100644 --- a/SerialICE/mainboard/kontron_986lcd-m.c +++ b/SerialICE/mainboard/kontron_986lcd-m.c @@ -21,92 +21,6 @@ const char boardname[33]="Kontron 986LCD-M "; -/* Hardware specific functions */ - -#define RCBA 0xfed1c000 -#define GCS 0x3410 -#define RCBA32(x) *((volatile u32 *)(RCBA + x)) - -static void southbridge_init(void) -{ - u16 reg16; - u32 reg32; - - // Set up RCBA - pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1); - -#if 0 - // port80 writes go to LPC: - reg32 = RCBA32(GCS); - reg32 = reg32 & ~0x04; - RCBA32(GCS) = reg32; - outb(0x23, 0x80); -#endif - - // Enable Serial IRQ - pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x64), 0xd0); - // Set COM1/COM2 decode range - pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x80), 0x0010); - // Enable COM1/COM2/KBD/SuperIO1+2 - pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x82), 0x340b); - // Enable HWM at 0xa00 - pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x84), 0x00fc0a01); - // COM3 decode - pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x88), 0x000403e9); - // COM4 decode - pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x8c), 0x000402e9); - // io 0x300 decode - pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x90), 0x00000301); - - // Disable watchdog -#define PMBASE 0x500 -#define TCOBASE (PMBASE + 0x60) - pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x40), PMBASE | 1); - pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x44), 0x80); - reg16 = inw(TCOBASE + 0x08); - reg16 |= (1 << 11); - outw(reg16, TCOBASE + 0x08); - outw(0x0008, TCOBASE + 0x04); - outw(0x0002, TCOBASE + 0x06); -} - -static void superio_init(void) -{ - pnp_enter_ext_func_mode(0x2e); - - pnp_set_logical_device(0x2e, 2); // COM-A - pnp_set_enable(0x2e, 0); - pnp_set_iobase0(0x2e, 0x3f8); - pnp_set_irq0(0x2e, 4); - pnp_set_enable(0x2e, 1); - - pnp_set_logical_device(0x2e, 3); // COM-B - pnp_set_enable(0x2e, 0); - pnp_set_iobase0(0x2e, 0x2f8); - pnp_set_irq0(0x2e, 3); - pnp_set_enable(0x2e, 1); - - pnp_exit_ext_func_mode(0x2e); - - pnp_enter_ext_func_mode(0x4e); - - // Set COM3 to sane non-conflicting values - pnp_set_logical_device(0x4e, 2); // COM-A - pnp_set_enable(0x4e, 0); - pnp_set_iobase0(0x4e, 0x3e8); - pnp_set_irq0(0x4e, 11); - pnp_set_enable(0x4e, 1); - - // Set COM4 to sane non-conflicting values - pnp_set_logical_device(0x4e, 3); // COM-B - pnp_set_enable(0x4e, 0); - pnp_set_iobase0(0x4e, 0x2e8); - pnp_set_irq0(0x4e, 10); - pnp_set_enable(0x4e, 1); - - pnp_exit_ext_func_mode(0x4e); -} - static void chipset_init(void) { southbridge_init(); diff --git a/SerialICE/serial.c b/SerialICE/serial.c index 9aaecb6..eee7e49 100644 --- a/SerialICE/serial.c +++ b/SerialICE/serial.c @@ -39,7 +39,17 @@ static void sio_init(void) { +#if SIO_SPEED > 115200 + /* "high speed" serial requires special chip setup + * (to be done in superio_init), and special divisor + * values (implement superio_serial_divisor() for that). + * Maybe it requires even more, but so far that seems + * to be enough. + */ + int divisor = superio_serial_divisor(SIO_SPEED); +#else int divisor = 115200 / SIO_SPEED; +#endif int lcs = 3; outb(0x00, SIO_PORT + UART_IER); outb(0x01, SIO_PORT + UART_FCR); diff --git a/SerialICE/serialice.c b/SerialICE/serialice.c index 35531dc..649ee11 100644 --- a/SerialICE/serialice.c +++ b/SerialICE/serialice.c @@ -21,13 +21,13 @@ #include <serialice.h> #include <io.h> -/* SIO functions */ -#include "serial.c" - /* Hardware specific functions */ #include "chipset.c" +/* SIO functions */ +#include "serial.c" + /* Accessor functions */ static void serialice_read_memory(void) diff --git a/SerialICE/southbridge/intel-ich7.c b/SerialICE/southbridge/intel-ich7.c new file mode 100644 index 0000000..3688084 --- /dev/null +++ b/SerialICE/southbridge/intel-ich7.c @@ -0,0 +1,73 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This initializes Intel's ICH7 that + * o the Super IO is accessible, + * o legacy serial port I/O ports are decoded, + * o the watchdog is turned off + */ + +#define RCBA 0xfed1c000 +#define GCS 0x3410 +#define RCBA32(x) *((volatile u32 *)(RCBA + x)) + +static void southbridge_init(void) +{ + u16 reg16; + u32 reg32; + + // Set up RCBA + pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1); + +#if 0 + // port80 writes go to LPC: + reg32 = RCBA32(GCS); + reg32 = reg32 & ~0x04; + RCBA32(GCS) = reg32; + outb(0x23, 0x80); +#endif + + // Enable Serial IRQ + pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x64), 0xd0); + // Set COM1/COM2 decode range + pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x80), 0x0010); + // Enable COM1/COM2/KBD/SuperIO1+2 + pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x82), 0x340b); + // Enable HWM at 0xa00 + pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x84), 0x00fc0a01); + // COM3 decode + pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x88), 0x000403e9); + // COM4 decode + pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x8c), 0x000402e9); + // io 0x300 decode + pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x90), 0x00000301); + + // Disable watchdog +#define PMBASE 0x500 +#define TCOBASE (PMBASE + 0x60) + pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x40), PMBASE | 1); + pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x44), 0x80); + reg16 = inw(TCOBASE + 0x08); + reg16 |= (1 << 11); + outw(reg16, TCOBASE + 0x08); + outw(0x0008, TCOBASE + 0x04); + outw(0x0002, TCOBASE + 0x06); +} + + diff --git a/SerialICE/superio/winbond-w83627thg.c b/SerialICE/superio/winbond-w83627thg.c new file mode 100644 index 0000000..5213921 --- /dev/null +++ b/SerialICE/superio/winbond-w83627thg.c @@ -0,0 +1,58 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This sets up the Super IO so up to 4 COM ports are usable */ + +static void superio_init(void) +{ + pnp_enter_ext_func_mode(0x2e); + + pnp_set_logical_device(0x2e, 2); // COM-A + pnp_set_enable(0x2e, 0); + pnp_set_iobase0(0x2e, 0x3f8); + pnp_set_irq0(0x2e, 4); + pnp_set_enable(0x2e, 1); + + pnp_set_logical_device(0x2e, 3); // COM-B + pnp_set_enable(0x2e, 0); + pnp_set_iobase0(0x2e, 0x2f8); + pnp_set_irq0(0x2e, 3); + pnp_set_enable(0x2e, 1); + + pnp_exit_ext_func_mode(0x2e); + + pnp_enter_ext_func_mode(0x4e); + + // Set COM3 to sane non-conflicting values + pnp_set_logical_device(0x4e, 2); // COM-A + pnp_set_enable(0x4e, 0); + pnp_set_iobase0(0x4e, 0x3e8); + pnp_set_irq0(0x4e, 11); + pnp_set_enable(0x4e, 1); + + // Set COM4 to sane non-conflicting values + pnp_set_logical_device(0x4e, 3); // COM-B + pnp_set_enable(0x4e, 0); + pnp_set_iobase0(0x4e, 0x2e8); + pnp_set_irq0(0x4e, 10); + pnp_set_enable(0x4e, 1); + + pnp_exit_ext_func_mode(0x4e); +} +

1 0

New patch to review for serialice: b1c818a Convert memory logging to hooks
by Patrick Georgi Dec. 1, 2011

Dec. 1, 2011

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/467 -gerrit commit b1c818a593947a0a2a6df79782d8e54b3cd5f36d Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Dec 1 15:23:14 2011 +0100 Convert memory logging to hooks Change-Id: I09c2a97964d4e3101000a10fac86df283eb9506c Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- SerialICE/scripts/serialice.lua | 64 +++++++++++++++++++++++--------------- 1 files changed, 39 insertions(+), 25 deletions(-) diff --git a/SerialICE/scripts/serialice.lua b/SerialICE/scripts/serialice.lua index 3a8bf74..0e7e902 100644 --- a/SerialICE/scripts/serialice.lua +++ b/SerialICE/scripts/serialice.lua @@ -97,12 +97,40 @@ function walk_list(list, ...) return false end -io_write_hooks = new_list() -io_write_log_hooks = new_list() io_read_hooks = new_list() +io_write_hooks = new_list() io_read_log_hooks = new_list() -msr_write_hooks = new_list() +io_write_log_hooks = new_list() + msr_read_hooks = new_list() +msr_write_hooks = new_list() + +mem_read_log_hooks = new_list() +mem_write_log_hooks = new_list() + +prepend_to_list(mem_read_log_hooks, function(addr, size, data, target) + if (PCIe_bar ~= 0) and addr >= PCIe_bar and addr <= (PCIe_bar + PCIe_size) then + printf("PCIe %x:%02x.%x R.%02x => %s\n", + bit.band(0xff,bit.rshift(addr, 20)), + bit.band(0x1f,bit.rshift(addr, 15)), + bit.band(0x7,bit.rshift(addr, 12)), + bit.band(0xfff,addr), + size_data(size, data)) + return true + end +end) + +prepend_to_list(mem_write_log_hooks, function(addr, size, data, target) + if (PCIe_bar ~= 0) and addr >= PCIe_bar and addr <= (PCIe_bar + PCIe_size) then + printf("PCIe %x:%02x.%x R.%02x <= %s\n", + bit.band(0xff,bit.rshift(addr, 20)), + bit.band(0x1f,bit.rshift(addr, 15)), + bit.band(0x7,bit.rshift(addr, 12)), + bit.band(0xfff,addr), + size_data(size, data)) + return true + end +end) prepend_to_list(io_write_log_hooks, function(port, size, data, target) if port == 0xcf9 then @@ -646,22 +674,15 @@ function SerialICE_memory_write_log(addr, size, data, target) log_cs_ip() + if walk_list(mem_write_log_hooks, addr, size, data, target) then + return + end + printf("MEM: write%s %08x <= %s", size_suffix(size), addr, size_data(size, data)) if target then printf(" *") end printf("\n") - - -- ********************************************************** - -- - - if (PCIe_bar ~= 0) and addr >= PCIe_bar and addr <= (PCIe_bar + PCIe_size) then - printf("PCIe %x:%02x.%x R.%02x\n", - bit.band(0xff,bit.rshift(addr, 20)), - bit.band(0x1f,bit.rshift(addr, 15)), - bit.band(0x7,bit.rshift(addr, 12)), - bit.band(0xfff,addr)) - end end function SerialICE_memory_read_log(addr, size, data, target) @@ -680,22 +701,15 @@ function SerialICE_memory_read_log(addr, size, data, target) log_cs_ip() + if walk_list(mem_read_log_hooks, addr, size, data, target) then + return + end + printf("MEM: read%s %08x => %s", size_suffix(size), addr, size_data(size, data)) if target then printf(" *") end printf("\n") - - -- ********************************************************** - -- - - if (PCIe_bar ~= 0) and addr >= PCIe_bar and addr <= (PCIe_bar + PCIe_size) then - printf("PCIe %x:%02x.%x R.%02x\n", - bit.band(0xff,bit.rshift(addr, 20)), - bit.band(0x1f,bit.rshift(addr, 15)), - bit.band(0x7,bit.rshift(addr, 12)), - bit.band(0xfff,addr)) - end end function SerialICE_io_write_log(port, size, data, target)

1 0

New patch to review for serialice: 5e3678c Refactor printing data
by Patrick Georgi Dec. 1, 2011

Dec. 1, 2011

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/461 -gerrit commit 5e3678c89ea1e89a86779170b797b23205683186 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Dec 1 12:30:41 2011 +0100 Refactor printing data Change-Id: Iabbcb6e0cb05552d21bac2e32fea7365247fdee0 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- SerialICE/scripts/serialice.lua | 37 +++++++++++++++++++++---------------- 1 files changed, 21 insertions(+), 16 deletions(-) diff --git a/SerialICE/scripts/serialice.lua b/SerialICE/scripts/serialice.lua index a5dfa62..ef77488 100644 --- a/SerialICE/scripts/serialice.lua +++ b/SerialICE/scripts/serialice.lua @@ -32,6 +32,23 @@ function printf(s,...) return io.write(s:format(...)) end +function size_suffix(size) + if size == 1 then return "b" + elseif size == 2 then return "w" + elseif size == 4 then return "l" + elseif size == 8 then return "ll" + else return string.format("invalid size: %d", size) + end +end + +function size_data(size, data) + if size == 1 then return string.format("%02x", data) + elseif size == 2 then return string.format("%04x", data) + elseif size == 4 then return string.format("%08x", data) + elseif size == 8 then return string.format("%16x", data) + else return string.format("Error: size=%x", size) + end +end -- In the beginning, during RAM initialization, it is essential that -- all DRAM accesses are handled by the target, or RAM will not work @@ -494,10 +511,7 @@ function SerialICE_memory_write_log(addr, size, data, target) log_cs_ip() - if size == 1 then printf("MEM: writeb %08x <= %02x", addr, data) - elseif size == 2 then printf("MEM: writew %08x <= %04x", addr, data) - elseif size == 4 then printf("MEM: writel %08x <= %08x", addr, data) - end + printf("MEM: write%s %08x <= %s", size_suffix(size), addr, size_data(size, data)) if target then printf(" *") end @@ -531,10 +545,7 @@ function SerialICE_memory_read_log(addr, size, data, target) log_cs_ip() - if size == 1 then printf("MEM: readb %08x => %02x", addr, data) - elseif size == 2 then printf("MEM: readw %08x => %04x", addr, data) - elseif size == 4 then printf("MEM: readl %08x => %08x", addr, data) - end + printf("MEM: read%s %08x => %s", size_suffix(size), addr, size_data(size, data)) if target then printf(" *") end @@ -555,10 +566,7 @@ end function SerialICE_io_write_log(port, size, data, target) log_cs_ip() - if size == 1 then printf("IO: outb %04x <= %02x\n", port, data) - elseif size == 2 then printf("IO: outw %04x <= %04x\n", port, data) - elseif size == 4 then printf("IO: outl %04x <= %08x\n", port, data) - end + printf("IO: out%s %04x <= %s\n", size_suffix(size), port, size_data(size, data)) -- ********************************************************** -- @@ -582,10 +590,7 @@ end function SerialICE_io_read_log(port, size, data, target) log_cs_ip() - if size == 1 then printf("IO: inb %04x => %02x\n", port, data) - elseif size == 2 then printf("IO: inw %04x => %04x\n", port, data) - elseif size == 4 then printf("IO: inl %04x => %08x\n", port, data) - end + printf("IO: in%s %04x => %s\n", size_suffix(size), port, size_data(size, data)) -- ********************************************************** --

1 0

New patch to review for serialice: 9536981 Add hooking mechanism to provide for special parsers
by Patrick Georgi Dec. 1, 2011

Dec. 1, 2011

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/462 -gerrit commit 953698142a9a0ac17af089b89d82b03cac409262 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Dec 1 13:03:30 2011 +0100 Add hooking mechanism to provide for special parsers Right now the code hardcodes a lot of special handling. The idea is to move these into functions that are run until one is successful, or use a standard routine if none claimed responsibility. Later-on, these handlers could be chipset specific and enabled automatically to provide a better view of what's going on. Change-Id: I10cf9debd718cf5f60a652d071dcb9356ac79a03 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- SerialICE/scripts/serialice.lua | 60 +++++++++++++++++++++++++++++++++++++- 1 files changed, 58 insertions(+), 2 deletions(-) diff --git a/SerialICE/scripts/serialice.lua b/SerialICE/scripts/serialice.lua index ef77488..535cb0b 100644 --- a/SerialICE/scripts/serialice.lua +++ b/SerialICE/scripts/serialice.lua @@ -50,6 +50,58 @@ function size_data(size, data) end end +function new_list() + return { list = nil } +end + +function prepend_to_list(list, value) + list.list = { next = list.list, value = value } +end + +function walk_list(list, ...) + if list == nil or list.list == nil then + return false + end + local l = list.list + while l do + if l.value(...) then + return true + end + l = l.next + end + return false +end + +msr_write_hooks = new_list() +msr_read_hooks = new_list() + +-- handle MTRRs +prepend_to_list(msr_write_hooks, +function(addr, hi, lo, filtered) + if addr >= 0x200 and addr < 0x210 then + if addr % 2 == 0 then + mt = lo % 0x100 + if mt == 0 then memtype = "Uncacheable" + elseif mt == 1 then memtype = "Write-Combine" + elseif mt == 4 then memtype = "Write-Through" + elseif mt == 5 then memtype = "Write-Protect" + elseif mt == 6 then memtype = "Write-Back" + else memtype = "Unknown" + end + printf("CPU: Set MTRR %x base to %08x.%08x (%s)\n", (addr - 0x200) / 2, hi, bit.band(lo, 0xffffff00), memtype) + else + if bit.band(lo, 0x800) == 0x800 then + valid = "valid" + else + valid = "disabled" + end + printf("CPU: Set MTRR %x mask to %08x.%08x (%s)\n", (addr - 0x200) / 2, hi, bit.band(lo, 0xfffff000), valid) + end + return true + end + return false +end) + -- In the beginning, during RAM initialization, it is essential that -- all DRAM accesses are handled by the target, or RAM will not work -- correctly. After RAM initialization, RAM access has no "special" @@ -606,12 +658,16 @@ end function SerialICE_msr_write_log(addr, hi, lo, filtered) log_cs_ip() - printf("CPU: wrmsr %08x <= %08x.%08x\n", addr, hi, lo) + if not walk_list(msr_write_hooks, addr, hi, lo, filtered) then + printf("CPU: wrmsr %08x <= %08x.%08x\n", addr, hi, lo) + end end function SerialICE_msr_read_log(addr, hi, lo, filtered) log_cs_ip() - printf("CPU: rdmsr %08x => %08x.%08x\n", addr, hi, lo) + if not walk_list(msr_write_hooks, addr, hi, lo, filtered) then + printf("CPU: rdmsr %08x => %08x.%08x\n", addr, hi, lo) + end end function SerialICE_cpuid_log(in_eax, in_ecx, out_eax, out_ebx, out_ecx, out_edx, filtered)

1 0

New patch to review for serialice: f91e38b Make PCIe handling a bit more generic
by Patrick Georgi Dec. 1, 2011

Dec. 1, 2011

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/463 -gerrit commit f91e38b253917c3dc505ea8dc2f8f8f4029fdd03 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Dec 1 13:43:36 2011 +0100 Make PCIe handling a bit more generic Change-Id: I1099969ed14debfd30f00f5efd10a9a6f3198d22 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- SerialICE/scripts/serialice.lua | 41 ++++++++++++++++++++++++++++++-------- 1 files changed, 32 insertions(+), 9 deletions(-) diff --git a/SerialICE/scripts/serialice.lua b/SerialICE/scripts/serialice.lua index 535cb0b..a41988a 100644 --- a/SerialICE/scripts/serialice.lua +++ b/SerialICE/scripts/serialice.lua @@ -50,6 +50,10 @@ function size_data(size, data) end end +function pci_bdf(bus, dev, func, reg) + return 0x80000000 + bus*65536 + dev*2048 + func*256 + reg +end + function new_list() return { list = nil } end @@ -72,6 +76,7 @@ function walk_list(list, ...) return false end +io_write_hooks = new_list() msr_write_hooks = new_list() msr_read_hooks = new_list() @@ -102,6 +107,27 @@ function(addr, hi, lo, filtered) return false end) +function trim (s) + return (string.gsub(s, "^%s*(.-)%s*$", "%1")) +end + +mainboard = trim(SerialICE_mainboard) + +if northbridge == "intel-i945" then + prepend_to_list(io_write_hooks, function(port, size, data, filter) + if port == 0xcfc then + -- Catch PCIe base address + if SerialICE_pci_device == pci_bdf(0,0,0,0x48) then + PCIe_bar = bit.band(0xfc000000,data) % 0x100000000 + PCIe_size = 64 * 1024 -- hard coded for now. + printf("PCIe BAR set up: 0x%08x\n", PCIe_bar) + return true + end + end + return false + end) +end + -- In the beginning, during RAM initialization, it is essential that -- all DRAM accesses are handled by the target, or RAM will not work -- correctly. After RAM initialization, RAM access has no "special" @@ -187,6 +213,10 @@ PCIe_size = 0 -- data Value returned if the write was *not* intercepted function SerialICE_io_write_filter(port, size, data) + filter = { filter = false, data = data } + if walk_list(io_write_hooks, port, size, data, filter) then + return filter.filter, filter.data + end -- ********************************************************** -- -- PCI config space handling @@ -205,13 +235,6 @@ function SerialICE_io_write_filter(port, size, data) return true, data end - -- Catch PCIe base address - if SerialICE_pci_device == 0x80000048 then - PCIe_bar = bit.band(0xfc000000,data) - PCIe_size = 64 * 1024 -- hard coded for now. - printf("PCIe BAR set up: 0x%08x\n", PCIe_bar) - end - return false, data end @@ -369,7 +392,7 @@ function SerialICE_memory_read_filter(addr, size) if addr >= 0xfff00000 and addr <= 0xffffffff then -- ROM accesses go to Qemu only return false, true, 0 - elseif addr >= 0xf0000000 and addr <= 0xf3ffffff then + elseif addr >= PCIe_bar and addr <= (PCIe_bar + PCIe_size) then -- PCIe MMIO config space accesses are -- exclusively handled by the SerialICE -- target @@ -448,7 +471,7 @@ function SerialICE_memory_write_filter(addr, size, data) printf("\nWARNING: write access to ROM?\n") -- ROM accesses go to Qemu only return false, true, data - elseif addr >= 0xf0000000 and addr <= 0xf3ffffff then + elseif addr >= PCIe_bar and addr <= (PCIe_bar + PCIe_size) then -- PCIe MMIO config space accesses are -- exclusively handled by the SerialICE -- target

1 0

New patch to review for serialice: 9309452 Refactor CAR region code
by Patrick Georgi Dec. 1, 2011

Dec. 1, 2011

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/464 -gerrit commit 93094522ace3e7b7f508f4d41f3550de660a3be9 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Dec 1 14:00:41 2011 +0100 Refactor CAR region code Change-Id: If7c4cff1690c4d48cca50d03d75ec533b26c8d9f Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- SerialICE/scripts/serialice.lua | 56 ++++++++++++++++++++++++++------------ 1 files changed, 38 insertions(+), 18 deletions(-) diff --git a/SerialICE/scripts/serialice.lua b/SerialICE/scripts/serialice.lua index a41988a..2472b49 100644 --- a/SerialICE/scripts/serialice.lua +++ b/SerialICE/scripts/serialice.lua @@ -54,6 +54,27 @@ function pci_bdf(bus, dev, func, reg) return 0x80000000 + bus*65536 + dev*2048 + func*256 + reg end +car_regions = { list = nil } + +function new_car_region(start, size) + car_regions.list = { next = car_regions.list, start = start, size = size } + SerialICE_register_physical(start, size) +end + +function is_car(addr) + if car_regions.list == nil then + return false + end + local l = car_regions.list + while l do + if addr >= l.start and addr < l.start + l.size then + return true + end + l = l.next + end + return false +end + function new_list() return { list = nil } end @@ -389,6 +410,12 @@ function SerialICE_memory_read_filter(addr, size) -- return false, false, 0x23232323 -- end + -- Cache-As-RAM is exclusively + -- handled by Qemu (RAM backed) + if is_car(addr) then + return false, true, 0 + end + if addr >= 0xfff00000 and addr <= 0xffffffff then -- ROM accesses go to Qemu only return false, true, 0 @@ -401,14 +428,6 @@ function SerialICE_memory_read_filter(addr, size) -- Intel chipset BARs are exclusively -- handled by the SerialICE target return true, false, 0 - elseif addr >= 0xffd80000 and addr <= 0xffdfffff then - -- coreboot Cache-As-RAM is exclusively - -- handled by Qemu (RAM backed) - return false, true, 0 - elseif addr >= 0xffbc0000 and addr <= 0xffbfffff then - -- AMI Cache-As-RAM is exclusively - -- handled by Qemu (RAM backed) - return false, true, 0 elseif addr >= 0xfee00000 and addr <= 0xfeefffff then -- Local APIC.. Hm, not sure what to do here. -- We should avoid that someone wakes up cores @@ -467,6 +486,12 @@ end -- result Data to be written (may be changed in filter) function SerialICE_memory_write_filter(addr, size, data) + -- Cache-As-RAM is exclusively + -- handled by Qemu (RAM backed) + if is_car(addr) then + return false, true, data + end + if addr >= 0xfff00000 and addr <= 0xffffffff then printf("\nWARNING: write access to ROM?\n") -- ROM accesses go to Qemu only @@ -480,14 +505,6 @@ function SerialICE_memory_write_filter(addr, size, data) -- Intel chipset BARs are exclusively -- handled by the SerialICE target return true, false, data - elseif addr >= 0xffd80000 and addr <= 0xffdfffff then - -- coreboot Cache-As-RAM is exclusively - -- handled by Qemu (RAM backed) - return false, true, data - elseif addr >= 0xffbc0000 and addr <= 0xffbfffff then - -- AMI Cache-As-RAM is exclusively - -- handled by Qemu (RAM backed) - return false, true, data elseif addr >= 0xfee00000 and addr <= 0xfeefffff then -- Local APIC.. Hm, not sure what to do here. -- We should avoid that someone wakes up cores @@ -707,11 +724,14 @@ printf("SerialICE: Registering physical memory areas for Cache-As-Ram:\n") -- Register Phoenix BIOS Cache as RAM area as normal RAM -- 0xffd80000 - 0xffdfffff -SerialICE_register_physical(0xffd80000, 0x80000) +new_car_region(0xffd80000, 0x80000) -- Register AMI BIOS Cache as RAM area as normal RAM -- 0xffbc0000 - 0xffbfffff -SerialICE_register_physical(0xffbc0000, 0x40000) +new_car_region(0xffbc0000, 0x40000) + +-- current Phoenix BIOS +new_car_region(0xde000, 0x2000) printf("SerialICE: LUA script initialized.\n")

1 0

New patch to review for serialice: 78b8ac1 Convert io logging functions to provide hooks
by Patrick Georgi Dec. 1, 2011

Dec. 1, 2011

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/465 -gerrit commit 78b8ac1f3946a9d27584554e3c800bf27949606a Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Dec 1 14:31:58 2011 +0100 Convert io logging functions to provide hooks Change-Id: Ib261b3812bba881d3a3124c5c0c36fa5e5ad2417 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- SerialICE/scripts/serialice.lua | 75 ++++++++++++++++++++++++--------------- 1 files changed, 46 insertions(+), 29 deletions(-) diff --git a/SerialICE/scripts/serialice.lua b/SerialICE/scripts/serialice.lua index 2472b49..7346046 100644 --- a/SerialICE/scripts/serialice.lua +++ b/SerialICE/scripts/serialice.lua @@ -98,9 +98,49 @@ function walk_list(list, ...) end io_write_hooks = new_list() +io_write_log_hooks = new_list() +io_read_hooks = new_list() +io_read_log_hooks = new_list() msr_write_hooks = new_list() msr_read_hooks = new_list() +prepend_to_list(io_write_log_hooks, function(port, size, data, target) + if port == 0xcf9 then + printf("Reset triggered at %04x:%04x\n", regs.cs, regs.eip); + return true + end +end) + +prepend_to_list(io_write_log_hooks, function(port, size, data, target) + if port == 0xcf8 then + return true -- Ignore + end + if port >= 0xcfc and port <= 0xcff then + printf("PCI %x:%02x.%x R.%02x <= %s\n", + bit.band(0xff,bit.rshift(SerialICE_pci_device, 16)), + bit.band(0x1f,bit.rshift(SerialICE_pci_device, 11)), + bit.band(0x7,bit.rshift(SerialICE_pci_device, 8)), + bit.band(0xff,SerialICE_pci_device + (port - 0xcfc)), + size_data(size, data)) + return true + end +end) + +prepend_to_list(io_read_log_hooks, function(port, size, data, target) + if port == 0xcf8 then + return true -- Ignore + end + if port >= 0xcfc and port <= 0xcff then + printf("PCI %x:%02x.%x R.%02x => %s\n", + bit.band(0xff,bit.rshift(SerialICE_pci_device, 16)), + bit.band(0x1f,bit.rshift(SerialICE_pci_device, 11)), + bit.band(0x7,bit.rshift(SerialICE_pci_device, 8)), + bit.band(0xff,SerialICE_pci_device + (port - 0xcfc)), + size_data(size, data)) + return true + end +end) + -- handle MTRRs prepend_to_list(msr_write_hooks, function(addr, hi, lo, filtered) @@ -657,43 +697,20 @@ end function SerialICE_io_write_log(port, size, data, target) log_cs_ip() - - printf("IO: out%s %04x <= %s\n", size_suffix(size), port, size_data(size, data)) - - -- ********************************************************** - -- - - if port >= 0xcfc and port <= 0xcff then - printf("PCI %x:%02x.%x R.%02x\n", - bit.band(0xff,bit.rshift(SerialICE_pci_device, 16)), - bit.band(0x1f,bit.rshift(SerialICE_pci_device, 11)), - bit.band(0x7,bit.rshift(SerialICE_pci_device, 8)), - bit.band(0xff,SerialICE_pci_device + (port - 0xcfc) )) + if walk_list(io_write_log_hooks, port, size, data, target) then + return end - -- ********************************************************** - -- - - if port == 0xcf9 then - printf("Reset triggered at %04x:%04x\n", regs.cs, regs.eip); - end + printf("IO: out%s %04x <= %s\n", size_suffix(size), port, size_data(size, data)) end function SerialICE_io_read_log(port, size, data, target) log_cs_ip() + if walk_list(io_read_log_hooks, port, size, data, target) then + return + end printf("IO: in%s %04x => %s\n", size_suffix(size), port, size_data(size, data)) - - -- ********************************************************** - -- - - if port >= 0xcfc and port <= 0xcff then - printf("PCI %x:%02x.%x R.%02x\n", - bit.band(0xff,bit.rshift(SerialICE_pci_device, 16)), - bit.band(0x1f,bit.rshift(SerialICE_pci_device, 11)), - bit.band(0x7,bit.rshift(SerialICE_pci_device, 8)), - bit.band(0xff,SerialICE_pci_device + (port - 0xcfc) )) - end end function SerialICE_msr_write_log(addr, hi, lo, filtered)

1 0

New patch to review for serialice: 01417da Make ROM size more easily configurable
by Patrick Georgi Dec. 1, 2011

Dec. 1, 2011

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/466 -gerrit commit 01417da079989be1558551e404022480a7e7230b Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Dec 1 15:09:08 2011 +0100 Make ROM size more easily configurable Change-Id: I683ebcb59c17b2460c797d6e94f3c15384d26407 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- SerialICE/scripts/serialice.lua | 9 ++++++--- 1 files changed, 6 insertions(+), 3 deletions(-) diff --git a/SerialICE/scripts/serialice.lua b/SerialICE/scripts/serialice.lua index 7346046..3a8bf74 100644 --- a/SerialICE/scripts/serialice.lua +++ b/SerialICE/scripts/serialice.lua @@ -209,6 +209,9 @@ ip_logging = false SerialICE_pci_device = 0 +rom_size = 4 * 1024 * 1024 +rom_base = 0x100000000 - rom_size + -- SerialICE_io_read_filter is the filter function for IO reads. -- -- Parameters: @@ -456,7 +459,7 @@ function SerialICE_memory_read_filter(addr, size) return false, true, 0 end - if addr >= 0xfff00000 and addr <= 0xffffffff then + if addr >= rom_base and addr <= 0xffffffff then -- ROM accesses go to Qemu only return false, true, 0 elseif addr >= PCIe_bar and addr <= (PCIe_bar + PCIe_size) then @@ -532,7 +535,7 @@ function SerialICE_memory_write_filter(addr, size, data) return false, true, data end - if addr >= 0xfff00000 and addr <= 0xffffffff then + if addr >= rom_base and addr <= 0xffffffff then printf("\nWARNING: write access to ROM?\n") -- ROM accesses go to Qemu only return false, true, data @@ -671,7 +674,7 @@ function SerialICE_memory_read_log(addr, size, data, target) if addr >= 0xe0000 and addr <= 0xfffff and not log_rom_access then return end - if addr >= 0xfff00000 and addr <= 0xffffffff and not log_rom_access then + if addr >= rom_base and addr <= 0xffffffff and not log_rom_access then return end

1 0

New patch to review for serialice: 4721aaa Support "high speed" serial transfers
by Patrick Georgi Dec. 1, 2011

Dec. 1, 2011

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/460 -gerrit commit 4721aaa7808c37e741559ac40c30372edbe983ab Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Dec 1 12:09:56 2011 +0100 Support "high speed" serial transfers This requires some chipset specific handling in case transfers faster than 115200bps are used. Due to that, the build must be reorganized a bit. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Change-Id: I5a36e939a15fea9ed58bf25dbcb322d0e6aa7c5a --- SerialICE/Kconfig | 20 ++++++++++++++++++++ SerialICE/Makefile | 2 +- SerialICE/chipset.c | 2 ++ SerialICE/serial.c | 10 ++++++++++ SerialICE/serialice.c | 6 +++--- 5 files changed, 36 insertions(+), 4 deletions(-) diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig index a28b4c5..917a4b1 100644 --- a/SerialICE/Kconfig +++ b/SerialICE/Kconfig @@ -124,6 +124,14 @@ config BOARD_INIT default "hp_dl165_g6.c" if BOARD_HP_DL165_G6 default "wyse_s50.c" if BOARD_WYSE_S50 default "asrock_p4i65gv.c" if BOARD_ASROCK_P4I65GV + +config SOUTHBRIDGE_INIT + string + +config SUPERIO_INIT + string + + choice prompt "Target communication" @@ -192,6 +200,16 @@ choice default SERIAL_115200 depends on SERIAL +config SERIAL_460800 + bool "460800 bps" + help + Set serial port speed to 460800 bps. + +config SERIAL_230400 + bool "230400 bps" + help + Set serial port speed to 230400 bps. + config SERIAL_115200 bool "115200 bps" help @@ -221,6 +239,8 @@ endchoice config SERIAL_BAUDRATE int + default 460800 if SERIAL_460800 + default 230400 if SERIAL_230400 default 115200 if SERIAL_115200 default 57600 if SERIAL_57600 default 38400 if SERIAL_38400 diff --git a/SerialICE/Makefile b/SerialICE/Makefile index 2fce4cc..102be31 100644 --- a/SerialICE/Makefile +++ b/SerialICE/Makefile @@ -120,7 +120,7 @@ $(obj)/serialice.elf: $(obj)/serialice.o $(obj)/start.o $(src)/serialice.ld $(obj)/serialice.S: $(SOURCES) $(obj)/romcc $(Q)printf " ROMCC $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(obj)/romcc -mcpu=i386 $(INCLUDES) -I. -Imainboard -DVERSION=\"$(VERSION)\" -o $@.tmp $< + $(Q)$(obj)/romcc -mcpu=i386 $(INCLUDES) -I. -Imainboard -Isouthbridge -Isuperio -DVERSION=\"$(VERSION)\" -o $@.tmp $< $(Q)printf ".section \".rom.text\"\n.globl main\nmain:\n" > $@ $(Q)cat $@.tmp >> $@ $(Q)rm $@.tmp diff --git a/SerialICE/chipset.c b/SerialICE/chipset.c index 97d0cbb..dd88f75 100644 --- a/SerialICE/chipset.c +++ b/SerialICE/chipset.c @@ -123,5 +123,7 @@ static void pnp_exit_ext_func_mode_ite(u16 port) pnp_write_register(port, 0x02, 0x02); } +#include CONFIG_SOUTHBRIDGE_INIT +#include CONFIG_SUPERIO_INIT #include MAINBOARD diff --git a/SerialICE/serial.c b/SerialICE/serial.c index 9aaecb6..eee7e49 100644 --- a/SerialICE/serial.c +++ b/SerialICE/serial.c @@ -39,7 +39,17 @@ static void sio_init(void) { +#if SIO_SPEED > 115200 + /* "high speed" serial requires special chip setup + * (to be done in superio_init), and special divisor + * values (implement superio_serial_divisor() for that). + * Maybe it requires even more, but so far that seems + * to be enough. + */ + int divisor = superio_serial_divisor(SIO_SPEED); +#else int divisor = 115200 / SIO_SPEED; +#endif int lcs = 3; outb(0x00, SIO_PORT + UART_IER); outb(0x01, SIO_PORT + UART_FCR); diff --git a/SerialICE/serialice.c b/SerialICE/serialice.c index 35531dc..649ee11 100644 --- a/SerialICE/serialice.c +++ b/SerialICE/serialice.c @@ -21,13 +21,13 @@ #include <serialice.h> #include <io.h> -/* SIO functions */ -#include "serial.c" - /* Hardware specific functions */ #include "chipset.c" +/* SIO functions */ +#include "serial.c" + /* Accessor functions */ static void serialice_read_memory(void)

1 0