Re: [SerialICE] [coreboot] Which MSR disables hyperthreading (all non-BSP/AP cores)?
by Kyösti Mälkki
On Wed, 2012-02-15 at 17:33 +0100, Idwer Vollering wrote:
> Or: how to start a multicore (hyperthreading) processor as if it were
> a singlecore (non-hyperthreading) processor.
>
To my knowledge, there is no such MSR for P4 Hyper-Threaded CPUs using
the NetBurst Architecture. So SerialICE may need a patch for
hyper-threaded CPUs to enable Cache-As-Ram, like coreboot does.
You've seen my cache-as-ram code with SIPIs for model f25 (P4 Xeon on
socket 604), to enable cache on HT-enabled CPU.
>From your responses (on e-mail) so far, I cannot determine where (if) it
stops with P4 models f29 and f49 on socket 478 (?). You have actual POST
code PCI device, make wise use of it.
Thanks,
KM
6 years, 11 months
Re: [SerialICE] Which MSR disables hyperthreading (all non-BSP/AP cores)?
by Stefan Reinauer
* Idwer Vollering <vidwer(a)gmail.com> [120215 17:33]:
> Or: how to start a multicore (hyperthreading) processor as if it were
> a singlecore (non-hyperthreading) processor.
>
> Would it be necessary to configure APIC/IPI in serialice' mainboard
> specific code?
You probably need something like:
/* Send INIT IPI to all excluding ourself. */
movl $0x000C4500, %eax
movl $0xFEE00300, %esi
movl %eax, (%esi)
(Taken from cache_as_ram.inc on model_6ex)
Stefan
6 years, 11 months
Which MSR disables hyperthreading (all non-BSP/AP cores)?
by Idwer Vollering
Or: how to start a multicore (hyperthreading) processor as if it were
a singlecore (non-hyperthreading) processor.
Would it be necessary to configure APIC/IPI in serialice' mainboard
specific code?
See these message [1] [2] [3].
This is the output from two processors with hyperthreading disabled and enabled:
$ diff cpu_intel_p4_model_f29_msr_with_ht_disabled.txt
cpu_intel_p4_model_f29_msr_with_ht_enabled.txt2
41c41
< MSR 0x00000300 = 0x000000FD:0x8E129919 (MSR_BPU_COUNTER0)
---
> MSR 0x00000300 = 0x000000FC:0xEB7BD6C3 (MSR_BPU_COUNTER0)
43c43
< MSR 0x00000302 = 0x00000000:0x00000000 (MSR_BPU_COUNTER2)
---
> MSR 0x00000302 = 0x000000FB:0x75D2A276 (MSR_BPU_COUNTER2)
61c61
< MSR 0x00000362 = 0x00000000:0x00000000 (MSR_BPU_CCCR2)
---
> MSR 0x00000362 = 0x00000000:0x0803D000 (MSR_BPU_CCCR2)
80c80
< MSR 0x000003A3 = 0x00000000:0x00000000 (MSR_FSB_ESCR1)
---
> MSR 0x000003A3 = 0x00000000:0x26000203 (MSR_FSB_ESCR1)
147c147
< MSR 0x00000010 = 0x0000003A:0x8FB50494 (IA32_TIME_STAMP_COUNTER)
---
> MSR 0x00000010 = 0x00000045:0x41DA8FAC (IA32_TIME_STAMP_COUNTER)
179a180,222
> MSR 0x000001D8 = 0x00000000:0x00000000 (MSR_LER_TO_LIP)
> MSR 0x000001D9 = 0x00000000:0x00000000 (MSR_DEBUGCTLA)
> MSR 0x000001DA = 0x00000000:0x00000000 (MSR_LASTBRANCH_TOS)
> MSR 0x000001DB = 0x00000000:0x00000000 (MSR_LASTBRANCH_0)
> MSR 0x000001DD = 0x00000000:0x00000000 (MSR_LASTBRANCH_2)
> MSR 0x000001DE = 0x00000000:0x00000000 (MSR_LASTBRANCH_3)
> MSR 0x00000277 = 0x00070106:0x00070106 (IA32_PAT)
> MSR 0x00000600 = 0x00000000:0x00000000 (IA32_DS_AREA)
>
> ====================== UNIQUE MSRs (core 1) ======================
> MSR 0x00000010 = 0x00000045:0x41DE63F4 (IA32_TIME_STAMP_COUNTER)
> MSR 0x0000001B = 0x00000000:0xFEE00800 (IA32_APIC_BASE)
> MSR 0x0000008B = 0x0000002E:0x00000000 (IA32_BIOS_SIGN_ID)
> MSR 0x000000FE = 0x00000000:0x00000508 (IA32_MTRRCAP)
> MSR 0x00000174 = 0x00000000:0x00000060 (IA32_SYSENTER_CS)
> MSR 0x00000175 = 0x00000000:0xF6606FC0 (IA32_SYSENTER_ESP)
> MSR 0x00000176 = 0x00000000:0xC047C31C (IA32_SYSENTER_EIP)
> MSR 0x00000179 = 0x00000000:0x000C0204 (IA32_MCG_CAP)
> MSR 0x0000017A = 0x00000000:0x00000000 (IA32_MCG_STATUS)
> (*) MSR 0x0000017B = 0xFFFFFFFF:0xFFFFFFFF (IA32_MCG_CTL)
> MSR 0x00000180 = 0x00000000:0x00000000 (MSR_MCG_RAX)
> MSR 0x00000181 = 0x00000000:0x00000000 (MSR_MCG_RBX)
> MSR 0x00000182 = 0x00000000:0x00000000 (MSR_MCG_RCX)
> MSR 0x00000183 = 0x00000000:0x00000000 (MSR_MCG_RDX)
> MSR 0x00000184 = 0x00000000:0x00000000 (MSR_MCG_RSI)
> MSR 0x00000185 = 0x00000000:0x00000000 (MSR_MCG_RDI)
> MSR 0x00000186 = 0x00000000:0x00000000 (MSR_MCG_RBP)
> MSR 0x00000187 = 0x00000000:0x00000000 (MSR_MCG_RSP)
> MSR 0x00000188 = 0x00000000:0x00000000 (MSR_MCG_RFLAGS)
> MSR 0x00000189 = 0x00000000:0x00000000 (MSR_MCG_RIP)
> MSR 0x0000018A = 0x00000000:0x00000000 (MSR_MCG_MISC)
> (*) MSR 0x00000190 = 0xFFFFFFFF:0xFFFFFFFF (MSR_MCG_R8)
> (*) MSR 0x00000191 = 0xFFFFFFFF:0xFFFFFFFF (MSR_MCG_R9)
> (*) MSR 0x00000192 = 0xFFFFFFFF:0xFFFFFFFF (MSR_MCG_R10)
> (*) MSR 0x00000193 = 0xFFFFFFFF:0xFFFFFFFF (MSR_MCG_R11)
> (*) MSR 0x00000194 = 0xFFFFFFFF:0xFFFFFFFF (MSR_MCG_R12)
> (*) MSR 0x00000195 = 0xFFFFFFFF:0xFFFFFFFF (MSR_MCG_R13)
> (*) MSR 0x00000196 = 0xFFFFFFFF:0xFFFFFFFF (MSR_MCG_R14)
> (*) MSR 0x00000197 = 0xFFFFFFFF:0xFFFFFFFF (MSR_MCG_R15)
> MSR 0x0000019A = 0x00000000:0x00000002 (IA32_CLOCK_MODULATION)
> MSR 0x0000019B = 0x00000000:0x00000003 (IA32_THERM_INTERRUPT)
> MSR 0x000001A0 = 0x00000000:0x00000089 (IA32_MISC_ENABLE)
> MSR 0x000001D7 = 0x00000000:0xFFFFE066 (MSR_LER_FROM_LIP)
And:
$ diff cpu_intel_p4_model_f49_msr_with_ht_enabled.txt
cpu_intel_p4_model_f49_msr_with_ht_dis
abled.txt
45c45
< MSR 0x00000300 = 0x000000FC:0x2C774AC9 (MSR_BPU_COUNTER0)
---
> MSR 0x00000300 = 0x000000FC:0xF2106B69 (MSR_BPU_COUNTER0)
47c47
< MSR 0x00000302 = 0x000000FA:0xF37E6A39 (MSR_BPU_COUNTER2)
---
> MSR 0x00000302 = 0x00000000:0x00000000 (MSR_BPU_COUNTER2)
71c71
< MSR 0x00000010 = 0x0000004C:0x69A3BC78 (IA32_TIME_STAMP_COUNTER)
---
> MSR 0x00000010 = 0x0000002E:0xD3FA1647 (IA32_TIME_STAMP_COUNTER)
79,121d78
< MSR 0x00000176 = 0x00000000:0xC047C31C (IA32_SYSENTER_EIP)
< MSR 0x00000179 = 0x00000000:0x00180204 (IA32_MCG_CAP)
< MSR 0x0000017A = 0x00000000:0x00000000 (IA32_MCG_STATUS)
< MSR 0x00000180 = 0x00000000:0x00000000 (MSR_MCG_RAX)
< MSR 0x00000181 = 0x00000000:0x00000000 (MSR_MCG_RBX)
< MSR 0x00000182 = 0x00000000:0x00000000 (MSR_MCG_RCX)
< MSR 0x00000183 = 0x00000000:0x00000000 (MSR_MCG_RDX)
< MSR 0x00000184 = 0x00000000:0x00000000 (MSR_MCG_RSI)
< MSR 0x00000185 = 0x00000000:0x00000000 (MSR_MCG_RDI)
< MSR 0x00000186 = 0x00000000:0x00000000 (MSR_MCG_RBP)
< MSR 0x00000187 = 0x00000000:0x00000000 (MSR_MCG_RSP)
< MSR 0x00000188 = 0x00000000:0x00000000 (MSR_MCG_RFLAGS)
< MSR 0x00000189 = 0x00000000:0x00000000 (MSR_MCG_RIP)
< MSR 0x0000018A = 0x00000000:0x00000000 (MSR_MCG_MISC)
< MSR 0x00000190 = 0x00000000:0x00000000 (MSR_MCG_R8)
< MSR 0x00000191 = 0x00000000:0x00000000 (MSR_MCG_R9)
< MSR 0x00000192 = 0x00000000:0x00000000 (MSR_MCG_R10)
< MSR 0x00000193 = 0x00000000:0x00000000 (MSR_MCG_R11)
< MSR 0x00000194 = 0x00000000:0x00000000 (MSR_MCG_R12)
< MSR 0x00000195 = 0x00000000:0x00000000 (MSR_MCG_R13)
< MSR 0x00000196 = 0x00000000:0x00000000 (MSR_MCG_R14)
< MSR 0x00000197 = 0x00000000:0x00000000 (MSR_MCG_R15)
< MSR 0x00000198 = 0x00000F2D:0x00000F2D (IA32_PERF_STATUS)
< MSR 0x00000199 = 0x00000000:0x00000F2D (IA32_PERF_CTL)
< MSR 0x0000019A = 0x00000000:0x00000000 (IA32_CLOCK_MODULATION)
< MSR 0x0000019B = 0x00000000:0x00000003 (IA32_THERM_INTERRUPT)
< MSR 0x000001A0 = 0x00000004:0x20840489 (IA32_MISC_ENABLE)
< MSR 0x000001D7 = 0x00000000:0x00000000 (MSR_LER_FROM_LIP)
< MSR 0x000001D8 = 0x00000000:0x00000000 (MSR_LER_TO_LIP)
< MSR 0x000001D9 = 0x00000000:0x00000000 (MSR_DEBUGCTLA)
< MSR 0x000001DA = 0x00000000:0x00000000 (MSR_LASTBRANCH_TOS)
< MSR 0x00000277 = 0x00070106:0x00070106 (IA32_PAT)
< MSR 0x00000600 = 0x00000000:0x00000000 (IA32_DS_AREA)
<
< ====================== UNIQUE MSRs (core 1) ======================
< MSR 0x00000010 = 0x0000004C:0x69AE1BD2 (IA32_TIME_STAMP_COUNTER)
< MSR 0x0000001B = 0x00000000:0xFEE00800 (IA32_APIC_BASE)
< (*) MSR 0x0000003A = 0xFFFFFFFF:0xFFFFFFFF (IA32_FEATURE_CONTROL)
< MSR 0x0000008B = 0x00000003:0x00000000 (IA32_BIOS_SIGN_ID)
< (*) MSR 0x0000009B = 0xFFFFFFFF:0xFFFFFFFF (IA32_SMM_MONITOR_CTL)
< MSR 0x000000FE = 0x00000000:0x00000508 (IA32_MTRRCAP)
< MSR 0x00000174 = 0x00000000:0x00000060 (IA32_SYSENTER_CS)
< MSR 0x00000175 = 0x00000000:0xF6106FC0 (IA32_SYSENTER_ESP)
[1] http://serialice.com/pipermail/serialice/2011-December/000305.html
[2] http://serialice.com/pipermail/serialice/2009-December/000068.html
[3] http://www.serialice.com/trac/serialice/changeset/82
6 years, 11 months
