On Wed, 2012-02-15 at 17:33 +0100, Idwer Vollering wrote:
> Or: how to start a multicore (hyperthreading) processor as if it were
> a singlecore (non-hyperthreading) processor.
>
To my knowledge, there is no such MSR for P4 Hyper-Threaded CPUs using
the NetBurst Architecture. So SerialICE may need a patch for
hyper-threaded CPUs to enable Cache-As-Ram, like coreboot does.
You've seen my cache-as-ram code with SIPIs for model f25 (P4 Xeon on
socket 604), to enable cache on HT-enabled CPU.
>From your responses (on e-mail) so far, I cannot determine where (if) it
stops with P4 models f29 and f49 on socket 478 (?). You have actual POST
code PCI device, make wise use of it.
Thanks,
KM
* Idwer Vollering <vidwer(a)gmail.com> [120215 17:33]:
> Or: how to start a multicore (hyperthreading) processor as if it were
> a singlecore (non-hyperthreading) processor.
>
> Would it be necessary to configure APIC/IPI in serialice' mainboard
> specific code?
You probably need something like:
/* Send INIT IPI to all excluding ourself. */
movl $0x000C4500, %eax
movl $0xFEE00300, %esi
movl %eax, (%esi)
(Taken from cache_as_ram.inc on model_6ex)
Stefan