the following patch was just integrated into master: commit c95bfbd09fa2b2483fe8f48dc99848084207b9b3 Author: Rudolf Marek email@example.com Date: Sun Nov 25 19:55:01 2012 +0100
Add support for extended PCI config space via 0xcf8
Some chipsets allows on request an access to extended PCI config space 0 - 4096. Lets add them to the decoder. There is no generic limitation for number of busses, but this mechanism is used as the backdoor to chipset extended PCI regs.
Change-Id: Ie446104c86916f719bc0230d5e9ce2f8a49cceb1 Signed-off-by: Rudolf Marek firstname.lastname@example.org Reviewed-on: http://review.coreboot.org/1912 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki email@example.com Reviewed-by: Anton Kochkov firstname.lastname@example.org
Build-Tested: build bot (Jenkins) at Sun Nov 25 21:25:19 2012, giving +1 Reviewed-By: Anton Kochkov email@example.com at Tue Dec 4 14:03:47 2012, giving +2 See http://review.coreboot.org/1912 for details.