SerialICE November 2012

serialice@serialice.com

2 participants
41 discussions

New patch to review for serialice: e09b188 Fix display of offset
by Kyösti Mälkki 14 Nov '12

14 Nov '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1856 -gerrit commit e09b188d4f333f637b1d08ed4f1a1fc381ceb505 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Nov 14 10:27:21 2012 +0200 Fix display of offset If the size of a region was not power of two, the offset was incorrectly displayed. Change-Id: Ib8751fe1165917477f827c9032ef12ac58b1fab0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- SerialICE/simba/core_io.lua | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/SerialICE/simba/core_io.lua b/SerialICE/simba/core_io.lua index 38a2df0..b89a3e2 100644 --- a/SerialICE/simba/core_io.lua +++ b/SerialICE/simba/core_io.lua @@ -19,9 +19,9 @@ end function io_base_post(f, action) if (action.write) then - printk(f, action, "[%04x] <= %s\n", bit32.band(action.addr, (f.size - 1)), size_data(action.size, action.data)) + printk(f, action, "[%04x] <= %s\n", action.addr - f.base, size_data(action.size, action.data)) else - printk(f, action, "[%04x] => %s\n", bit32.band(action.addr, (f.size - 1)), size_data(action.size, action.data)) + printk(f, action, "[%04x] => %s\n", action.addr - f.base, size_data(action.size, action.data)) end return true end

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Patch merged into serialice/master: eb1e4cf Add mainboard ASRock 775i65G
by gerrit＠coreboot.org 14 Nov '12

14 Nov '12

the following patch was just integrated into master: commit eb1e4cfd23d647119de17a9b8e3421f98f254701 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Tue Nov 13 22:30:36 2012 +0100 Add mainboard ASRock 775i65G Add mainboard ASRock 775i65G Change-Id: Ia1177107c98fc75cc6c4bc89cdcc24ba8b1e2ae6 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> Reviewed-on: http://review.coreboot.org/1830 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Nov 14 01:41:29 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Nov 14 05:50:58 2012, giving +2 See http://review.coreboot.org/1830 for details. -gerrit

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New patch to review for serialice: 6204bc6 Add mainboard ASRock 775i65G
by Idwer Vollering 13 Nov '12

13 Nov '12

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1830 -gerrit commit 6204bc6bff8d55251003394a7c217540a76c2e6e Author: Idwer Vollering <vidwer(a)gmail.com> Date: Tue Nov 13 22:30:36 2012 +0100 Add mainboard ASRock 775i65G Add mainboard ASRock 775i65G Change-Id: Ia1177107c98fc75cc6c4bc89cdcc24ba8b1e2ae6 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- SerialICE/Kconfig | 4 +++ SerialICE/mainboard/asrock_775i65g.c | 57 ++++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig index 7199453..72e3924 100644 --- a/SerialICE/Kconfig +++ b/SerialICE/Kconfig @@ -111,6 +111,9 @@ config BOARD_VIA_EPIA_M850 config BOARD_INTEL_D845GBV2 bool "Intel D845GBV2" +config BOARD_ASROCK_775I65G + bool "ASRock 775i65G" + endchoice config BOARD_INIT @@ -140,6 +143,7 @@ config BOARD_INIT default "aopen_dxpl-plus.c" if BOARD_AOPEN_DXPL_PLUS default "via_epia_m850.c" if BOARD_VIA_EPIA_M850 default "intel_d845gbv2.c" if BOARD_INTEL_D845GBV2 + default "asrock_775i65g.c" if BOARD_ASROCK_775I65G config SOUTHBRIDGE_INIT string diff --git a/SerialICE/mainboard/asrock_775i65g.c b/SerialICE/mainboard/asrock_775i65g.c new file mode 100644 index 0000000..4d1512f --- /dev/null +++ b/SerialICE/mainboard/asrock_775i65g.c @@ -0,0 +1,57 @@ +/* + * SerialICE + * + * Copyright (C) 2012 Idwer Vollering <vidwer(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +const char boardname[33]="ASRock 775i65G "; + +#define SUPERIO_CONFIG_PORT 0x2e + +/* Hardware specific functions */ +static void mainboard_set_ich5(void) +{ + /* COM_DEC */ /* COMA at 0x3f8, COMB at 0x3f8 */ + pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0xe0), 0x0); + /* LPC_EN */ /* FDD_LPC_EN=1, KBC_LPC_EN=1, CNF1_LPC_EN=1 */ + pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0xe6), 0x1408); + /* FB_DEC_EN1 */ /* FN_F8_EN=1, decode two 512 kilobyte flash ranges */ + pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0xe3), 0x80); + /* FB_DEC_EN2 */ /* don't decode two 1 megabyte ranges */ + pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0xf0), 0x0); + /* FUNC_DIS */ /* D31_F6_DISABLE=1 (AC97 modem) */ + pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0xf2), 0x0040); +} + +/* Winbond W83627HG */ +static void superio_init(void) +{ + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + /* Set the clock to 48MHz */ + pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0xc0); + pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); + pnp_set_enable(SUPERIO_CONFIG_PORT, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); +} + +static void chipset_init(void) +{ + mainboard_set_ich5(); + superio_init(); +}

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Patch merged into serialice/master: 6ed6cc5 Add AMD SBxxx helpers
by gerrit＠coreboot.org 12 Nov '12

12 Nov '12

the following patch was just integrated into master: commit 6ed6cc5cd7a78a2687647de20b0e5ddce4a14121 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Nov 11 15:54:04 2012 +0100 Add AMD SBxxx helpers The newer AMD southbridges need a bit more complex setup for the start. Change-Id: Ieb782bdb35831568d61fd57c7c956bf4cc9747c7 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Reviewed-on: http://review.coreboot.org/1680 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Nov 12 02:31:47 2012, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Mon Nov 12 06:59:12 2012, giving +2 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Nov 12 17:34:33 2012, giving +2 See http://review.coreboot.org/1680 for details. -gerrit

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New patch to review for serialice: 0a5e0b3 Add the Asus F2A85-M
by Rudolf Marek 11 Nov '12

11 Nov '12

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1815 -gerrit commit 0a5e0b33d9ebbbe2bd5c6513cd3256a085eb1664 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Nov 11 15:57:15 2012 +0100 Add the Asus F2A85-M Add the Asus F2A85-M. Change-Id: Ia981f30e7444165570b3ebfbd4082173ef6c4205 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- SerialICE/Kconfig | 6 +++++ SerialICE/mainboard/asus_f2a85-m.c | 50 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig index 7199453..5a4c073 100644 --- a/SerialICE/Kconfig +++ b/SerialICE/Kconfig @@ -45,6 +45,10 @@ config BOARD_INTEL_D945GCLF config BOARD_DELL_S1850 bool "Dell PowerEdge S1850" +config BOARD_ASUS_F2A85_M + bool "ASUS F2A85-M" + select BUILD_XMMSTACK + config BOARD_ASUS_M2V_MX_SE bool "ASUS M2V-MX SE" select VIA_ROMSTRAP @@ -121,6 +125,7 @@ config BOARD_INIT default "roda_rk886ex.c" if BOARD_RODA_RK886EX default "intel_d945gclf.c" if BOARD_INTEL_D945GCLF default "dell_s1850.c" if BOARD_DELL_S1850 + default "asus_f2a85-m.c" if BOARD_ASUS_F2A85_M default "asus_m2v-mx_se.c" if BOARD_ASUS_M2V_MX_SE default "asus_k8v-x.c" if BOARD_ASUS_K8V_X default "msi_ms6178.c" if BOARD_MSI_MS6178 @@ -144,6 +149,7 @@ config BOARD_INIT config SOUTHBRIDGE_INIT string default "southbridge/intel-ich7.c" if BOARD_KONTRON_986LCD_M + default "southbridge/amd-sbxxx.c" if BOARD_ASUS_F2A85_M config SUPERIO_INIT string diff --git a/SerialICE/mainboard/asus_f2a85-m.c b/SerialICE/mainboard/asus_f2a85-m.c new file mode 100644 index 0000000..532421d --- /dev/null +++ b/SerialICE/mainboard/asus_f2a85-m.c @@ -0,0 +1,50 @@ +/* + * SerialICE + * + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +const char boardname[33]="Asus F2A85-M "; + +#define SUPERIO_CONFIG_PORT 0x2e + +static void superio_init(void) +{ + u8 byte; + pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + + /* Disable the watchdog. */ + pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7); + pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00); + + /* Enable the serial port. */ + pnp_set_logical_device(SUPERIO_CONFIG_PORT, 1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + + pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT); +} + + +static void chipset_init(void) +{ + southbridge_init(); + sbxxx_enable_48mhzout(); + superio_init(); +}

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Patch set updated for serialice: 7d40b28 Add config option for LPC/PCI POST card
by Rudolf Marek 11 Nov '12

11 Nov '12

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1682 -gerrit commit 7d40b2876a5c192919571f85305ff850594615c5 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Nov 11 15:59:24 2012 +0100 Add config option for LPC/PCI POST card It turns out that first works POST card than serial port. Make it a nice Kconfig option and convert #if 0 existing code to use it. Change-Id: I38af84211d686484deabcec0002d7d261993e4d6 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- SerialICE/Kconfig | 15 +++++++++++++ SerialICE/mainboard/intel_d945gclf.c | 3 ++- SerialICE/mainboard/roda_rk886ex.c | 4 +++- SerialICE/southbridge/amd-sbxxx.c | 43 +++++++++++++++++++++++++++++++++++- SerialICE/southbridge/intel-ich7.c | 4 +++- 5 files changed, 65 insertions(+), 4 deletions(-) diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig index 5a4c073..f1f3d8e 100644 --- a/SerialICE/Kconfig +++ b/SerialICE/Kconfig @@ -319,6 +319,21 @@ config EXPERIMENTAL We do not make any guarantees about anything that is marked as EXPERIMENTAL! You have been warned! +choice + prompt "POST card" + default POST_NONE + +config POST_NONE + boolean "None" + +config POST_PCI + boolean "PCI POST card" + +config POST_LPC + boolean "LPC POST card" + +endchoice + config EXPERT bool "Expert mode" help diff --git a/SerialICE/mainboard/intel_d945gclf.c b/SerialICE/mainboard/intel_d945gclf.c index c78f3bc..85d4d82 100644 --- a/SerialICE/mainboard/intel_d945gclf.c +++ b/SerialICE/mainboard/intel_d945gclf.c @@ -18,6 +18,7 @@ */ /* This is a chipset init file for the Intel D945GCLF mainboard */ +#include "config.h" const char boardname[33]="Intel D945GCLF "; @@ -35,7 +36,7 @@ static void southbridge_init(void) // Set up RCBA pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1); -#if 0 +#if defined(CONFIG_POST_LPC) // port80 writes go to LPC: reg32 = RCBA32(GCS); reg32 = reg32 & ~0x04; diff --git a/SerialICE/mainboard/roda_rk886ex.c b/SerialICE/mainboard/roda_rk886ex.c index e3e02c1..b54fd79 100644 --- a/SerialICE/mainboard/roda_rk886ex.c +++ b/SerialICE/mainboard/roda_rk886ex.c @@ -20,6 +20,8 @@ /* * This is an example chipset init file for the Roda RK886EX (Rocky 3+) */ +#include "config.h" + const char boardname[33]="Roda RK886EX (Rocky III+) "; /* Hardware specific functions */ @@ -36,7 +38,7 @@ static void southbridge_init(void) // Set up RCBA pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1); -#if 0 +#if defined(CONFIG_POST_LPC) // port80 writes go to LPC: reg32 = RCBA32(GCS); reg32 = reg32 & ~0x04; diff --git a/SerialICE/southbridge/amd-sbxxx.c b/SerialICE/southbridge/amd-sbxxx.c index 86f1278..37dca92 100644 --- a/SerialICE/southbridge/amd-sbxxx.c +++ b/SerialICE/southbridge/amd-sbxxx.c @@ -23,6 +23,8 @@ * o enables POST card (see #if 0) */ +#include "config.h" + #define MMIO_NON_POSTED_START 0xfed00000 #define MMIO_NON_POSTED_END 0xfedfffff #define SB_MMIO 0xFED80000 @@ -44,7 +46,7 @@ static void sbxxx_enable_48mhzout(void) static void southbridge_init(void) { - u16 reg16; + u8 reg8; u32 reg32; /* route FED00000 - FEDFFFFF as non-posted to SB */ @@ -65,4 +67,43 @@ static void southbridge_init(void) /* Enable LPC decoding of 0x2e/0x2f, 0x4e/0x4f 0x3f8 */ pci_write_config8(PCI_ADDR(0, 0x14, 3, 0x44), (1<<6)); pci_write_config8(PCI_ADDR(0, 0x14, 3, 0x48), (1 << 1) | (1 << 0)); + +#if defined(CONFIG_POST_PCI) + /* Chip Control: Enable subtractive decoding */ + reg8 = pci_read_config8(PCI_ADDR(0, 0x14, 4, 0x40)); + reg8 |= 1 << 5; + pci_write_config8(PCI_ADDR(0, 0x14, 4, 0x40), reg8); + + /* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */ + reg8 = pci_read_config8(PCI_ADDR(0, 0x14, 4, 0x4b)); + reg8 |= 1 << 7; + pci_write_config8(PCI_ADDR(0, 0x14, 4, 0x4b), reg8); + + /* The same IO Base and IO Limit here is meaningful because we set the + * bridge to be subtractive. During early setup stage, we have to make + * sure that data can go through port 0x80. + */ + /* IO Base: 0xf000 */ + reg8 = pci_read_config8(PCI_ADDR(0, 0x14, 4, 0x1c)); + reg8 |= 0xf << 4; + pci_write_config8(PCI_ADDR(0, 0x14, 4, 0x1c), reg8); + + /* IO Limit: 0xf000 */ + reg8 = pci_read_config8(PCI_ADDR(0, 0x14, 4, 0x1d)); + reg8 |= 0xf << 4; + pci_write_config8(PCI_ADDR(0, 0x14, 4, 0x1d), reg8); + + /* PCI Command: Enable IO response */ + reg8 = pci_read_config8(PCI_ADDR(0, 0x14, 4, 0x4)); + reg8 |= 1 << 0; + pci_write_config8(PCI_ADDR(0, 0x14, 4, 0x4) , reg8); + + reg8 = pci_read_config8(PCI_ADDR(0, 0x14, 3, 0x4a)); + reg8 &= ~(1 << 5); /* disable lpc port 80 */ + pci_write_config8(PCI_ADDR(0, 0x14, 3, 0x4a), reg8); +#elif defined(CONFIG_POST_LPC) + reg8 = pci_read_config8(PCI_ADDR(0, 0x14, 3, 0x4a)); + reg8 |= (1 << 5); /* enable lpc port 80 */ + pci_write_config8(PCI_ADDR(0, 0x14, 3, 0x4a), reg8); +#endif } diff --git a/SerialICE/southbridge/intel-ich7.c b/SerialICE/southbridge/intel-ich7.c index 3688084..c58aca1 100644 --- a/SerialICE/southbridge/intel-ich7.c +++ b/SerialICE/southbridge/intel-ich7.c @@ -23,6 +23,8 @@ * o the watchdog is turned off */ +#include "config.h" + #define RCBA 0xfed1c000 #define GCS 0x3410 #define RCBA32(x) *((volatile u32 *)(RCBA + x)) @@ -35,7 +37,7 @@ static void southbridge_init(void) // Set up RCBA pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1); -#if 0 +#if defined(CONFIG_POST_LPC) // port80 writes go to LPC: reg32 = RCBA32(GCS); reg32 = reg32 & ~0x04;

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Patch set updated for serialice: 8ae36e4 Add AMD SBxxx helpers
by Rudolf Marek 11 Nov '12

11 Nov '12

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1680 -gerrit commit 8ae36e4f59b745c1dd402f130235f1fcb3880e8f Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Nov 11 15:54:04 2012 +0100 Add AMD SBxxx helpers The newer AMD southbridges need a bit more complex setup for the start. Change-Id: Ieb782bdb35831568d61fd57c7c956bf4cc9747c7 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- SerialICE/southbridge/amd-sbxxx.c | 68 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/SerialICE/southbridge/amd-sbxxx.c b/SerialICE/southbridge/amd-sbxxx.c new file mode 100644 index 0000000..86f1278 --- /dev/null +++ b/SerialICE/southbridge/amd-sbxxx.c @@ -0,0 +1,68 @@ +/* + * SerialICE + * + * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This initializes AMD SBxx that + * o Ports 0x2e/0x2f 0x4e/0x4f and 0x3f8 are routed to superio + * o the MMIO regs of SB are accesible + * o enables POST card (see #if 0) + */ + +#define MMIO_NON_POSTED_START 0xfed00000 +#define MMIO_NON_POSTED_END 0xfedfffff +#define SB_MMIO 0xFED80000 +#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x)) + +static void sbxxx_enable_48mhzout(void) +{ + /* most likely programming to 48MHz out signal */ + u32 reg32; + reg32 = SB_MMIO_MISC32(0x28); + reg32 &= 0xffc7ffff; + reg32 |= 0x00100000; + SB_MMIO_MISC32(0x28) = reg32; + + reg32 = SB_MMIO_MISC32(0x40); + reg32 &= ~0x80u; + SB_MMIO_MISC32(0x40) = reg32; +} + +static void southbridge_init(void) +{ + u16 reg16; + u32 reg32; + + /* route FED00000 - FEDFFFFF as non-posted to SB */ + pci_write_config32(PCI_ADDR(0, 0x18, 1, 0x84), + (((MMIO_NON_POSTED_END & ~0xffffu) >> 8) | (1 << 7))); + /* lowest NP address is HPET at FED00000 */ + pci_write_config32(PCI_ADDR(0, 0x18, 1, 0x80), + (MMIO_NON_POSTED_START >> 8) | 3); + + /* Send all IO (0000-FFFF) to southbridge. */ + pci_write_config32(PCI_ADDR(0, 0x18, 1, 0xc4), 0x0000f000); + pci_write_config32(PCI_ADDR(0, 0x18, 1, 0xc0), 0x00000003); + + /* SB MMIO range decode enable */ + outb(0x24, 0xcd6); + outb(0x1, 0xcd7); + + /* Enable LPC decoding of 0x2e/0x2f, 0x4e/0x4f 0x3f8 */ + pci_write_config8(PCI_ADDR(0, 0x14, 3, 0x44), (1<<6)); + pci_write_config8(PCI_ADDR(0, 0x14, 3, 0x48), (1 << 1) | (1 << 0)); +}

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Patch merged into serialice/master: 4227d5f Add sample mainboard scripts
by gerrit＠coreboot.org 07 Nov '12

07 Nov '12

the following patch was just integrated into master: commit 4227d5fbe0e5e1e0915256d57e0370961310bcb8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 28 09:51:43 2012 +0200 Add sample mainboard scripts Scripts are written by replaying old logfiles from these platforms, they may or may not work when used live. Change-Id: I6510d9c82625eb6315cfd92d4a4b961a61e555a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/1651 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Sun Oct 28 23:14:50 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Nov 6 22:08:29 2012, giving +2 See http://review.coreboot.org/1651 for details. -gerrit

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Patch merged into serialice/master: f3d96b7 Add PCI bridge device filters
by gerrit＠coreboot.org 07 Nov '12

07 Nov '12

the following patch was just integrated into master: commit f3d96b7e7aa08d1a7ae2c08f99f060bc8b686716 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 28 10:29:10 2012 +0200 Add PCI bridge device filters Samples of decoding BARs as found on ich4, ihc7, i945 and i946 bridge devices. See board samples how to enable decoding. Change-Id: I5b602ca51ac53cd6d61abed63450293fca2192f7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/1650 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Sun Oct 28 23:03:41 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Nov 6 22:07:55 2012, giving +2 See http://review.coreboot.org/1650 for details. -gerrit

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Patch merged into serialice/master: 5a4d395 Add SMBus decoder
by gerrit＠coreboot.org 07 Nov '12

07 Nov '12

the following patch was just integrated into master: commit 5a4d39579721d84b943827224878896eac66a0ce Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 28 12:19:03 2012 +0200 Add SMBus decoder Decodes a series of IO accesses to the SMBus controller device as a series of bytes transmitted on the SMBus. Tested mostly on Intel ICH4, some VIA seemed to be compatible too. Change-Id: Id5248f4d9a2d550e8fd06d4252a67a404f719b77 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/1649 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Sun Oct 28 22:52:34 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Nov 6 22:06:05 2012, giving +2 See http://review.coreboot.org/1649 for details. -gerrit

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