r84 - in openbios-devel: arch/sparc32 config/examples

Author: stepan
Date: 2006-09-14 17:08:45 +0200 (Thu, 14 Sep 2006)
New Revision: 84

Modified:
   openbios-devel/arch/sparc32/console.c
   openbios-devel/config/examples/cross-sparc32_config.xml
   openbios-devel/config/examples/sparc32_config.xml
Log:
Blueswirl's serial patch

Modified: openbios-devel/arch/sparc32/console.c
===================================================================
--- openbios-devel/arch/sparc32/console.c	2006-09-14 15:06:38 UTC (rev 83)
+++ openbios-devel/arch/sparc32/console.c	2006-09-14 15:08:45 UTC (rev 84)
@@ -33,9 +33,17 @@

/* Write Register 3 */
 #define	RxENAB  	0x1	/* Rx Enable */
+#define	Rx8		0xc0	/* Rx 8 Bits/Character */

+/* Write Register 4 */
+#define	SB1		0x4	/* 1 stop bit/char */
+#define	X16CLK		0x40	/* x16 clock mode */
+
 /* Write Register 5 */
+#define	RTS		0x2	/* RTS */
 #define	TxENAB		0x8	/* Tx Enable */
+#define	Tx8		0x60	/* Tx 8 bits/character */
+#define	DTR		0x80	/* DTR */

/* Write Register 14 (Misc control bits) */
 #define	BRENAB 	1	/* Baud rate generator enable */
@@ -65,12 +73,10 @@

static void uart_init_line(int port, unsigned long baud)
 {
-        outb(3, CTRL(port)); // reg 3
-        outb(RxENAB, CTRL(port)); // enable rx
+        outb(4, CTRL(port)); // reg 4
+        outb(SB1 | X16CLK, CTRL(port)); // no parity, async, 1 stop
+                                        // bit, 16x clock

-        outb(5, CTRL(port)); // reg 5
-        outb(TxENAB, CTRL(port)); // enable tx
-
         baud = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);

outb(12, CTRL(port)); // reg 12
@@ -79,6 +85,15 @@
         outb((baud >> 8) & 0xff, CTRL(port));
         outb(14, CTRL(port)); // reg 14
         outb(BRSRC | BRENAB, CTRL(port));
+
+        outb(3, CTRL(port)); // reg 3
+        outb(RxENAB | Rx8, CTRL(port)); // enable rx, 8 bits/char
+
+        outb(5, CTRL(port)); // reg 5
+        outb(RTS | TxENAB | Tx8 | DTR, CTRL(port)); // enable tx, 8
+                                                    // bits/char, set
+                                                    // RTS & DTR
+
 }

int uart_init(int port, unsigned long speed)

Modified: openbios-devel/config/examples/cross-sparc32_config.xml
===================================================================
--- openbios-devel/config/examples/cross-sparc32_config.xml	2006-09-14 15:06:38 UTC (rev 83)
+++ openbios-devel/config/examples/cross-sparc32_config.xml	2006-09-14 15:08:45 UTC (rev 84)
@@ -32,7 +32,7 @@
   <option name="CONFIG_DEBUG_OBP" type="boolean" value="false"/>
   <option name="CONFIG_DEBUG_IOMMU" type="boolean" value="false"/>
   <option name="CONFIG_SERIAL_PORT" type="integer" value="0"/>
-  <option name="CONFIG_SERIAL_SPEED" type="integer" value="115200"/>
+  <option name="CONFIG_SERIAL_SPEED" type="integer" value="9600"/>

<!-- Module Configuration -->

Modified: openbios-devel/config/examples/sparc32_config.xml
===================================================================
--- openbios-devel/config/examples/sparc32_config.xml	2006-09-14 15:06:38 UTC (rev 83)
+++ openbios-devel/config/examples/sparc32_config.xml	2006-09-14 15:08:45 UTC (rev 84)
@@ -32,7 +32,7 @@
   <option name="CONFIG_DEBUG_OBP" type="boolean" value="false"/>
   <option name="CONFIG_DEBUG_IOMMU" type="boolean" value="false"/>
   <option name="CONFIG_SERIAL_PORT" type="integer" value="0"/>
-  <option name="CONFIG_SERIAL_SPEED" type="integer" value="115200"/>
+  <option name="CONFIG_SERIAL_SPEED" type="integer" value="9600"/>

<!-- Module Configuration -->