Unlike the 604 core, the 603 doesn't perform table search in HW. When a TLB Miss occurs, the 603 generates one of three specific TLB Miss exception: - Instruction TLB Miss - Data read TLB Miss - Data store TLB Miss
The associated exception handlers have to search the match page table entry and load it in a TLB entry.
This patch implements the exemple provided in the reference manual (with a couple of errors corrected).
Signed-off-by: Christophe Leroy christophe.leroy@csgroup.eu Cc: Fabiano Rosas farosas@linux.ibm.com Cc: Cédric Le Goater clg@kaod.org Cc: Mark Cave-Ayland mark.cave-ayland@ilande.co.uk --- arch/ppc/qemu/start.S | 158 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 155 insertions(+), 3 deletions(-)
diff --git a/arch/ppc/qemu/start.S b/arch/ppc/qemu/start.S index c679230..3d4102d 100644 --- a/arch/ppc/qemu/start.S +++ b/arch/ppc/qemu/start.S @@ -25,6 +25,14 @@ #define ILLEGAL_VECTOR( v ) .org __vectors + v ; vector__##v: bl trap_error ; #define VECTOR( v, dummystr ) .org __vectors + v ; vector__##v
+#define SPR_DMISS 976 +#define SPR_DCMP 977 +#define SPR_HASH1 978 +#define SPR_HASH2 979 +#define SPR_IMISS 980 +#define SPR_ICMP 981 +#define SPR_RPA 982 + #ifdef CONFIG_PPC_64BITSUPPORT
/* We're trying to use the same code for the ppc32 and ppc64 handlers here. @@ -329,9 +337,153 @@ ILLEGAL_VECTOR( 0xd00 ) ILLEGAL_VECTOR( 0xe00 ) ILLEGAL_VECTOR( 0xf00 ) ILLEGAL_VECTOR( 0xf20 ) -ILLEGAL_VECTOR( 0x1000 ) -ILLEGAL_VECTOR( 0x1100 ) -ILLEGAL_VECTOR( 0x1200 ) + +VECTOR( 0x1000, "IFTLB" ): + mfspr r2, SPR_HASH1 + li r1, 8 + mfctr r0 + mfspr r3, SPR_ICMP + addi r2, r2, -8 +0: mtctr r1 +1: lwzu r1, 8(r2) + cmp cr0, r1, r3 + bdnzf eq, 1b + bne 2f + lwz r1, 4(r2) + andi. r3, r1, 8 + bne 3f + mtctr r0 + mfspr r0, SPR_IMISS + mfsrr1 r3 + mtcrf 0x80, r3 + mtspr SPR_RPA, r1 + ori r1, r1, 0x100 + srwi r1, r1, 8 + tlbli r0 + stb r1, 6(r2) + rfi +2: + andi. r1, r3, 0x0040 + bne 4f + mfspr r2, SPR_HASH2 + ori r3, r3, 0x0040 + addi r1, 0, 8 + addi r2, r2, -8 + b 0b +3: + mfsrr1 r3 + andi. r2,r3,0xffff + addis r2, r2, 0x0800 + b 5f +4: + mfsrr1 r3 + andi. r2,r3,0xffff + addis r2, r2, 0x4000 +5: mtctr r0 + mtsrr1 r2 + mfmsr r0 + xoris r0, r0, 0x02 + mtcrf 0x80, r3 + mtmsr r0 + b real_isi + +VECTOR( 0x1100, "DLTLB" ): + mfspr r2, SPR_HASH1 + addi r1, 0, 8 + mfctr r0 + mfspr r3, SPR_DCMP + addi r2, r2, -8 +0: mtctr r1 +1: lwzu r1, 8(r2) + cmp cr0, r1, r3 + bdnzf eq, 1b + bne 2f + lwz r1, +4(r2) + mtctr r0 + mfspr r0, SPR_DMISS + mfsrr1 r3 + mtcrf 0x80, r3 + mtspr SPR_RPA, r1 + ori r1, r1, 0x100 + srw r1, r1, 8 + tlbld r0 + stb r1, +6(r2) + rfi +2: + andi. r1, r3, 0x0040 + bne 7f + mfspr r2, SPR_HASH2 + ori r3, r3, 0x0040 + addi r1, 0, 8 + addi r2, r2, -8 + b 0b + +VECTOR( 0x1200, "DSTLB" ): + mfspr r2, SPR_HASH1 + addi r1, 0, 8 + mfctr r0 + mfspr r3, SPR_DCMP + addi r2, r2, -8 +0: mtctr r1 +1: lwzu r1, 8(r2) + cmp cr0, r1, r3 + bdnzf eq, 1b + bne 3f + lwz r1, +4(r2) + andi. r3,r1,0x80 + beq 4f +2: mtctr r0 + mfspr r0, SPR_DMISS + mfsrr1 r3 + mtcrf 0x80, r3 + mtspr SPR_RPA, r1 + tlbld r0 + rfi +3: + andi. r1, r3, 0x0040 + bne 7f + mfspr r2, SPR_HASH2 + ori r3, r3, 0x0040 + addi r1, 0, 8 + addi r2, r2, -8 + b 0b +4: + rlwinm. r3,r1,30,0,1 + bge- 5f + andi. r3,r1,1 + beq+ 6f + b 8f +5: mfsrr1 r3 + andis. r3,r3,0x0008 + beq 6f + b 8f +6: ori r1, r1, 0x180 + sth r1, 6(r2) + b 2b +7: + mfsrr1 r3 + rlwinm r1, r3, 9,6,6 + addis r1, r1, 0x4000 + b 9f +8: + mfsrr1 r3 + rlwinm r1, r3, 9,6,6 + addis r1, r1, 0x0800 +9: mtctr r0 + andi. r2, r3, 0xffff + mtsrr1 r2 + mtdsisr r1 + mfspr r1, SPR_DMISS + rlwinm. r2,r2,0,31,31 + beq 10f + xor r1,r1,0x07 +10: mtdar r1 + mfmsr r0 + xoris r0, r0, 0x02 + mtcrf 0x80, r3 + mtmsr r0 + b real_dsi + ILLEGAL_VECTOR( 0x1300 ) ILLEGAL_VECTOR( 0x1400 ) ILLEGAL_VECTOR( 0x1500 )
On 1/28/22 07:20, Christophe Leroy wrote:
Unlike the 604 core, the 603 doesn't perform table search in HW. When a TLB Miss occurs, the 603 generates one of three specific TLB Miss exception:
- Instruction TLB Miss
- Data read TLB Miss
- Data store TLB Miss
The associated exception handlers have to search the match page table entry and load it in a TLB entry.
This patch implements the exemple provided in the reference manual (with a couple of errors corrected).
It is running under QEMU now ? what else do we need ?
Thanks,
C.
Signed-off-by: Christophe Leroy christophe.leroy@csgroup.eu Cc: Fabiano Rosas farosas@linux.ibm.com Cc: Cédric Le Goater clg@kaod.org Cc: Mark Cave-Ayland mark.cave-ayland@ilande.co.uk
arch/ppc/qemu/start.S | 158 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 155 insertions(+), 3 deletions(-)
diff --git a/arch/ppc/qemu/start.S b/arch/ppc/qemu/start.S index c679230..3d4102d 100644 --- a/arch/ppc/qemu/start.S +++ b/arch/ppc/qemu/start.S @@ -25,6 +25,14 @@ #define ILLEGAL_VECTOR( v ) .org __vectors + v ; vector__##v: bl trap_error ; #define VECTOR( v, dummystr ) .org __vectors + v ; vector__##v
+#define SPR_DMISS 976 +#define SPR_DCMP 977 +#define SPR_HASH1 978 +#define SPR_HASH2 979 +#define SPR_IMISS 980 +#define SPR_ICMP 981 +#define SPR_RPA 982
#ifdef CONFIG_PPC_64BITSUPPORT
/* We're trying to use the same code for the ppc32 and ppc64 handlers here.
@@ -329,9 +337,153 @@ ILLEGAL_VECTOR( 0xd00 ) ILLEGAL_VECTOR( 0xe00 ) ILLEGAL_VECTOR( 0xf00 ) ILLEGAL_VECTOR( 0xf20 ) -ILLEGAL_VECTOR( 0x1000 ) -ILLEGAL_VECTOR( 0x1100 ) -ILLEGAL_VECTOR( 0x1200 )
+VECTOR( 0x1000, "IFTLB" ):
- mfspr r2, SPR_HASH1
- li r1, 8
- mfctr r0
- mfspr r3, SPR_ICMP
- addi r2, r2, -8
+0: mtctr r1 +1: lwzu r1, 8(r2)
- cmp cr0, r1, r3
- bdnzf eq, 1b
- bne 2f
- lwz r1, 4(r2)
- andi. r3, r1, 8
- bne 3f
- mtctr r0
- mfspr r0, SPR_IMISS
- mfsrr1 r3
- mtcrf 0x80, r3
- mtspr SPR_RPA, r1
- ori r1, r1, 0x100
- srwi r1, r1, 8
- tlbli r0
- stb r1, 6(r2)
- rfi
+2:
- andi. r1, r3, 0x0040
- bne 4f
- mfspr r2, SPR_HASH2
- ori r3, r3, 0x0040
- addi r1, 0, 8
- addi r2, r2, -8
- b 0b
+3:
- mfsrr1 r3
- andi. r2,r3,0xffff
- addis r2, r2, 0x0800
- b 5f
+4:
- mfsrr1 r3
- andi. r2,r3,0xffff
- addis r2, r2, 0x4000
+5: mtctr r0
- mtsrr1 r2
- mfmsr r0
- xoris r0, r0, 0x02
- mtcrf 0x80, r3
- mtmsr r0
- b real_isi
+VECTOR( 0x1100, "DLTLB" ):
- mfspr r2, SPR_HASH1
- addi r1, 0, 8
- mfctr r0
- mfspr r3, SPR_DCMP
- addi r2, r2, -8
+0: mtctr r1 +1: lwzu r1, 8(r2)
- cmp cr0, r1, r3
- bdnzf eq, 1b
- bne 2f
- lwz r1, +4(r2)
- mtctr r0
- mfspr r0, SPR_DMISS
- mfsrr1 r3
- mtcrf 0x80, r3
- mtspr SPR_RPA, r1
- ori r1, r1, 0x100
- srw r1, r1, 8
- tlbld r0
- stb r1, +6(r2)
- rfi
+2:
- andi. r1, r3, 0x0040
- bne 7f
- mfspr r2, SPR_HASH2
- ori r3, r3, 0x0040
- addi r1, 0, 8
- addi r2, r2, -8
- b 0b
+VECTOR( 0x1200, "DSTLB" ):
- mfspr r2, SPR_HASH1
- addi r1, 0, 8
- mfctr r0
- mfspr r3, SPR_DCMP
- addi r2, r2, -8
+0: mtctr r1 +1: lwzu r1, 8(r2)
- cmp cr0, r1, r3
- bdnzf eq, 1b
- bne 3f
- lwz r1, +4(r2)
- andi. r3,r1,0x80
- beq 4f
+2: mtctr r0
- mfspr r0, SPR_DMISS
- mfsrr1 r3
- mtcrf 0x80, r3
- mtspr SPR_RPA, r1
- tlbld r0
- rfi
+3:
- andi. r1, r3, 0x0040
- bne 7f
- mfspr r2, SPR_HASH2
- ori r3, r3, 0x0040
- addi r1, 0, 8
- addi r2, r2, -8
- b 0b
+4:
- rlwinm. r3,r1,30,0,1
- bge- 5f
- andi. r3,r1,1
- beq+ 6f
- b 8f
+5: mfsrr1 r3
- andis. r3,r3,0x0008
- beq 6f
- b 8f
+6: ori r1, r1, 0x180
- sth r1, 6(r2)
- b 2b
+7:
- mfsrr1 r3
- rlwinm r1, r3, 9,6,6
- addis r1, r1, 0x4000
- b 9f
+8:
- mfsrr1 r3
- rlwinm r1, r3, 9,6,6
- addis r1, r1, 0x0800
+9: mtctr r0
- andi. r2, r3, 0xffff
- mtsrr1 r2
- mtdsisr r1
- mfspr r1, SPR_DMISS
- rlwinm. r2,r2,0,31,31
- beq 10f
- xor r1,r1,0x07
+10: mtdar r1
- mfmsr r0
- xoris r0, r0, 0x02
- mtcrf 0x80, r3
- mtmsr r0
- b real_dsi
- ILLEGAL_VECTOR( 0x1300 ) ILLEGAL_VECTOR( 0x1400 ) ILLEGAL_VECTOR( 0x1500 )
Le 28/01/2022 à 09:07, Cédric Le Goater a écrit :
On 1/28/22 07:20, Christophe Leroy wrote:
Unlike the 604 core, the 603 doesn't perform table search in HW. When a TLB Miss occurs, the 603 generates one of three specific TLB Miss exception:
- Instruction TLB Miss
- Data read TLB Miss
- Data store TLB Miss
The associated exception handlers have to search the match page table entry and load it in a TLB entry.
This patch implements the exemple provided in the reference manual (with a couple of errors corrected).
It is running under QEMU now ? what else do we need ?
Address translation now works properly.
I'm still facing some blocking, it enters enterforth() again and again then ends up at a wrong address.
Breakpoint 5, enterforth (xt=0xfff5ce54) at /home/chleroy/openbios/kernel/forth.c:137 137 if (read_ucell(_cfa) != DOCOL) { => 0xfff0c9cc <enterforth+0>: 81 23 00 00 lwz r9,0(r3) 0xfff0c9d0 <enterforth+4>: 7c 08 02 a6 mflr r0 0xfff0c9d4 <enterforth+8>: 94 21 ff b0 stwu r1,-80(r1) 0xfff0c9d8 <enterforth+12>: 2c 09 00 01 cmpwi r9,1 0xfff0c9dc <enterforth+16>: be 01 00 10 stmw r16,16(r1) 0xfff0c9e0 <enterforth+20>: 7c 7f 1b 78 mr r31,r3 0xfff0c9e4 <enterforth+24>: 90 01 00 54 stw r0,84(r1) 0xfff0c9e8 <enterforth+28>: 41 82 00 14 beq 0xfff0c9fc <enterforth+48> (gdb) Continuing.
Breakpoint 5, enterforth (xt=0xfff51e08) at /home/chleroy/openbios/kernel/forth.c:137 137 if (read_ucell(_cfa) != DOCOL) { => 0xfff0c9cc <enterforth+0>: 81 23 00 00 lwz r9,0(r3) 0xfff0c9d0 <enterforth+4>: 7c 08 02 a6 mflr r0 0xfff0c9d4 <enterforth+8>: 94 21 ff b0 stwu r1,-80(r1) 0xfff0c9d8 <enterforth+12>: 2c 09 00 01 cmpwi r9,1 0xfff0c9dc <enterforth+16>: be 01 00 10 stmw r16,16(r1) 0xfff0c9e0 <enterforth+20>: 7c 7f 1b 78 mr r31,r3 0xfff0c9e4 <enterforth+24>: 90 01 00 54 stw r0,84(r1) 0xfff0c9e8 <enterforth+28>: 41 82 00 14 beq 0xfff0c9fc <enterforth+48> (gdb) Continuing.
Breakpoint 5, enterforth (xt=0xfff5ce54) at /home/chleroy/openbios/kernel/forth.c:137 137 if (read_ucell(_cfa) != DOCOL) { => 0xfff0c9cc <enterforth+0>: 81 23 00 00 lwz r9,0(r3) 0xfff0c9d0 <enterforth+4>: 7c 08 02 a6 mflr r0 0xfff0c9d4 <enterforth+8>: 94 21 ff b0 stwu r1,-80(r1) 0xfff0c9d8 <enterforth+12>: 2c 09 00 01 cmpwi r9,1 0xfff0c9dc <enterforth+16>: be 01 00 10 stmw r16,16(r1) 0xfff0c9e0 <enterforth+20>: 7c 7f 1b 78 mr r31,r3 0xfff0c9e4 <enterforth+24>: 90 01 00 54 stw r0,84(r1) 0xfff0c9e8 <enterforth+28>: 41 82 00 14 beq 0xfff0c9fc <enterforth+48> (gdb) Continuing.
Program received signal SIGTRAP, Trace/breakpoint trap. 0x00120000 in ?? () => 0x00120000: 00 00 00 00 .long 0x0 (gdb)
Christophe Leroy christophe.leroy@csgroup.eu writes:
Unlike the 604 core, the 603 doesn't perform table search in HW. When a TLB Miss occurs, the 603 generates one of three specific TLB Miss exception:
- Instruction TLB Miss
- Data read TLB Miss
- Data store TLB Miss
The associated exception handlers have to search the match page table entry and load it in a TLB entry.
This patch implements the exemple provided in the reference manual (with a couple of errors corrected).
Signed-off-by: Christophe Leroy christophe.leroy@csgroup.eu Cc: Fabiano Rosas farosas@linux.ibm.com Cc: Cédric Le Goater clg@kaod.org Cc: Mark Cave-Ayland mark.cave-ayland@ilande.co.uk
arch/ppc/qemu/start.S | 158 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 155 insertions(+), 3 deletions(-)
diff --git a/arch/ppc/qemu/start.S b/arch/ppc/qemu/start.S index c679230..3d4102d 100644 --- a/arch/ppc/qemu/start.S +++ b/arch/ppc/qemu/start.S @@ -25,6 +25,14 @@ #define ILLEGAL_VECTOR( v ) .org __vectors + v ; vector__##v: bl trap_error ; #define VECTOR( v, dummystr ) .org __vectors + v ; vector__##v
+#define SPR_DMISS 976 +#define SPR_DCMP 977 +#define SPR_HASH1 978 +#define SPR_HASH2 979 +#define SPR_IMISS 980 +#define SPR_ICMP 981 +#define SPR_RPA 982
#ifdef CONFIG_PPC_64BITSUPPORT
/* We're trying to use the same code for the ppc32 and ppc64 handlers here. @@ -329,9 +337,153 @@ ILLEGAL_VECTOR( 0xd00 ) ILLEGAL_VECTOR( 0xe00 ) ILLEGAL_VECTOR( 0xf00 ) ILLEGAL_VECTOR( 0xf20 ) -ILLEGAL_VECTOR( 0x1000 ) -ILLEGAL_VECTOR( 0x1100 ) -ILLEGAL_VECTOR( 0x1200 )
+VECTOR( 0x1000, "IFTLB" ):
Won't these vectors clobber r0-r3? You might need an EXCEPTION_PREAMBLE here and use exception_return instead of rfi. At least I did in the 7450 patch:
https://lists.nongnu.org/archive/html/qemu-ppc/2021-11/msg00288.html
- mfspr r2, SPR_HASH1
- li r1, 8
- mfctr r0
- mfspr r3, SPR_ICMP
- addi r2, r2, -8
+0: mtctr r1 +1: lwzu r1, 8(r2)
- cmp cr0, r1, r3
- bdnzf eq, 1b
- bne 2f
- lwz r1, 4(r2)
- andi. r3, r1, 8
- bne 3f
- mtctr r0
- mfspr r0, SPR_IMISS
- mfsrr1 r3
- mtcrf 0x80, r3
- mtspr SPR_RPA, r1
- ori r1, r1, 0x100
- srwi r1, r1, 8
- tlbli r0
- stb r1, 6(r2)
- rfi
+2:
- andi. r1, r3, 0x0040
- bne 4f
- mfspr r2, SPR_HASH2
- ori r3, r3, 0x0040
- addi r1, 0, 8
- addi r2, r2, -8
- b 0b
+3:
- mfsrr1 r3
- andi. r2,r3,0xffff
- addis r2, r2, 0x0800
- b 5f
+4:
- mfsrr1 r3
- andi. r2,r3,0xffff
- addis r2, r2, 0x4000
+5: mtctr r0
- mtsrr1 r2
- mfmsr r0
- xoris r0, r0, 0x02
- mtcrf 0x80, r3
- mtmsr r0
- b real_isi
+VECTOR( 0x1100, "DLTLB" ):
- mfspr r2, SPR_HASH1
- addi r1, 0, 8
- mfctr r0
- mfspr r3, SPR_DCMP
- addi r2, r2, -8
+0: mtctr r1 +1: lwzu r1, 8(r2)
- cmp cr0, r1, r3
- bdnzf eq, 1b
- bne 2f
- lwz r1, +4(r2)
- mtctr r0
- mfspr r0, SPR_DMISS
- mfsrr1 r3
- mtcrf 0x80, r3
- mtspr SPR_RPA, r1
- ori r1, r1, 0x100
- srw r1, r1, 8
- tlbld r0
- stb r1, +6(r2)
- rfi
+2:
- andi. r1, r3, 0x0040
- bne 7f
- mfspr r2, SPR_HASH2
- ori r3, r3, 0x0040
- addi r1, 0, 8
- addi r2, r2, -8
- b 0b
+VECTOR( 0x1200, "DSTLB" ):
- mfspr r2, SPR_HASH1
- addi r1, 0, 8
- mfctr r0
- mfspr r3, SPR_DCMP
- addi r2, r2, -8
+0: mtctr r1 +1: lwzu r1, 8(r2)
- cmp cr0, r1, r3
- bdnzf eq, 1b
- bne 3f
- lwz r1, +4(r2)
- andi. r3,r1,0x80
- beq 4f
+2: mtctr r0
- mfspr r0, SPR_DMISS
- mfsrr1 r3
- mtcrf 0x80, r3
- mtspr SPR_RPA, r1
- tlbld r0
- rfi
+3:
- andi. r1, r3, 0x0040
- bne 7f
- mfspr r2, SPR_HASH2
- ori r3, r3, 0x0040
- addi r1, 0, 8
- addi r2, r2, -8
- b 0b
+4:
- rlwinm. r3,r1,30,0,1
- bge- 5f
- andi. r3,r1,1
- beq+ 6f
- b 8f
+5: mfsrr1 r3
- andis. r3,r3,0x0008
- beq 6f
- b 8f
+6: ori r1, r1, 0x180
- sth r1, 6(r2)
- b 2b
+7:
- mfsrr1 r3
- rlwinm r1, r3, 9,6,6
- addis r1, r1, 0x4000
- b 9f
+8:
- mfsrr1 r3
- rlwinm r1, r3, 9,6,6
- addis r1, r1, 0x0800
+9: mtctr r0
- andi. r2, r3, 0xffff
- mtsrr1 r2
- mtdsisr r1
- mfspr r1, SPR_DMISS
- rlwinm. r2,r2,0,31,31
- beq 10f
- xor r1,r1,0x07
+10: mtdar r1
- mfmsr r0
- xoris r0, r0, 0x02
- mtcrf 0x80, r3
- mtmsr r0
- b real_dsi
ILLEGAL_VECTOR( 0x1300 ) ILLEGAL_VECTOR( 0x1400 ) ILLEGAL_VECTOR( 0x1500 )
Le 28/01/2022 à 13:14, Fabiano Rosas a écrit :
Christophe Leroy christophe.leroy@csgroup.eu writes:
Unlike the 604 core, the 603 doesn't perform table search in HW. When a TLB Miss occurs, the 603 generates one of three specific TLB Miss exception:
- Instruction TLB Miss
- Data read TLB Miss
- Data store TLB Miss
The associated exception handlers have to search the match page table entry and load it in a TLB entry.
This patch implements the exemple provided in the reference manual (with a couple of errors corrected).
Signed-off-by: Christophe Leroy christophe.leroy@csgroup.eu Cc: Fabiano Rosas farosas@linux.ibm.com Cc: Cédric Le Goater clg@kaod.org Cc: Mark Cave-Ayland mark.cave-ayland@ilande.co.uk
arch/ppc/qemu/start.S | 158 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 155 insertions(+), 3 deletions(-)
diff --git a/arch/ppc/qemu/start.S b/arch/ppc/qemu/start.S index c679230..3d4102d 100644 --- a/arch/ppc/qemu/start.S +++ b/arch/ppc/qemu/start.S @@ -25,6 +25,14 @@ #define ILLEGAL_VECTOR( v ) .org __vectors + v ; vector__##v: bl trap_error ; #define VECTOR( v, dummystr ) .org __vectors + v ; vector__##v
+#define SPR_DMISS 976 +#define SPR_DCMP 977 +#define SPR_HASH1 978 +#define SPR_HASH2 979 +#define SPR_IMISS 980 +#define SPR_ICMP 981 +#define SPR_RPA 982
#ifdef CONFIG_PPC_64BITSUPPORT
/* We're trying to use the same code for the ppc32 and ppc64 handlers here.
@@ -329,9 +337,153 @@ ILLEGAL_VECTOR( 0xd00 ) ILLEGAL_VECTOR( 0xe00 ) ILLEGAL_VECTOR( 0xf00 ) ILLEGAL_VECTOR( 0xf20 ) -ILLEGAL_VECTOR( 0x1000 ) -ILLEGAL_VECTOR( 0x1100 ) -ILLEGAL_VECTOR( 0x1200 )
+VECTOR( 0x1000, "IFTLB" ):
Won't these vectors clobber r0-r3? You might need an EXCEPTION_PREAMBLE here and use exception_return instead of rfi. At least I did in the 7450 patch:
No they don't clobber r0-r3 on the 603, that's one of the features of the 603 MMU hardware assist.
Extract from reference manual (https://www.nxp.com/docs/en/reference-manual/MPC603EUM.pdf)
Shadow registers for GPR0–GPR3 that allow miss code to execute without corrupting the state of any of the existing GPRs. Shadow registers are used only for servicing a TLB miss.
Christophe
Christophe Leroy christophe.leroy@csgroup.eu writes:
Le 28/01/2022 à 13:14, Fabiano Rosas a écrit :
Christophe Leroy christophe.leroy@csgroup.eu writes:
Unlike the 604 core, the 603 doesn't perform table search in HW. When a TLB Miss occurs, the 603 generates one of three specific TLB Miss exception:
- Instruction TLB Miss
- Data read TLB Miss
- Data store TLB Miss
The associated exception handlers have to search the match page table entry and load it in a TLB entry.
This patch implements the exemple provided in the reference manual (with a couple of errors corrected).
Signed-off-by: Christophe Leroy christophe.leroy@csgroup.eu Cc: Fabiano Rosas farosas@linux.ibm.com Cc: Cédric Le Goater clg@kaod.org Cc: Mark Cave-Ayland mark.cave-ayland@ilande.co.uk
arch/ppc/qemu/start.S | 158 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 155 insertions(+), 3 deletions(-)
diff --git a/arch/ppc/qemu/start.S b/arch/ppc/qemu/start.S index c679230..3d4102d 100644 --- a/arch/ppc/qemu/start.S +++ b/arch/ppc/qemu/start.S @@ -25,6 +25,14 @@ #define ILLEGAL_VECTOR( v ) .org __vectors + v ; vector__##v: bl trap_error ; #define VECTOR( v, dummystr ) .org __vectors + v ; vector__##v
+#define SPR_DMISS 976 +#define SPR_DCMP 977 +#define SPR_HASH1 978 +#define SPR_HASH2 979 +#define SPR_IMISS 980 +#define SPR_ICMP 981 +#define SPR_RPA 982
#ifdef CONFIG_PPC_64BITSUPPORT
/* We're trying to use the same code for the ppc32 and ppc64 handlers here.
@@ -329,9 +337,153 @@ ILLEGAL_VECTOR( 0xd00 ) ILLEGAL_VECTOR( 0xe00 ) ILLEGAL_VECTOR( 0xf00 ) ILLEGAL_VECTOR( 0xf20 ) -ILLEGAL_VECTOR( 0x1000 ) -ILLEGAL_VECTOR( 0x1100 ) -ILLEGAL_VECTOR( 0x1200 )
+VECTOR( 0x1000, "IFTLB" ):
Won't these vectors clobber r0-r3? You might need an EXCEPTION_PREAMBLE here and use exception_return instead of rfi. At least I did in the 7450 patch:
No they don't clobber r0-r3 on the 603, that's one of the features of the 603 MMU hardware assist.
Extract from reference manual (https://www.nxp.com/docs/en/reference-manual/MPC603EUM.pdf)
Shadow registers for GPR0–GPR3 that allow miss code to execute without corrupting the state of any of the existing GPRs. Shadow registers are used only for servicing a TLB miss.
Ah, that's interesting! The feature in QEMU is POWERPC_FLAG_TGPR. It swaps the registers before dispatching the interrupt and during mtmsr.
In that case:
Reviewed-by: Fabiano Rosas farosas@linux.ibm.com
Le 28/01/2022 à 15:14, Fabiano Rosas a écrit :
Christophe Leroy christophe.leroy@csgroup.eu writes:
Le 28/01/2022 à 13:14, Fabiano Rosas a écrit :
Christophe Leroy christophe.leroy@csgroup.eu writes:
Unlike the 604 core, the 603 doesn't perform table search in HW. When a TLB Miss occurs, the 603 generates one of three specific TLB Miss exception:
- Instruction TLB Miss
- Data read TLB Miss
- Data store TLB Miss
The associated exception handlers have to search the match page table entry and load it in a TLB entry.
This patch implements the exemple provided in the reference manual (with a couple of errors corrected).
Signed-off-by: Christophe Leroy christophe.leroy@csgroup.eu Cc: Fabiano Rosas farosas@linux.ibm.com Cc: Cédric Le Goater clg@kaod.org Cc: Mark Cave-Ayland mark.cave-ayland@ilande.co.uk
arch/ppc/qemu/start.S | 158 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 155 insertions(+), 3 deletions(-)
diff --git a/arch/ppc/qemu/start.S b/arch/ppc/qemu/start.S index c679230..3d4102d 100644 --- a/arch/ppc/qemu/start.S +++ b/arch/ppc/qemu/start.S @@ -25,6 +25,14 @@ #define ILLEGAL_VECTOR( v ) .org __vectors + v ; vector__##v: bl trap_error ; #define VECTOR( v, dummystr ) .org __vectors + v ; vector__##v
+#define SPR_DMISS 976 +#define SPR_DCMP 977 +#define SPR_HASH1 978 +#define SPR_HASH2 979 +#define SPR_IMISS 980 +#define SPR_ICMP 981 +#define SPR_RPA 982
#ifdef CONFIG_PPC_64BITSUPPORT
/* We're trying to use the same code for the ppc32 and ppc64 handlers here.
@@ -329,9 +337,153 @@ ILLEGAL_VECTOR( 0xd00 ) ILLEGAL_VECTOR( 0xe00 ) ILLEGAL_VECTOR( 0xf00 ) ILLEGAL_VECTOR( 0xf20 ) -ILLEGAL_VECTOR( 0x1000 ) -ILLEGAL_VECTOR( 0x1100 ) -ILLEGAL_VECTOR( 0x1200 )
+VECTOR( 0x1000, "IFTLB" ):
Won't these vectors clobber r0-r3? You might need an EXCEPTION_PREAMBLE here and use exception_return instead of rfi. At least I did in the 7450 patch:
No they don't clobber r0-r3 on the 603, that's one of the features of the 603 MMU hardware assist.
Extract from reference manual (https://www.nxp.com/docs/en/reference-manual/MPC603EUM.pdf)
Shadow registers for GPR0–GPR3 that allow miss code to execute without corrupting the state of any of the existing GPRs. Shadow registers are used only for servicing a TLB miss.
Ah, that's interesting! The feature in QEMU is POWERPC_FLAG_TGPR. It swaps the registers before dispatching the interrupt and during mtmsr.
Yes and it's buggy in QEMU, see https://lore.kernel.org/qemu-devel/20220120103824.239573-1-christophe.leroy@...
In that case:
Reviewed-by: Fabiano Rosas farosas@linux.ibm.com
Thanks
Christophe
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Christophe Leroy -
Cédric Le Goater -
Fabiano Rosas