L2 cache

[Ronald G Minnich]

In case I did not mention it: we aren't turning on L2 cache. 

We need to figure this one out. All hints gratefully accepted ...

ron

-
To unsubscribe: send mail to majordomo(a)freiburg.linux.de
with 'unsubscribe openbios' in the body of the message

Ronald G Minnich <rminnich(a)lanl.gov> wrote:
  In case I did not mention it: we aren't turning on
L2 cache. 
 We need to figure this one out. All hints gratefully accepted ...
Bear in mind that L2 cache can be off-CPU. In the case of my
devel system, I have a VIA VP3 with 1mb of L2 cache on the
motherboard. Enabling this requires flipping a bit in PCI space.
This will be documented in the register-level docs for the chipset.

Other systems (Celeron, P2/P3[xeon]/p4?, K6-2/3, Athlon] have
their caches onboard and require MSR poking. This should be in
the BIOS writers guides for the respective CPUs.


regards,
-- 
Dave.
-
To unsubscribe: send mail to majordomo(a)freiburg.linux.de
with 'unsubscribe openbios' in the body of the message

[Ronald G Minnich]

On 3 Jul 2000, Dave Jones wrote:

  Other systems (Celeron, P2/P3[xeon]/p4?, K6-2/3,
Athlon] have
 their caches onboard and require MSR poking. This should be in
 the BIOS writers guides for the respective CPUs.
we're just trying to find that darn bit. Any hints :-)

ron

-
To unsubscribe: send mail to majordomo(a)freiburg.linux.de
with 'unsubscribe openbios' in the body of the message

Ronald G Minnich <rminnich(a)lanl.gov> wrote:

  Other systems
(Celeron, P2/P3[xeon]/p4?, K6-2/3, Athlon] have
 their caches onboard and require MSR poking. This should be in
 the BIOS writers guides for the respective CPUs.
 we're just trying to find
that darn bit. Any hints :-)
It's not just a case of setting one bit. You have to set up a whole
bunch of other stuff, latencies, ranges, frequencies etc.
I'll dig some more, I've got example code somewhere.

-- 
Dave.
-
To unsubscribe: send mail to majordomo(a)freiburg.linux.de
with 'unsubscribe openbios' in the body of the message