[PATCH 0/3] sparc64 cleanups v1

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Bug report

Igor V. Kovalenko

25 May 2010 25 May '10

12:12 p.m.

One code cleanup and another pci host bridge remap change, the latter requires qemu update with patch already posted to qemu list.

v0->v1: added missing patch moving asi.h to arch includes

---

Igor V. Kovalenko (3): sparc64: move asi.h to arch includes sparc64: replace ASI numbers with macros sparc64: fix pci host bridge offsets

arch/sparc64/asi.h | 145 -------------------------------------------- arch/sparc64/entry.S | 2 - arch/sparc64/openbios.c | 12 ++-- arch/sparc64/spitfire.h | 2 - arch/sparc64/switch.S | 2 - arch/sparc64/vectors.S | 2 - include/arch/sparc64/asi.h | 145 ++++++++++++++++++++++++++++++++++++++++++++ include/arch/sparc64/io.h | 61 ++++++++++++------- 8 files changed, 196 insertions(+), 175 deletions(-) delete mode 100644 arch/sparc64/asi.h create mode 100644 include/arch/sparc64/asi.h

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Igor V. Kovalenko

25 May 25 May

12:12 p.m.

New subject: [PATCH 1/3] sparc64: move asi.h to arch includes

From: Igor V. Kovalenko igor.v.kovalenko@gmail.com

Signed-off-by: Igor V. Kovalenko igor.v.kovalenko@gmail.com --- arch/sparc64/asi.h | 145 -------------------------------------------- arch/sparc64/entry.S | 2 - arch/sparc64/spitfire.h | 2 - arch/sparc64/switch.S | 2 - arch/sparc64/vectors.S | 2 - include/arch/sparc64/asi.h | 145 ++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 149 insertions(+), 149 deletions(-) delete mode 100644 arch/sparc64/asi.h create mode 100644 include/arch/sparc64/asi.h

diff --git a/arch/sparc64/asi.h b/arch/sparc64/asi.h deleted file mode 100644 index 5348556..0000000 --- a/arch/sparc64/asi.h +++ /dev/null @@ -1,145 +0,0 @@ -/* $Id: asi.h,v 1.5 2001/03/29 11:47:47 davem Exp $ */ -#ifndef _SPARC64_ASI_H -#define _SPARC64_ASI_H - -/* asi.h: Address Space Identifier values for the V9. - * - * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) - */ - -/* V9 Architecture mandary ASIs. */ -#define ASI_N 0x04 /* Nucleus */ -#define ASI_NL 0x0c /* Nucleus, little endian */ -#define ASI_AIUP 0x10 /* Primary, user */ -#define ASI_AIUS 0x11 /* Secondary, user */ -#define ASI_AIUPL 0x18 /* Primary, user, little endian */ -#define ASI_AIUSL 0x19 /* Secondary, user, little endian */ -#define ASI_P 0x80 /* Primary, implicit */ -#define ASI_S 0x81 /* Secondary, implicit */ -#define ASI_PNF 0x82 /* Primary, no fault */ -#define ASI_SNF 0x83 /* Secondary, no fault */ -#define ASI_PL 0x88 /* Primary, implicit, l-endian */ -#define ASI_SL 0x89 /* Secondary, implicit, l-endian */ -#define ASI_PNFL 0x8a /* Primary, no fault, l-endian */ -#define ASI_SNFL 0x8b /* Secondary, no fault, l-endian */ - -/* SpitFire and later extended ASIs. The "(III)" marker designates - * UltraSparc-III and later specific ASIs. The "(CMT)" marker designates - * Chip Multi Threading specific ASIs. - */ -#define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cachable */ -#define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */ -#define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cachable, little endian*/ -#define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */ -#define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cachable, qword load */ -#define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cachable, qword load, l-endian */ -#define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */ -#define ASI_PCACHE_DATA 0x31 /* (III) PCache data RAM diag */ -#define ASI_PCACHE_TAG 0x32 /* (III) PCache tag RAM diag */ -#define ASI_PCACHE_SNOOP_TAG 0x33 /* (III) PCache snoop tag RAM diag */ -#define ASI_QUAD_LDD_PHYS 0x34 /* (III+) PADDR, qword load */ -#define ASI_WCACHE_VALID_BITS 0x38 /* (III) WCache Valid Bits diag */ -#define ASI_WCACHE_DATA 0x39 /* (III) WCache data RAM diag */ -#define ASI_WCACHE_TAG 0x3a /* (III) WCache tag RAM diag */ -#define ASI_WCACHE_SNOOP_TAG 0x3b /* (III) WCache snoop tag RAM diag */ -#define ASI_QUAD_LDD_PHYS_L 0x3c /* (III+) PADDR, qw-load, l-endian */ -#define ASI_SRAM_FAST_INIT 0x40 /* (III+) Fast SRAM init */ -#define ASI_CORE_AVAILABLE 0x41 /* (CMT) LP Available */ -#define ASI_CORE_ENABLE_STAT 0x41 /* (CMT) LP Enable Status */ -#define ASI_CORE_ENABLE 0x41 /* (CMT) LP Enable RW */ -#define ASI_XIR_STEERING 0x41 /* (CMT) XIR Steering RW */ -#define ASI_CORE_RUNNING_RW 0x41 /* (CMT) LP Running RW */ -#define ASI_CORE_RUNNING_W1S 0x41 /* (CMT) LP Running Write-One Set */ -#define ASI_CORE_RUNNING_W1C 0x41 /* (CMT) LP Running Write-One Clr */ -#define ASI_CORE_RUNNING_STAT 0x41 /* (CMT) LP Running Status */ -#define ASI_CMT_ERROR_STEERING 0x41 /* (CMT) Error Steering RW */ -#define ASI_DCACHE_INVALIDATE 0x42 /* (III) DCache Invalidate diag */ -#define ASI_DCACHE_UTAG 0x43 /* (III) DCache uTag diag */ -#define ASI_DCACHE_SNOOP_TAG 0x44 /* (III) DCache snoop tag RAM diag */ -#define ASI_LSU_CONTROL 0x45 /* Load-store control unit */ -#define ASI_DCU_CONTROL_REG 0x45 /* (III) DCache Unit Control reg */ -#define ASI_DCACHE_DATA 0x46 /* DCache data-ram diag access */ -#define ASI_DCACHE_TAG 0x47 /* Dcache tag/valid ram diag access*/ -#define ASI_INTR_DISPATCH_STAT 0x48 /* IRQ vector dispatch status */ -#define ASI_INTR_RECEIVE 0x49 /* IRQ vector receive status */ -#define ASI_UPA_CONFIG 0x4a /* UPA config space */ -#define ASI_JBUS_CONFIG 0x4a /* (IIIi) JBUS Config Register */ -#define ASI_SAFARI_CONFIG 0x4a /* (III) Safari Config Register */ -#define ASI_SAFARI_ADDRESS 0x4a /* (III) Safari Address Register */ -#define ASI_ESTATE_ERROR_EN 0x4b /* E-cache error enable space */ -#define ASI_AFSR 0x4c /* Async fault status register */ -#define ASI_AFAR 0x4d /* Async fault address register */ -#define ASI_EC_TAG_DATA 0x4e /* E-cache tag/valid ram diag acc */ -#define ASI_IMMU 0x50 /* Insn-MMU main register space */ -#define ASI_IMMU_TSB_8KB_PTR 0x51 /* Insn-MMU 8KB TSB pointer reg */ -#define ASI_IMMU_TSB_64KB_PTR 0x52 /* Insn-MMU 64KB TSB pointer reg */ -#define ASI_ITLB_DATA_IN 0x54 /* Insn-MMU TLB data in reg */ -#define ASI_ITLB_DATA_ACCESS 0x55 /* Insn-MMU TLB data access reg */ -#define ASI_ITLB_TAG_READ 0x56 /* Insn-MMU TLB tag read reg */ -#define ASI_IMMU_DEMAP 0x57 /* Insn-MMU TLB demap */ -#define ASI_DMMU 0x58 /* Data-MMU main register space */ -#define ASI_DMMU_TSB_8KB_PTR 0x59 /* Data-MMU 8KB TSB pointer reg */ -#define ASI_DMMU_TSB_64KB_PTR 0x5a /* Data-MMU 16KB TSB pointer reg */ -#define ASI_DMMU_TSB_DIRECT_PTR 0x5b /* Data-MMU TSB direct pointer reg */ -#define ASI_DTLB_DATA_IN 0x5c /* Data-MMU TLB data in reg */ -#define ASI_DTLB_DATA_ACCESS 0x5d /* Data-MMU TLB data access reg */ -#define ASI_DTLB_TAG_READ 0x5e /* Data-MMU TLB tag read reg */ -#define ASI_DMMU_DEMAP 0x5f /* Data-MMU TLB demap */ -#define ASI_IIU_INST_TRAP 0x60 /* (III) Instruction Breakpoint */ -#define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */ -#define ASI_CORE_ID 0x63 /* (CMT) LP ID register */ -#define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */ -#define ASI_IC_INSTR 0x66 /* Insn cache instrucion ram diag */ -#define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */ -#define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */ -#define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */ -#define ASI_IC_NEXT_FIELD 0x6f /* Insn cache next-field ram diag */ -#define ASI_BRPRED_ARRAY 0x6f /* (III) Branch Prediction RAM diag*/ -#define ASI_BLK_AIUP 0x70 /* Primary, user, block load/store */ -#define ASI_BLK_AIUS 0x71 /* Secondary, user, block ld/st */ -#define ASI_MCU_CTRL_REG 0x72 /* (III) Memory controller regs */ -#define ASI_EC_DATA 0x74 /* (III) E-cache data staging reg */ -#define ASI_EC_CTRL 0x75 /* (III) E-cache control reg */ -#define ASI_EC_W 0x76 /* E-cache diag write access */ -#define ASI_UDB_ERROR_W 0x77 /* External UDB error regs W */ -#define ASI_UDB_CONTROL_W 0x77 /* External UDB control regs W */ -#define ASI_INTR_W 0x77 /* IRQ vector dispatch write */ -#define ASI_INTR_DATAN_W 0x77 /* (III) Out irq vector data reg N */ -#define ASI_INTR_DISPATCH_W 0x77 /* (III) Interrupt vector dispatch */ -#define ASI_BLK_AIUPL 0x78 /* Primary, user, little, blk ld/st*/ -#define ASI_BLK_AIUSL 0x79 /* Secondary, user, little, blk ld/st*/ -#define ASI_EC_R 0x7e /* E-cache diag read access */ -#define ASI_UDBH_ERROR_R 0x7f /* External UDB error regs rd hi */ -#define ASI_UDBL_ERROR_R 0x7f /* External UDB error regs rd low */ -#define ASI_UDBH_CONTROL_R 0x7f /* External UDB control regs rd hi */ -#define ASI_UDBL_CONTROL_R 0x7f /* External UDB control regs rd low*/ -#define ASI_INTR_R 0x7f /* IRQ vector dispatch read */ -#define ASI_INTR_DATAN_R 0x7f /* (III) In irq vector data reg N */ -#define ASI_PST8_P 0xc0 /* Primary, 8 8-bit, partial */ -#define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */ -#define ASI_PST16_P 0xc2 /* Primary, 4 16-bit, partial */ -#define ASI_PST16_S 0xc3 /* Secondary, 4 16-bit, partial */ -#define ASI_PST32_P 0xc4 /* Primary, 2 32-bit, partial */ -#define ASI_PST32_S 0xc5 /* Secondary, 2 32-bit, partial */ -#define ASI_PST8_PL 0xc8 /* Primary, 8 8-bit, partial, L */ -#define ASI_PST8_SL 0xc9 /* Secondary, 8 8-bit, partial, L */ -#define ASI_PST16_PL 0xca /* Primary, 4 16-bit, partial, L */ -#define ASI_PST16_SL 0xcb /* Secondary, 4 16-bit, partial, L */ -#define ASI_PST32_PL 0xcc /* Primary, 2 32-bit, partial, L */ -#define ASI_PST32_SL 0xcd /* Secondary, 2 32-bit, partial, L */ -#define ASI_FL8_P 0xd0 /* Primary, 1 8-bit, fpu ld/st */ -#define ASI_FL8_S 0xd1 /* Secondary, 1 8-bit, fpu ld/st */ -#define ASI_FL16_P 0xd2 /* Primary, 1 16-bit, fpu ld/st */ -#define ASI_FL16_S 0xd3 /* Secondary, 1 16-bit, fpu ld/st */ -#define ASI_FL8_PL 0xd8 /* Primary, 1 8-bit, fpu ld/st, L */ -#define ASI_FL8_SL 0xd9 /* Secondary, 1 8-bit, fpu ld/st, L*/ -#define ASI_FL16_PL 0xda /* Primary, 1 16-bit, fpu ld/st, L */ -#define ASI_FL16_SL 0xdb /* Secondary, 1 16-bit, fpu ld/st,L*/ -#define ASI_BLK_COMMIT_P 0xe0 /* Primary, blk store commit */ -#define ASI_BLK_COMMIT_S 0xe1 /* Secondary, blk store commit */ -#define ASI_BLK_P 0xf0 /* Primary, blk ld/st */ -#define ASI_BLK_S 0xf1 /* Secondary, blk ld/st */ -#define ASI_BLK_PL 0xf8 /* Primary, blk ld/st, little */ -#define ASI_BLK_SL 0xf9 /* Secondary, blk ld/st, little */ - -#endif /* _SPARC64_ASI_H */ diff --git a/arch/sparc64/entry.S b/arch/sparc64/entry.S index 82c588d..33632b1 100644 --- a/arch/sparc64/entry.S +++ b/arch/sparc64/entry.S @@ -8,7 +8,7 @@ */

#define __ASSEMBLY__ -#include "asi.h" +#include <asm/asi.h> #include "pstate.h" #include "lsu.h" #define NO_QEMU_PROTOS diff --git a/arch/sparc64/spitfire.h b/arch/sparc64/spitfire.h index 6a2f87a..4a951b1 100644 --- a/arch/sparc64/spitfire.h +++ b/arch/sparc64/spitfire.h @@ -7,7 +7,7 @@ #ifndef _SPARC64_SPITFIRE_H #define _SPARC64_SPITFIRE_H

-#include "asi.h" +#include <asm/asi.h>

/* The following register addresses are accessible via ASI_DMMU * and ASI_IMMU, that is there is a distinct and unique copy of diff --git a/arch/sparc64/switch.S b/arch/sparc64/switch.S index e0d2df7..d2cc7be 100644 --- a/arch/sparc64/switch.S +++ b/arch/sparc64/switch.S @@ -1,5 +1,5 @@ #include "pstate.h" -#include "asi.h" +#include <asm/asi.h> #define ASI_BP ASI_M_BYPASS #define REGWIN_SZ 0x40

diff --git a/arch/sparc64/vectors.S b/arch/sparc64/vectors.S index 6b3d5be..529afbe 100644 --- a/arch/sparc64/vectors.S +++ b/arch/sparc64/vectors.S @@ -25,7 +25,7 @@

#define __ASSEMBLY__ #include "pstate.h" -#include "asi.h" +#include <asm/asi.h> #define ASI_BP ASI_PHYS_BYPASS_EC_E #define PROM_ADDR 0x1fff0000000 #define SER_ADDR 0x1fe020003f8 diff --git a/include/arch/sparc64/asi.h b/include/arch/sparc64/asi.h new file mode 100644 index 0000000..5348556 --- /dev/null +++ b/include/arch/sparc64/asi.h @@ -0,0 +1,145 @@ +/* $Id: asi.h,v 1.5 2001/03/29 11:47:47 davem Exp $ */ +#ifndef _SPARC64_ASI_H +#define _SPARC64_ASI_H + +/* asi.h: Address Space Identifier values for the V9. + * + * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) + */ + +/* V9 Architecture mandary ASIs. */ +#define ASI_N 0x04 /* Nucleus */ +#define ASI_NL 0x0c /* Nucleus, little endian */ +#define ASI_AIUP 0x10 /* Primary, user */ +#define ASI_AIUS 0x11 /* Secondary, user */ +#define ASI_AIUPL 0x18 /* Primary, user, little endian */ +#define ASI_AIUSL 0x19 /* Secondary, user, little endian */ +#define ASI_P 0x80 /* Primary, implicit */ +#define ASI_S 0x81 /* Secondary, implicit */ +#define ASI_PNF 0x82 /* Primary, no fault */ +#define ASI_SNF 0x83 /* Secondary, no fault */ +#define ASI_PL 0x88 /* Primary, implicit, l-endian */ +#define ASI_SL 0x89 /* Secondary, implicit, l-endian */ +#define ASI_PNFL 0x8a /* Primary, no fault, l-endian */ +#define ASI_SNFL 0x8b /* Secondary, no fault, l-endian */ + +/* SpitFire and later extended ASIs. The "(III)" marker designates + * UltraSparc-III and later specific ASIs. The "(CMT)" marker designates + * Chip Multi Threading specific ASIs. + */ +#define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cachable */ +#define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */ +#define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cachable, little endian*/ +#define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */ +#define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cachable, qword load */ +#define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cachable, qword load, l-endian */ +#define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */ +#define ASI_PCACHE_DATA 0x31 /* (III) PCache data RAM diag */ +#define ASI_PCACHE_TAG 0x32 /* (III) PCache tag RAM diag */ +#define ASI_PCACHE_SNOOP_TAG 0x33 /* (III) PCache snoop tag RAM diag */ +#define ASI_QUAD_LDD_PHYS 0x34 /* (III+) PADDR, qword load */ +#define ASI_WCACHE_VALID_BITS 0x38 /* (III) WCache Valid Bits diag */ +#define ASI_WCACHE_DATA 0x39 /* (III) WCache data RAM diag */ +#define ASI_WCACHE_TAG 0x3a /* (III) WCache tag RAM diag */ +#define ASI_WCACHE_SNOOP_TAG 0x3b /* (III) WCache snoop tag RAM diag */ +#define ASI_QUAD_LDD_PHYS_L 0x3c /* (III+) PADDR, qw-load, l-endian */ +#define ASI_SRAM_FAST_INIT 0x40 /* (III+) Fast SRAM init */ +#define ASI_CORE_AVAILABLE 0x41 /* (CMT) LP Available */ +#define ASI_CORE_ENABLE_STAT 0x41 /* (CMT) LP Enable Status */ +#define ASI_CORE_ENABLE 0x41 /* (CMT) LP Enable RW */ +#define ASI_XIR_STEERING 0x41 /* (CMT) XIR Steering RW */ +#define ASI_CORE_RUNNING_RW 0x41 /* (CMT) LP Running RW */ +#define ASI_CORE_RUNNING_W1S 0x41 /* (CMT) LP Running Write-One Set */ +#define ASI_CORE_RUNNING_W1C 0x41 /* (CMT) LP Running Write-One Clr */ +#define ASI_CORE_RUNNING_STAT 0x41 /* (CMT) LP Running Status */ +#define ASI_CMT_ERROR_STEERING 0x41 /* (CMT) Error Steering RW */ +#define ASI_DCACHE_INVALIDATE 0x42 /* (III) DCache Invalidate diag */ +#define ASI_DCACHE_UTAG 0x43 /* (III) DCache uTag diag */ +#define ASI_DCACHE_SNOOP_TAG 0x44 /* (III) DCache snoop tag RAM diag */ +#define ASI_LSU_CONTROL 0x45 /* Load-store control unit */ +#define ASI_DCU_CONTROL_REG 0x45 /* (III) DCache Unit Control reg */ +#define ASI_DCACHE_DATA 0x46 /* DCache data-ram diag access */ +#define ASI_DCACHE_TAG 0x47 /* Dcache tag/valid ram diag access*/ +#define ASI_INTR_DISPATCH_STAT 0x48 /* IRQ vector dispatch status */ +#define ASI_INTR_RECEIVE 0x49 /* IRQ vector receive status */ +#define ASI_UPA_CONFIG 0x4a /* UPA config space */ +#define ASI_JBUS_CONFIG 0x4a /* (IIIi) JBUS Config Register */ +#define ASI_SAFARI_CONFIG 0x4a /* (III) Safari Config Register */ +#define ASI_SAFARI_ADDRESS 0x4a /* (III) Safari Address Register */ +#define ASI_ESTATE_ERROR_EN 0x4b /* E-cache error enable space */ +#define ASI_AFSR 0x4c /* Async fault status register */ +#define ASI_AFAR 0x4d /* Async fault address register */ +#define ASI_EC_TAG_DATA 0x4e /* E-cache tag/valid ram diag acc */ +#define ASI_IMMU 0x50 /* Insn-MMU main register space */ +#define ASI_IMMU_TSB_8KB_PTR 0x51 /* Insn-MMU 8KB TSB pointer reg */ +#define ASI_IMMU_TSB_64KB_PTR 0x52 /* Insn-MMU 64KB TSB pointer reg */ +#define ASI_ITLB_DATA_IN 0x54 /* Insn-MMU TLB data in reg */ +#define ASI_ITLB_DATA_ACCESS 0x55 /* Insn-MMU TLB data access reg */ +#define ASI_ITLB_TAG_READ 0x56 /* Insn-MMU TLB tag read reg */ +#define ASI_IMMU_DEMAP 0x57 /* Insn-MMU TLB demap */ +#define ASI_DMMU 0x58 /* Data-MMU main register space */ +#define ASI_DMMU_TSB_8KB_PTR 0x59 /* Data-MMU 8KB TSB pointer reg */ +#define ASI_DMMU_TSB_64KB_PTR 0x5a /* Data-MMU 16KB TSB pointer reg */ +#define ASI_DMMU_TSB_DIRECT_PTR 0x5b /* Data-MMU TSB direct pointer reg */ +#define ASI_DTLB_DATA_IN 0x5c /* Data-MMU TLB data in reg */ +#define ASI_DTLB_DATA_ACCESS 0x5d /* Data-MMU TLB data access reg */ +#define ASI_DTLB_TAG_READ 0x5e /* Data-MMU TLB tag read reg */ +#define ASI_DMMU_DEMAP 0x5f /* Data-MMU TLB demap */ +#define ASI_IIU_INST_TRAP 0x60 /* (III) Instruction Breakpoint */ +#define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */ +#define ASI_CORE_ID 0x63 /* (CMT) LP ID register */ +#define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */ +#define ASI_IC_INSTR 0x66 /* Insn cache instrucion ram diag */ +#define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */ +#define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */ +#define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */ +#define ASI_IC_NEXT_FIELD 0x6f /* Insn cache next-field ram diag */ +#define ASI_BRPRED_ARRAY 0x6f /* (III) Branch Prediction RAM diag*/ +#define ASI_BLK_AIUP 0x70 /* Primary, user, block load/store */ +#define ASI_BLK_AIUS 0x71 /* Secondary, user, block ld/st */ +#define ASI_MCU_CTRL_REG 0x72 /* (III) Memory controller regs */ +#define ASI_EC_DATA 0x74 /* (III) E-cache data staging reg */ +#define ASI_EC_CTRL 0x75 /* (III) E-cache control reg */ +#define ASI_EC_W 0x76 /* E-cache diag write access */ +#define ASI_UDB_ERROR_W 0x77 /* External UDB error regs W */ +#define ASI_UDB_CONTROL_W 0x77 /* External UDB control regs W */ +#define ASI_INTR_W 0x77 /* IRQ vector dispatch write */ +#define ASI_INTR_DATAN_W 0x77 /* (III) Out irq vector data reg N */ +#define ASI_INTR_DISPATCH_W 0x77 /* (III) Interrupt vector dispatch */ +#define ASI_BLK_AIUPL 0x78 /* Primary, user, little, blk ld/st*/ +#define ASI_BLK_AIUSL 0x79 /* Secondary, user, little, blk ld/st*/ +#define ASI_EC_R 0x7e /* E-cache diag read access */ +#define ASI_UDBH_ERROR_R 0x7f /* External UDB error regs rd hi */ +#define ASI_UDBL_ERROR_R 0x7f /* External UDB error regs rd low */ +#define ASI_UDBH_CONTROL_R 0x7f /* External UDB control regs rd hi */ +#define ASI_UDBL_CONTROL_R 0x7f /* External UDB control regs rd low*/ +#define ASI_INTR_R 0x7f /* IRQ vector dispatch read */ +#define ASI_INTR_DATAN_R 0x7f /* (III) In irq vector data reg N */ +#define ASI_PST8_P 0xc0 /* Primary, 8 8-bit, partial */ +#define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */ +#define ASI_PST16_P 0xc2 /* Primary, 4 16-bit, partial */ +#define ASI_PST16_S 0xc3 /* Secondary, 4 16-bit, partial */ +#define ASI_PST32_P 0xc4 /* Primary, 2 32-bit, partial */ +#define ASI_PST32_S 0xc5 /* Secondary, 2 32-bit, partial */ +#define ASI_PST8_PL 0xc8 /* Primary, 8 8-bit, partial, L */ +#define ASI_PST8_SL 0xc9 /* Secondary, 8 8-bit, partial, L */ +#define ASI_PST16_PL 0xca /* Primary, 4 16-bit, partial, L */ +#define ASI_PST16_SL 0xcb /* Secondary, 4 16-bit, partial, L */ +#define ASI_PST32_PL 0xcc /* Primary, 2 32-bit, partial, L */ +#define ASI_PST32_SL 0xcd /* Secondary, 2 32-bit, partial, L */ +#define ASI_FL8_P 0xd0 /* Primary, 1 8-bit, fpu ld/st */ +#define ASI_FL8_S 0xd1 /* Secondary, 1 8-bit, fpu ld/st */ +#define ASI_FL16_P 0xd2 /* Primary, 1 16-bit, fpu ld/st */ +#define ASI_FL16_S 0xd3 /* Secondary, 1 16-bit, fpu ld/st */ +#define ASI_FL8_PL 0xd8 /* Primary, 1 8-bit, fpu ld/st, L */ +#define ASI_FL8_SL 0xd9 /* Secondary, 1 8-bit, fpu ld/st, L*/ +#define ASI_FL16_PL 0xda /* Primary, 1 16-bit, fpu ld/st, L */ +#define ASI_FL16_SL 0xdb /* Secondary, 1 16-bit, fpu ld/st,L*/ +#define ASI_BLK_COMMIT_P 0xe0 /* Primary, blk store commit */ +#define ASI_BLK_COMMIT_S 0xe1 /* Secondary, blk store commit */ +#define ASI_BLK_P 0xf0 /* Primary, blk ld/st */ +#define ASI_BLK_S 0xf1 /* Secondary, blk ld/st */ +#define ASI_BLK_PL 0xf8 /* Primary, blk ld/st, little */ +#define ASI_BLK_SL 0xf9 /* Secondary, blk ld/st, little */ + +#endif /* _SPARC64_ASI_H */

Igor V. Kovalenko

12:12 p.m.

New subject: [PATCH 2/3] sparc64: replace ASI numbers with macros

From: Igor V. Kovalenko igor.v.kovalenko@gmail.com

Signed-off-by: Igor V. Kovalenko igor.v.kovalenko@gmail.com --- include/arch/sparc64/io.h | 61 ++++++++++++++++++++++++++++++--------------- 1 files changed, 41 insertions(+), 20 deletions(-)

diff --git a/include/arch/sparc64/io.h b/include/arch/sparc64/io.h index d6280fe..f9088c3 100644 --- a/include/arch/sparc64/io.h +++ b/include/arch/sparc64/io.h @@ -2,6 +2,7 @@ #define _ASM_IO_H

#include "asm/types.h" +#include "asi.h"

#define NO_QEMU_PROTOS #include "arch/common/fw_cfg.h" @@ -62,24 +63,30 @@ static inline int in_8(volatile unsigned char *addr) { int ret;

- __asm__ __volatile__("lduba [%1] 0x15, %0\n\t" - :"=r"(ret):"r"(addr):"memory"); + __asm__ __volatile__("lduba [%1] %2, %0\n\t" + : "=r"(ret) + : "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E) + : "memory");

return ret; }

static inline void out_8(volatile unsigned char *addr, int val) { - __asm__ __volatile__("stba %0, [%1] 0x15\n\t" - : : "r"(val), "r"(addr):"memory"); + __asm__ __volatile__("stba %0, [%1] %2\n\t" + : + : "r"(val), "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E) + : "memory"); }

static inline int in_le16(volatile unsigned short *addr) { int ret;

- __asm__ __volatile__("lduha [%1] 0x15, %0\n\t" - :"=r"(ret):"r"(addr):"memory"); + __asm__ __volatile__("lduha [%1] %2, %0\n\t" + : "=r"(ret) + : "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E) + : "memory");

return ret; } @@ -88,8 +95,10 @@ static inline int in_be16(volatile unsigned short *addr) { int ret;

- __asm__ __volatile__("lduha [%1] 0x1d, %0\n\t" - :"=r"(ret):"r"(addr):"memory"); + __asm__ __volatile__("lduha [%1] %2, %0\n\t" + : "=r"(ret) + : "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E_L) + : "memory");

return ret; } @@ -97,22 +106,28 @@ static inline int in_be16(volatile unsigned short *addr) static inline void out_le16(volatile unsigned short *addr, int val) {

- __asm__ __volatile__("stha %0, [%1] 0x15\n\t" - : : "r"(val), "r"(addr):"memory"); + __asm__ __volatile__("stha %0, [%1] %2\n\t" + : + : "r"(val), "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E) + : "memory"); }

static inline void out_be16(volatile unsigned short *addr, int val) { - __asm__ __volatile__("stha %0, [%1] 0x1d\n\t" - : : "r"(val), "r"(addr):"memory"); + __asm__ __volatile__("stha %0, [%1] %2\n\t" + : + : "r"(val), "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E_L) + : "memory"); }

static inline unsigned in_le32(volatile unsigned *addr) { unsigned ret;

- __asm__ __volatile__("lduwa [%1] 0x15, %0\n\t" - :"=r"(ret):"r"(addr):"memory"); + __asm__ __volatile__("lduwa [%1] %2, %0\n\t" + : "=r"(ret) + : "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E) + : "memory");

return ret; } @@ -121,21 +136,27 @@ static inline unsigned in_be32(volatile unsigned *addr) { unsigned ret;

- __asm__ __volatile__("lduwa [%1] 0x1d, %0\n\t" - :"=r"(ret):"r"(addr):"memory"); + __asm__ __volatile__("lduwa [%1] %2, %0\n\t" + : "=r"(ret) + : "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E_L) + : "memory"); return ret; }

static inline void out_le32(volatile unsigned *addr, int val) { - __asm__ __volatile__("stwa %0, [%1] 0x15\n\t" - : : "r"(val), "r"(addr):"memory"); + __asm__ __volatile__("stwa %0, [%1] %2\n\t" + : + : "r"(val), "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E) + : "memory"); }

static inline void out_be32(volatile unsigned *addr, int val) { - __asm__ __volatile__("stwa %0, [%1] 0x1d\n\t" - : : "r"(val), "r"(addr):"memory"); + __asm__ __volatile__("stwa %0, [%1] %2\n\t" + : + : "r"(val), "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E_L) + : "memory"); }

static inline void _insw_ns(volatile uint16_t * port, void *buf, int ns)

Blue Swirl

7:28 p.m.

New subject: [PATCH 2/3] sparc64: replace ASI numbers with macros

On Tue, May 25, 2010 at 12:12 PM, Igor V. Kovalenko igor.v.kovalenko@gmail.com wrote:

...

From: Igor V. Kovalenko igor.v.kovalenko@gmail.com

Signed-off-by: Igor V. Kovalenko igor.v.kovalenko@gmail.com

include/arch/sparc64/io.h | 61 ++++++++++++++++++++++++++++++--------------- 1 files changed, 41 insertions(+), 20 deletions(-)

diff --git a/include/arch/sparc64/io.h b/include/arch/sparc64/io.h index d6280fe..f9088c3 100644 --- a/include/arch/sparc64/io.h +++ b/include/arch/sparc64/io.h @@ -2,6 +2,7 @@ #define _ASM_IO_H

#include "asm/types.h" +#include "asi.h"

Shouldn't this be <asm/asi.h> after 1/3?

Nice cleanup otherwise.

...

#define NO_QEMU_PROTOS #include "arch/common/fw_cfg.h" @@ -62,24 +63,30 @@ static inline int in_8(volatile unsigned char *addr) { int ret;

__asm__ __volatile__("lduba [%1] 0x15, %0\n\t"

:"=r"(ret):"r"(addr):"memory");

__asm__ __volatile__("lduba [%1] %2, %0\n\t"

: "=r"(ret)

: "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E)

: "memory");

return ret; }

static inline void out_8(volatile unsigned char *addr, int val) {

__asm__ __volatile__("stba %0, [%1] 0x15\n\t"

: : "r"(val), "r"(addr):"memory");

__asm__ __volatile__("stba %0, [%1] %2\n\t"

:

: "r"(val), "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E)

: "memory");

}

static inline int in_le16(volatile unsigned short *addr) { int ret;

__asm__ __volatile__("lduha [%1] 0x15, %0\n\t"

:"=r"(ret):"r"(addr):"memory");

__asm__ __volatile__("lduha [%1] %2, %0\n\t"

: "=r"(ret)

: "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E)

: "memory");

return ret; } @@ -88,8 +95,10 @@ static inline int in_be16(volatile unsigned short *addr) { int ret;

__asm__ __volatile__("lduha [%1] 0x1d, %0\n\t"

:"=r"(ret):"r"(addr):"memory");

__asm__ __volatile__("lduha [%1] %2, %0\n\t"

: "=r"(ret)

: "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E_L)

: "memory");

return ret; } @@ -97,22 +106,28 @@ static inline int in_be16(volatile unsigned short *addr) static inline void out_le16(volatile unsigned short *addr, int val) {

__asm__ __volatile__("stha %0, [%1] 0x15\n\t"

: : "r"(val), "r"(addr):"memory");

__asm__ __volatile__("stha %0, [%1] %2\n\t"

:

: "r"(val), "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E)

: "memory");

}

static inline void out_be16(volatile unsigned short *addr, int val) {

__asm__ __volatile__("stha %0, [%1] 0x1d\n\t"

: : "r"(val), "r"(addr):"memory");

__asm__ __volatile__("stha %0, [%1] %2\n\t"

:

: "r"(val), "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E_L)

: "memory");

}

static inline unsigned in_le32(volatile unsigned *addr) { unsigned ret;

__asm__ __volatile__("lduwa [%1] 0x15, %0\n\t"

:"=r"(ret):"r"(addr):"memory");

__asm__ __volatile__("lduwa [%1] %2, %0\n\t"

: "=r"(ret)

: "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E)

: "memory");

return ret; } @@ -121,21 +136,27 @@ static inline unsigned in_be32(volatile unsigned *addr) { unsigned ret;

__asm__ __volatile__("lduwa [%1] 0x1d, %0\n\t"

:"=r"(ret):"r"(addr):"memory");

__asm__ __volatile__("lduwa [%1] %2, %0\n\t"

: "=r"(ret)

: "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E_L)

: "memory");

return ret; }

static inline void out_le32(volatile unsigned *addr, int val) {

__asm__ __volatile__("stwa %0, [%1] 0x15\n\t"

: : "r"(val), "r"(addr):"memory");

__asm__ __volatile__("stwa %0, [%1] %2\n\t"

:

: "r"(val), "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E)

: "memory");

}

static inline void out_be32(volatile unsigned *addr, int val) {

__asm__ __volatile__("stwa %0, [%1] 0x1d\n\t"

: : "r"(val), "r"(addr):"memory");

__asm__ __volatile__("stwa %0, [%1] %2\n\t"

:

: "r"(val), "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E_L)

: "memory");

}

static inline void _insw_ns(volatile uint16_t * port, void *buf, int ns)

-- OpenBIOS http://openbios.org/ Mailinglist: http://lists.openbios.org/mailman/listinfo Free your System - May the Forth be with you

Igor Kovalenko

8:28 p.m.

New subject: [PATCH 2/3] sparc64: replace ASI numbers with macros

On Tue, May 25, 2010 at 11:28 PM, Blue Swirl blauwirbel@gmail.com wrote:

...

On Tue, May 25, 2010 at 12:12 PM, Igor V. Kovalenko igor.v.kovalenko@gmail.com wrote:

...
From: Igor V. Kovalenko igor.v.kovalenko@gmail.com

Signed-off-by: Igor V. Kovalenko igor.v.kovalenko@gmail.com

include/arch/sparc64/io.h | 61 ++++++++++++++++++++++++++++++--------------- 1 files changed, 41 insertions(+), 20 deletions(-)

diff --git a/include/arch/sparc64/io.h b/include/arch/sparc64/io.h index d6280fe..f9088c3 100644 --- a/include/arch/sparc64/io.h +++ b/include/arch/sparc64/io.h @@ -2,6 +2,7 @@ #define _ASM_IO_H

#include "asm/types.h" +#include "asi.h"

Shouldn't this be <asm/asi.h> after 1/3?

It ends up in the same directory so "asi.h" is good.

-- Kind regards, Igor V. Kovalenko

Igor V. Kovalenko

12:12 p.m.

New subject: [PATCH 3/3] sparc64: fix pci host bridge offsets

From: Igor V. Kovalenko igor.v.kovalenko@gmail.com

Signed-off-by: Igor V. Kovalenko igor.v.kovalenko@gmail.com --- arch/sparc64/openbios.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/sparc64/openbios.c b/arch/sparc64/openbios.c index 795d4f1..3f583f2 100644 --- a/arch/sparc64/openbios.c +++ b/arch/sparc64/openbios.c @@ -60,13 +60,13 @@ static const struct hwdef hwdefs[] = { .name = "SUNW,sabre", .vendor_id = PCI_VENDOR_ID_SUN, .device_id = PCI_DEVICE_ID_SUN_SABRE, - .cfg_addr = APB_SPECIAL_BASE + 0x1000000ULL, - .cfg_data = APB_MEM_BASE, - .cfg_base = 0x80000000ULL, - .cfg_len = 0, - .mem_base = APB_MEM_BASE + 0x400000ULL, + .cfg_addr = APB_SPECIAL_BASE + 0x1000000ULL, // PCI bus configuration space + .cfg_data = APB_MEM_BASE, // PCI bus memory space + .cfg_base = APB_SPECIAL_BASE, + .cfg_len = 0x2000000, + .mem_base = APB_MEM_BASE, .mem_len = 0x10000000, - .io_base = APB_SPECIAL_BASE + 0x2000000ULL, + .io_base = APB_SPECIAL_BASE + 0x2000000ULL, // PCI Bus I/O space .io_len = 0x10000, .irqs = { 0, 1, 2, 3 }, },

Blue Swirl

26 May 26 May

7:11 p.m.

On Tue, May 25, 2010 at 12:12 PM, Igor V. Kovalenko igor.v.kovalenko@gmail.com wrote:

...

One code cleanup and another pci host bridge remap change, the latter requires qemu update with patch already posted to qemu list.

v0->v1: added missing patch moving asi.h to arch includes

Thanks, applied all.

...

Igor V. Kovalenko (3): sparc64: move asi.h to arch includes sparc64: replace ASI numbers with macros sparc64: fix pci host bridge offsets

arch/sparc64/asi.h | 145 -------------------------------------------- arch/sparc64/entry.S | 2 - arch/sparc64/openbios.c | 12 ++-- arch/sparc64/spitfire.h | 2 - arch/sparc64/switch.S | 2 - arch/sparc64/vectors.S | 2 - include/arch/sparc64/asi.h | 145 ++++++++++++++++++++++++++++++++++++++++++++ include/arch/sparc64/io.h | 61 ++++++++++++------- 8 files changed, 196 insertions(+), 175 deletions(-) delete mode 100644 arch/sparc64/asi.h create mode 100644 include/arch/sparc64/asi.h

-- Signature

-- OpenBIOS http://openbios.org/ Mailinglist: http://lists.openbios.org/mailman/listinfo Free your System - May the Forth be with you

Mark Cave-Ayland

27 May 27 May

4:57 p.m.

Blue Swirl wrote:

...

On Tue, May 25, 2010 at 12:12 PM, Igor V. Kovalenko igor.v.kovalenko@gmail.com wrote:

...
One code cleanup and another pci host bridge remap change, the latter requires qemu update with patch already posted to qemu list.

v0->v1: added missing patch moving asi.h to arch includes

Thanks, applied all.

Whilst updating to OpenBIOS SVN and qemu git head to test these patches, I've found a regression with qemu-system-sparc64 and debian-504-sparc-netinst.iso. Rather than getting to the end of the kernel boot and being unable to mount the root filesystem, instead I now get the following fatal trap message:

[ 42.493402] Console: switching to mono PROM 128x96 [ 63.440200] [drm] Initialized drm 1.1.0 20060810 [ 63.542123] su: probe of ffe2dea0 failed with error -12 [ 63.690331] brd: module loaded [ 63.787034] loop: module loaded [ 63.863989] Uniform Multi-Platform E-IDE driver [ 63.961215] ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx [ 64.115119] mice: PS/2 mouse device common for all mice [ 64.234482] usbcore: registered new interface driver usbhid [ 64.359397] usbhid: v2.6:USB HID core driver [ 64.462167] TCP cubic registered [ 64.539714] NET: Registered protocol family 17 [ 64.642969] registered taskstats version 1 [ 64.737822] drivers/rtc/hctosys.c: unable to open rtc device (rtc0) qemu: fatal: Trap 0x0068 while trap level (5) >= MAXTL (5), Error state pc: 0000000000424d18 npc: 0000000000424d1c General Registers: %g0-3: 0000000000000000 0000000008000000 0000000000004000 0000000000000002 %g4-7: 00000000000003ff 0000000000000001 0000000000000020 0000000000004000

Current Register Window: %o0-3: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 %o4-7: 0000000000000000 0000000000000000 00000000fffd3ef0 0000000000000000 %l0-3: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 %l4-7: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 %i0-3: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 %i4-7: 0000000000000000 0000000000000000 0000000000000000 0000000000000000

Floating Point Registers: %f00: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f04: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f08: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f12: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f16: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f20: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f24: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f28: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f32: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f36: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f40: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f44: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f48: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f52: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f56: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f60: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 pstate: 00000414 ccr: 00 (icc: ---- xcc: ----) asi: 82 tl: 5 pil: 0 cansave: 6 canrestore: 0 otherwin: 0 wstate: 2 cleanwin: 0 cwp: 7 fsr: 0000000000000000 y: 0000000000000000 fprs: 0000000000000000 Aborted

Digging deeper, it seems that this was something that was introduced earlier than the last set of patches. Reverting to OpenBIOS SVN r777 and using 'git bisect', I can identify the offending commit in qemu git as 2aae2b8e0abd58e76d616bcbe93c6966d06d0188 "sparc64: fix pstate privilege bits". Does that help at all?

ATB,

Mark.

-- Mark Cave-Ayland - Senior Technical Architect PostgreSQL - PostGIS Sirius Corporation plc - control through freedom http://www.siriusit.co.uk t: +44 870 608 0063 Sirius Labs: http://www.siriusit.co.uk/labs

Blue Swirl

8:42 p.m.

On Thu, May 27, 2010 at 4:57 PM, Mark Cave-Ayland mark.cave-ayland@siriusit.co.uk wrote:

...

Blue Swirl wrote:

...
On Tue, May 25, 2010 at 12:12 PM, Igor V. Kovalenko igor.v.kovalenko@gmail.com wrote:

...
One code cleanup and another pci host bridge remap change, the latter requires qemu update with patch already posted to qemu list.

v0->v1: added missing patch moving asi.h to arch includes

Thanks, applied all.

Whilst updating to OpenBIOS SVN and qemu git head to test these patches, I've found a regression with qemu-system-sparc64 and debian-504-sparc-netinst.iso. Rather than getting to the end of the kernel boot and being unable to mount the root filesystem, instead I now get the following fatal trap message:

[ 42.493402] Console: switching to mono PROM 128x96 [ 63.440200] [drm] Initialized drm 1.1.0 20060810 [ 63.542123] su: probe of ffe2dea0 failed with error -12 [ 63.690331] brd: module loaded [ 63.787034] loop: module loaded [ 63.863989] Uniform Multi-Platform E-IDE driver [ 63.961215] ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx [ 64.115119] mice: PS/2 mouse device common for all mice [ 64.234482] usbcore: registered new interface driver usbhid [ 64.359397] usbhid: v2.6:USB HID core driver [ 64.462167] TCP cubic registered [ 64.539714] NET: Registered protocol family 17 [ 64.642969] registered taskstats version 1 [ 64.737822] drivers/rtc/hctosys.c: unable to open rtc device (rtc0) qemu: fatal: Trap 0x0068 while trap level (5) >= MAXTL (5), Error state pc: 0000000000424d18 npc: 0000000000424d1c General Registers: %g0-3: 0000000000000000 0000000008000000 0000000000004000 0000000000000002 %g4-7: 00000000000003ff 0000000000000001 0000000000000020 0000000000004000

Current Register Window: %o0-3: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 %o4-7: 0000000000000000 0000000000000000 00000000fffd3ef0 0000000000000000 %l0-3: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 %l4-7: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 %i0-3: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 %i4-7: 0000000000000000 0000000000000000 0000000000000000 0000000000000000

Floating Point Registers: %f00: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f04: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f08: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f12: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f16: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f20: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f24: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f28: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f32: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f36: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f40: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f44: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f48: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f52: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f56: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f60: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 pstate: 00000414 ccr: 00 (icc: ---- xcc: ----) asi: 82 tl: 5 pil: 0 cansave: 6 canrestore: 0 otherwin: 0 wstate: 2 cleanwin: 0 cwp: 7 fsr: 0000000000000000 y: 0000000000000000 fprs: 0000000000000000 Aborted

Digging deeper, it seems that this was something that was introduced earlier than the last set of patches. Reverting to OpenBIOS SVN r777 and using 'git bisect', I can identify the offending commit in qemu git as 2aae2b8e0abd58e76d616bcbe93c6966d06d0188 "sparc64: fix pstate privilege bits". Does that help at all?

Yes, bisection results are usually very helpful, thanks.

I think the problem is that previously psrs was always 1 and PSR_HYPV always set, so maximally permissive MMU_HYPV_INDEX was always selected by cpu_mmu_index (bug!). Also because PSR_HYPV is no longer set, some checks in translate.c indicate privilege violations.

The logic was previously such that if the CPU does not have a hypervisor mode, for compatibility, supervisor mode would also select hypervisor mode (or at least that was my intention and probably Igor wasn't aware of this, sorry). Now that they are separate, CPUs without hypervisor mode must be handled differently. Perhaps this commit should be reverted, the fix won't be so trivial.

The lesson here is also that subtle assumptions like this should be documented.

Igor Kovalenko

28 May 28 May

3:13 a.m.

On Fri, May 28, 2010 at 12:42 AM, Blue Swirl blauwirbel@gmail.com wrote:

...

On Thu, May 27, 2010 at 4:57 PM, Mark Cave-Ayland mark.cave-ayland@siriusit.co.uk wrote:

...
Blue Swirl wrote:

...
On Tue, May 25, 2010 at 12:12 PM, Igor V. Kovalenko igor.v.kovalenko@gmail.com wrote:

...
One code cleanup and another pci host bridge remap change, the latter requires qemu update with patch already posted to qemu list.

v0->v1: added missing patch moving asi.h to arch includes

Thanks, applied all.

Whilst updating to OpenBIOS SVN and qemu git head to test these patches, I've found a regression with qemu-system-sparc64 and debian-504-sparc-netinst.iso. Rather than getting to the end of the kernel boot and being unable to mount the root filesystem, instead I now get the following fatal trap message:

[ 42.493402] Console: switching to mono PROM 128x96 [ 63.440200] [drm] Initialized drm 1.1.0 20060810 [ 63.542123] su: probe of ffe2dea0 failed with error -12 [ 63.690331] brd: module loaded [ 63.787034] loop: module loaded [ 63.863989] Uniform Multi-Platform E-IDE driver [ 63.961215] ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx [ 64.115119] mice: PS/2 mouse device common for all mice [ 64.234482] usbcore: registered new interface driver usbhid [ 64.359397] usbhid: v2.6:USB HID core driver [ 64.462167] TCP cubic registered [ 64.539714] NET: Registered protocol family 17 [ 64.642969] registered taskstats version 1 [ 64.737822] drivers/rtc/hctosys.c: unable to open rtc device (rtc0) qemu: fatal: Trap 0x0068 while trap level (5) >= MAXTL (5), Error state pc: 0000000000424d18 npc: 0000000000424d1c General Registers: %g0-3: 0000000000000000 0000000008000000 0000000000004000 0000000000000002 %g4-7: 00000000000003ff 0000000000000001 0000000000000020 0000000000004000

Current Register Window: %o0-3: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 %o4-7: 0000000000000000 0000000000000000 00000000fffd3ef0 0000000000000000 %l0-3: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 %l4-7: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 %i0-3: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 %i4-7: 0000000000000000 0000000000000000 0000000000000000 0000000000000000

Floating Point Registers: %f00: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f04: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f08: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f12: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f16: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f20: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f24: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f28: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f32: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f36: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f40: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f44: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f48: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f52: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f56: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f60: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 pstate: 00000414 ccr: 00 (icc: ---- xcc: ----) asi: 82 tl: 5 pil: 0 cansave: 6 canrestore: 0 otherwin: 0 wstate: 2 cleanwin: 0 cwp: 7 fsr: 0000000000000000 y: 0000000000000000 fprs: 0000000000000000 Aborted

Digging deeper, it seems that this was something that was introduced earlier than the last set of patches. Reverting to OpenBIOS SVN r777 and using 'git bisect', I can identify the offending commit in qemu git as 2aae2b8e0abd58e76d616bcbe93c6966d06d0188 "sparc64: fix pstate privilege bits". Does that help at all?

Yes, bisection results are usually very helpful, thanks.

I think the problem is that previously psrs was always 1 and PSR_HYPV always set, so maximally permissive MMU_HYPV_INDEX was always selected by cpu_mmu_index (bug!). Also because PSR_HYPV is no longer set, some checks in translate.c indicate privilege violations.

The logic was previously such that if the CPU does not have a hypervisor mode, for compatibility, supervisor mode would also select hypervisor mode (or at least that was my intention and probably Igor wasn't aware of this, sorry). Now that they are separate, CPUs without hypervisor mode must be handled differently. Perhaps this commit should be reverted, the fix won't be so trivial.

I'll take a look at this issue.

...

The lesson here is also that subtle assumptions like this should be documented.

-- Kind regards, Igor V. Kovalenko

Igor Kovalenko

4:31 a.m.

On Thu, May 27, 2010 at 8:57 PM, Mark Cave-Ayland mark.cave-ayland@siriusit.co.uk wrote:

...

Blue Swirl wrote:

...
On Tue, May 25, 2010 at 12:12 PM, Igor V. Kovalenko igor.v.kovalenko@gmail.com wrote:

...
One code cleanup and another pci host bridge remap change, the latter requires qemu update with patch already posted to qemu list.

v0->v1: added missing patch moving asi.h to arch includes

Thanks, applied all.

Whilst updating to OpenBIOS SVN and qemu git head to test these patches, I've found a regression with qemu-system-sparc64 and debian-504-sparc-netinst.iso. Rather than getting to the end of the kernel boot and being unable to mount the root filesystem, instead I now get the following fatal trap message:

[ 42.493402] Console: switching to mono PROM 128x96 [ 63.440200] [drm] Initialized drm 1.1.0 20060810 [ 63.542123] su: probe of ffe2dea0 failed with error -12 [ 63.690331] brd: module loaded [ 63.787034] loop: module loaded [ 63.863989] Uniform Multi-Platform E-IDE driver [ 63.961215] ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx [ 64.115119] mice: PS/2 mouse device common for all mice [ 64.234482] usbcore: registered new interface driver usbhid [ 64.359397] usbhid: v2.6:USB HID core driver [ 64.462167] TCP cubic registered [ 64.539714] NET: Registered protocol family 17 [ 64.642969] registered taskstats version 1 [ 64.737822] drivers/rtc/hctosys.c: unable to open rtc device (rtc0) qemu: fatal: Trap 0x0068 while trap level (5) >= MAXTL (5), Error state pc: 0000000000424d18 npc: 0000000000424d1c General Registers: %g0-3: 0000000000000000 0000000008000000 0000000000004000 0000000000000002 %g4-7: 00000000000003ff 0000000000000001 0000000000000020 0000000000004000

Current Register Window: %o0-3: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 %o4-7: 0000000000000000 0000000000000000 00000000fffd3ef0 0000000000000000 %l0-3: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 %l4-7: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 %i0-3: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 %i4-7: 0000000000000000 0000000000000000 0000000000000000 0000000000000000

Floating Point Registers: %f00: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f04: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f08: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f12: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f16: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f20: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f24: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f28: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f32: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f36: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f40: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f44: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f48: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f52: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f56: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 %f60: 000000000.000000 000000000.000000 000000000.000000 000000000.000000 pstate: 00000414 ccr: 00 (icc: ---- xcc: ----) asi: 82 tl: 5 pil: 0 cansave: 6 canrestore: 0 otherwin: 0 wstate: 2 cleanwin: 0 cwp: 7 fsr: 0000000000000000 y: 0000000000000000 fprs: 0000000000000000 Aborted

Digging deeper, it seems that this was something that was introduced earlier than the last set of patches. Reverting to OpenBIOS SVN r777 and using 'git bisect', I can identify the offending commit in qemu git as 2aae2b8e0abd58e76d616bcbe93c6966d06d0188 "sparc64: fix pstate privilege bits". Does that help at all?

With many debian iso images I consistently get scrolling blanks after the following line on qemu video console:

io sched cfq registered (default)

Please share your qemu command line, and installer prompt input if any.

-- Kind regards, Igor V. Kovalenko

Mark Cave-Ayland

8:43 a.m.

Igor Kovalenko wrote:

...

With many debian iso images I consistently get scrolling blanks after the following line on qemu video console:

io sched cfq registered (default)

Please share your qemu command line, and installer prompt input if any.

Yeah, I do too. I originally thought that the Debian kernel was broken, but if you leave it long enough then it does proceed to the end. My guess is that there is a bug in the OpenBIOS console which is obscuring the output.

The first part of the boot below happens reasonably quickly; then like you the console puts out lots of junk before it returns:

OpenBIOS for Sparc64 Configuration device id QEMU version 1 machine id 0 kernel cmdline CPUs: 1 x SUNW,UltraSPARC-IIi UUID: 00000000-0000-0000-0000-000000000000 Welcome to OpenBIOS v1.0 built on May 28 2010 08:24 Type 'help' for detailed information

[sparc64] Booting file 'cdrom' with parameters '' Not a bootable ELF image Not a Linux kernel image Loading a.out image... Loaded 7680 bytes entry point is 0x4000

Jumping to entry point 0000000000004000 for type 0000000000000005... switching to new context: entry point 0x4000 stack 0x00000000ffe02b51 SILO Version 1.4.13 \

Welcome to Debian GNU/Linux lenny!

This is a Debian installation CDROM, built on 20100201-16:54. Keep it once you have installed your system, as you can boot from it to repair the system on your hard disk if that ever becomes necessary.

WARNING: You should completely back up all of your hard disks before proceeding. The installation procedure can completely and irreversibly erase them! If you haven't made backups yet, remove the rescue CD from the drive and press L1-A to get back to the OpenBoot prompt.

Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent permitted by applicable law.

[ ENTER - Boot install ] [ Type "expert" - Boot into expert mode ] [ Type "rescue" - Boot into rescue mode ] boot: Allocated 8 Megs of memory at 0x40000000 for kernel Loaded kernel version 2.6.26 Loading initial ramdisk (4312781 bytes at 0xC00000 phys, 0x40C00000 virt)... | [ 0.000000] PROMLIB: Sun IEEE Boot Prom 'OBP 3.10.24 1999/01/01 01:01' [ 0.000000] PROMLIB: Root node compatible: sun4u [ 0.000000] Initializing cgroup subsys cpu [ 0.000000] Linux version 2.6.26-2-sparc64 (Debian 2.6.26-21) (dannf@debian.org) (gcc version 4.1.3 20080704 (prerelease) (Debian 4.1.2-25)) #1 Tue Jan 12 22:16:05 UTC 2010 [ 0.000000] console [earlyprom0] enabled [ 0.000000] ARCH: SUN4U [ 0.000000] Ethernet address: 52:54:00:12:34:56 [ 0.000000] Kernel: Using 1 locked TLB entries for main kernel image. [ 0.000000] Remapping the kernel... done. [ 0.000000] OF stdout device is: /pci@1fe,0/ebus@3/su [ 0.000000] PROM: Built device tree with 32655 bytes of memory. [ 0.000000] Top of RAM: 0x7e80000, Total RAM: 0x7e80000 [ 0.000000] Memory hole size: 0MB [ 0.000000] [0000000200000000-fffff80000800000] page_structs=131072 node=0 entry=0/0 [ 0.000000] [0000000200000000-fffff80001400000] page_structs=131072 node=0 entry=1/0 [ 0.000000] Zone PFN ranges: [ 0.000000] Normal 0 -> 16192 [ 0.000000] Movable zone start PFN for each node [ 0.000000] early_node_map[1] active PFN ranges [ 0.000000] 0: 0 -> 16192 [ 0.000000] Booting Linux... [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 16081 [ 0.000000] Kernel command line: [ 0.000000] PID hash table entries: 512 (order: 9, 4096 bytes) [ 0.000000] clocksource: mult[a0000] shift[16] [ 0.000000] clockevent: mult[19999999] shift[32] [ 11.273908] Console: colour dummy device 80x25 [ 11.339826] console handover: boot [earlyprom0] -> real [tty0]

.... the console then prints blocks along the RHS of the screen for about 60s on my Intel Core 2 1.83GHz before returning...

[ 40.450573] Console: switching to mono PROM 128x96 [ 60.624138] [drm] Initialized drm 1.1.0 20060810 [ 60.725621] ffe2df18: ttyS0 at MMIO 0x1fe020003f8 (irq = 0) is a 16550A [ 60.849637] Console: ttyS0 (SU) [ 60.931684] console [ttyS0] enabled [ 0.000000] PROMLIB: Sun IEEE Boot Prom 'OBP 3.10.24 1999/01/01 01:01' [ 0.000000] PROMLIB: Root node compatible: sun4u .24 1999/01/01 01:01' [ 0.000000] Initializing cgroup subsys cpu sun4u [ 0.000000] Linux version 2.6.26-2-sparc64 (Debian 2.6.26-21) (dannf@debian.org) (gcc version 4.1.3 20080704 (prerelease) (Deeebian 4.1.2-25)) #1 Tue Jan 12 22:16:05 U bian 4.1.2-25)) #1 Tue Jan 12 22:16:05 UTC 2010 [ 0.000000] console [earlyprom0] enabled 4 (Debian 2.6.26-21) (dannf@debian.org) (gcc version 4.1.3 20080704 (prerelease) (De [ 0.000000] ARCH: SUN4U lyprom0] enabled [ 0.000000] Ethernet address: 52:54:00:12:34:56 [ 0.000000] Kernel: Using 1 locked TLB entries for main kernel image. [ 0.000000] Remapping the kernel... done. ries for main kernel image. [ 0.000000] OF stdout device is: /pci@1fe,0/ebus@3/su [ 0.000000] PROM: Built device tree with 32655 bytes of memory. [ 0.000000] Top of RAM: 0x7e80000, Total RAM: 0x7e80000 memory. 0.000000] [0000000200000000-fffff80000800000] page_structs=131072 node=0 entry=0/0 0.000000] Zone PFN ranges: -fffff80001400000] page_structs=131072 node=0 entry=1/0 0.000000] Movable zone start PFN for each node 0.000000] 0: 0 -> 16192 ranges 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 16081 0.000000] PID hash table entries: 512 (order: 9, 4096 bytes) 0.000000] clockevent: mult[19999999] shift[32] 10.861313] console handover: boot [earlyprom0] -> real [tty0] 10.943240] Inode-cache hash table entries: 8192 (order: 3, 65536 bytes)es) 11.052494] Calibrating delay using timer specific routine.. 203.38 BogoMIPS (lpj=406760)00000000,0000000007e80000] 11.057509] SELinux: Disabled at boot.zed 11.058937] Mount-cache hash table entries: 512 11.073067] Initializing cgroup subsys cpuacct 11.107516] net_namespace: 1208 bytess devices 11.160324] PCI: Probing for controllers.ly 16 11.166356] /pci@1f,0: PCI IO[1fe02000000] MEM[1ff00000000] 11.182694] ebus0: [fdthree] [su] [kb_ps2] 11.218962] usbcore: registered new interface driver hubfs 11.256772] NET: Registered protocol family 2iver usb 11.305741] TCP established hash table entries: 4096 (order: 3, 65536 bytes) 11.307073] TCP: Hash tables configured (established 4096 bind 4096)) [ 11.307399] TCP reno registerednfigured (established 4096 bind 4096) [ 11.317930] NET: Registered protocol family 1 [ 11.329393] checking if image is initramfs... it is [ 19.232833] Freeing initrd memory: 4211k freedit is [ 19.241377] audit: initializing netlink socket (disabled) [ 19.242582] type=2000 audit(8.292:1): initializedisabled) [ 19.246130] Total HugeTLB memory allocated, 0ized [ 19.250809] VFS: Disk quotas dquot_6.5.1ed, 0 [ 19.251650] Dquot-cache hash table entries: 1024 (order 0, 8192 bytes) [ 19.254760] msgmni has been set to 228ries: 1024 (order 0, 8192 bytes) [ 19.258260] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253) [ 19.258713] io scheduler noop registeredg) driver version 0.4 loaded (major 253) [ 19.258713] io scheduler noop registered [ 19.258943] io scheduler anticipatory registered [ 19.258943] io scheduler anticipatory registered [ 19.259135] io scheduler deadline registered [ 19.259135] io scheduler deadline registered [ 19.259503] io scheduler cfq registered (default) [ 19.259503] io scheduler cfq registered (default) [ 40.450573] Console: switching to mono PROM 128x96 [ 40.450573] Console: switching to mono PROM 128x96 [ 60.624138] [drm] Initialized drm 1.1.0 20060810 [ 60.624138] [drm] Initialized drm 1.1.0 20060810 [ 60.725621] ffe2df18: ttyS0 at MMIO 0x1fe020003f8 (irq = 0) is a 16550A [ 60.725621] ffe2df18: ttyS0 at MMIO 0x1fe020003f8 (irq = 0) is a 16550A [ 60.849637] Console: ttyS0 (SU) [ 60.849637] Console: ttyS0 (SU) [ 60.931684] console [ttyS0] enabled [ 60.931684] console [ttyS0] enabled [ 68.952023] brd: module loaded [ 68.952023] brd: module loaded [ 69.074597] loop: module loaded [ 69.074597] loop: module loaded [ 69.185675] Uniform Multi-Platform E-IDE driver [ 69.185675] Uniform Multi-Platform E-IDE driver [ 69.315268] ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx [ 69.315268] ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx [ 69.500789] mice: PS/2 mouse device common for all mice [ 69.500789] mice: PS/2 mouse device common for all mice [ 69.646046] usbcore: registered new interface driver usbhid [ 69.646046] usbcore: registered new interface driver usbhid [ 69.793655] usbhid: v2.6:USB HID core driver [ 69.793655] usbhid: v2.6:USB HID core driver [ 69.928176] TCP cubic registered [ 69.928176] TCP cubic registered [ 70.038642] NET: Registered protocol family 17 [ 70.038642] NET: Registered protocol family 17 [ 70.172972] registered taskstats version 1 [ 70.172972] registered taskstats version 1 [ 70.297926] drivers/rtc/hctosys.c: unable to open rtc device (rtc0) [ 70.297926] drivers/rtc/hctosys.c: unable to open rtc device (rtc0) [ 70.482657] su: Cannot register IRQ 0 [ 70.482657] su: Cannot register IRQ 0 qemu: fatal: Trap 0x0068 while trap level (5) >= MAXTL (5), Error state pc: 0000000000424d18 npc: 0000000000424d1c General Registers: %g0-3: 0000000000000000 0000000008000000 0000000000004000 0000000000000002 %g4-7: 00000000000003fe 0000000000000001 0000000000000020 0000000000004000

Current Register Window: %o0-3: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 %o4-7: 0000000000000000 0000000000000000 00000000ffb29ef0 0000000000000000 %l0-3: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 %l4-7: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 %i0-3: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 %i4-7: 0000000000000000 0000000000000000 0000000000000000 0000000000000000

It looks like your latest set of OpenBIOS patches has helped with the serial port, since before these the buffered portion (i.e. the part that I imagine is supposed to appear at the time when the blocks are being drawn on the console) never used to appear. Not quite sure why some of the entries are duplicated though.

Finally, the command line I am using is:

./qemu-system-sparc64 -cdrom debian-504-sparc-netinst.iso -nographic -boot d

HTH,

Mark.

Igor Kovalenko

9:03 a.m.

On Fri, May 28, 2010 at 12:43 PM, Mark Cave-Ayland mark.cave-ayland@siriusit.co.uk wrote:

...

Igor Kovalenko wrote:

...
With many debian iso images I consistently get scrolling blanks after the following line on qemu video console:

io sched cfq registered (default)

Please share your qemu command line, and installer prompt input if any.

Yeah, I do too. I originally thought that the Debian kernel was broken, but if you leave it long enough then it does proceed to the end. My guess is that there is a bug in the OpenBIOS console which is obscuring the output.

I allowed it to scroll and now I can confirm it would crash with tl=5. Last insn is ldda with ASI=0x24 (Nucleus quad LDD 128 bit atomic)

IN: 0x0000000000424d18: ldda [ %g1 ] (36), %g4 0x0000000000424d1c: cmp %g4, %g6 0x0000000000424d20: bne,pn %xcc, 0x4076c0 0x0000000000424d24: mov 2, %g3

qemu: fatal: Trap 0x0068 while trap level (5) >= MAXTL (5), Error state pc: 0000000000424d18 npc: 0000000000424d1c General Registers: %g0-3: 0000000000000000 0000000008000000 0000000000004000 0000000000000002 %g4-7: 00000000000003ff 0000000000000001 0000000000000020 0000000000004000

Well, not sure how it worked before. Related code in helper_ld_asi() states:

case 0x24: // Nucleus quad LDD 128 bit atomic case 0x2c: // Nucleus quad LDD 128 bit atomic LE // Only ldda allowed raise_exception(TT_ILL_INSN); return 0;

HelenOS also uses quad ldd when configured with TSB for memory management. I guess that atomic quad ldd deserves to be implemented. I'll see if it is not hard.

-- Kind regards, Igor V. Kovalenko

Jakub Jermar

9:24 a.m.

On 05/28/2010 11:03 AM, Igor Kovalenko wrote:

...

On Fri, May 28, 2010 at 12:43 PM, Mark Cave-Ayland mark.cave-ayland@siriusit.co.uk wrote:

...
Igor Kovalenko wrote:

I allowed it to scroll and now I can confirm it would crash with tl=5. Last insn is ldda with ASI=0x24 (Nucleus quad LDD 128 bit atomic)

IN: 0x0000000000424d18: ldda [ %g1 ] (36), %g4 0x0000000000424d1c: cmp %g4, %g6 0x0000000000424d20: bne,pn %xcc, 0x4076c0 0x0000000000424d24: mov 2, %g3

qemu: fatal: Trap 0x0068 while trap level (5)>= MAXTL (5), Error state pc: 0000000000424d18 npc: 0000000000424d1c General Registers: %g0-3: 0000000000000000 0000000008000000 0000000000004000 0000000000000002 %g4-7: 00000000000003ff 0000000000000001 0000000000000020 0000000000004000

Well, not sure how it worked before. Related code in helper_ld_asi() states:
 case 0x24: // Nucleus quad LDD 128 bit atomic
 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
     //  Only ldda allowed
     raise_exception(TT_ILL_INSN);
     return 0;
HelenOS also uses quad ldd when configured with TSB for memory management. I guess that atomic quad ldd deserves to be implemented. I'll see if it is not hard.

The LDDA instruction is an essential instruction for TLB miss handlers that are TSB-aware. Except for HelenOS, where one can disable TSB, I'd expect all the other OSes that run on sparc64 to use it unconditionally.

Jakub

Andreas Färber

4:17 p.m.

Am 28.05.2010 um 10:43 schrieb Mark Cave-Ayland:

...

[ 60.725621] ffe2df18: ttyS0 at MMIO 0x1fe020003f8 (irq = 0) is a 16550A [ 60.849637] Console: ttyS0 (SU) [ 60.931684] console [ttyS0] enabled

[...]

...

[ 19.251650] Dquot-cache hash table entries: 1024 (order 0, 8192 bytes) [ 19.254760] msgmni has been set to 228ries: 1024 (order 0, 8192 bytes) [ 19.258260] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253) [ 19.258713] io scheduler noop registeredg) driver version 0.4 loaded (major 253) [ 19.258713] io scheduler noop registered [ 19.258943] io scheduler anticipatory registered [ 19.258943] io scheduler anticipatory registered [ 19.259135] io scheduler deadline registered [ 19.259135] io scheduler deadline registered [ 19.259503] io scheduler cfq registered (default) [ 19.259503] io scheduler cfq registered (default) [ 40.450573] Console: switching to mono PROM 128x96 [ 40.450573] Console: switching to mono PROM 128x96 [ 60.624138] [drm] Initialized drm 1.1.0 20060810 [ 60.624138] [drm] Initialized drm 1.1.0 20060810 [ 60.725621] ffe2df18: ttyS0 at MMIO 0x1fe020003f8 (irq = 0) is a 16550A [ 60.725621] ffe2df18: ttyS0 at MMIO 0x1fe020003f8 (irq = 0) is a 16550A [ 60.849637] Console: ttyS0 (SU) [ 60.849637] Console: ttyS0 (SU) [ 60.931684] console [ttyS0] enabled [ 60.931684] console [ttyS0] enabled [ 68.952023] brd: module loaded [ 68.952023] brd: module loaded [ 69.074597] loop: module loaded [ 69.074597] loop: module loaded [ 69.185675] Uniform Multi-Platform E-IDE driver [ 69.185675] Uniform Multi-Platform E-IDE driver [ 69.315268] ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx [ 69.315268] ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx [ 69.500789] mice: PS/2 mouse device common for all mice [ 69.500789] mice: PS/2 mouse device common for all mice [ 69.646046] usbcore: registered new interface driver usbhid [ 69.646046] usbcore: registered new interface driver usbhid [ 69.793655] usbhid: v2.6:USB HID core driver [ 69.793655] usbhid: v2.6:USB HID core driver [ 69.928176] TCP cubic registered [ 69.928176] TCP cubic registered [ 70.038642] NET: Registered protocol family 17 [ 70.038642] NET: Registered protocol family 17 [ 70.172972] registered taskstats version 1 [ 70.172972] registered taskstats version 1 [ 70.297926] drivers/rtc/hctosys.c: unable to open rtc device (rtc0) [ 70.297926] drivers/rtc/hctosys.c: unable to open rtc device (rtc0) [ 70.482657] su: Cannot register IRQ 0 [ 70.482657] su: Cannot register IRQ 0

[...]

...

It looks like your latest set of OpenBIOS patches has helped with the serial port, since before these the buffered portion (i.e. the part that I imagine is supposed to appear at the time when the blocks are being drawn on the console) never used to appear.

...

Not quite sure why some of the entries are duplicated though.

[...]

...

./qemu-system-sparc64 -cdrom debian-504-sparc-netinst.iso -nographic -boot d

Probably the kernel directs certain output to both stdio and ttyS0, which -nographic redirects to stdio? Those "mixed" lines might then be the result of a concurrent \r serial output...

Or do you get this with SDL, too?

Andreas

Igor Kovalenko

1 Jun 1 Jun

8:19 p.m.

On Wed, May 26, 2010 at 11:11 PM, Blue Swirl blauwirbel@gmail.com wrote:

...

On Tue, May 25, 2010 at 12:12 PM, Igor V. Kovalenko igor.v.kovalenko@gmail.com wrote:

...
One code cleanup and another pci host bridge remap change, the latter requires qemu update with patch already posted to qemu list.

v0->v1: added missing patch moving asi.h to arch includes

Thanks, applied all.

Can you please update qemu binary images?

-- Kind regards, Igor V. Kovalenko

5319

days inactive

5326

days old

openbios@openbios.org

15 comments

6 participants

tags (0)

participants (6)

Andreas Färber
Blue Swirl
Igor Kovalenko
Igor V. Kovalenko
Jakub Jermar
Mark Cave-Ayland