On Thu, 15 Jul 1999 12:31:48 -0400 (EDT), Kevin P Lawton wrote:
Also IMHO, by far their greatest mistake in history was when they went to a new protected mode environment in the 286, they carried forward the segmentation architecture.
But they had to. The 286 is a 16-bit processor. Without segmented memory, you would be limited to 64k of memory... Leaving protected mode out of it, the rest of the 286 was merely an evolution of the 80186: a change from a 20-bit memory bus to a 24-bit. That's the only real change. Of course, there *is* protected mode...
Only with a 32-bit processor can you realistically eliminate segmented memory.
Tim Massey
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On Thu, 15 Jul 1999, Timothy J. Massey wrote:
Only with a 32-bit processor can you realistically eliminate segmented memory.
Don't say that: There are some Xeon motherboards around (well, most of them are sold in complete supported systems) supporting 16GB of memory and more. Since you need more than 32 bits to address this space, they had to design work-arounds like segmentation (I don't know anything more about it). Even worse: The switching is done externally, by the chipset...
Tim Massey
Sehr Wus, - Matthias
On Thu, 15 Jul 1999, [iso-8859-1] Matthias Wächter wrote:
Don't say that: There are some Xeon motherboards around (well, most of them are sold in complete supported systems) supporting 16GB of memory and more. Since you need more than 32 bits to address this space, they had to design work-arounds like segmentation (I don't know anything more about it). Even worse: The switching is done externally, by the chipset...
You haven't read Intel processor specifications, have you?
Since PPro ia32 processors support the so called Physical Address Extensions which for current processors allow to address up to 64 GB of memory. The limitation comes from the limited number of processor's address lines which currently support 36-bit addressing.
Using Physical Address Extensions the CPU may address memory above 4 GB using C-mode paging which needs a special setup of page tables; in general after setting the PAE bit of CR4, paging becomes three-level deep and CR3 becomes PDBR (Page Directory Base Register). Page directory and table entries are now 64-bit. You have a choice of 4 kB and 2 MB page sizes in this mode. See Intel documentation for details.
Actually A-step Pentiums also included this feature but probably due to bugs in the implementation the feature has been removed for B-step and later chips. A-step chips were never available to the market.
Since PII Xeon, some further extensions were added -- see appropriate docs.
But they had to. The 286 is a 16-bit processor. Without segmented memory, you would be limited to 64k of memory... Leaving protected mode out of it, the rest of the 286 was merely an evolution of the 80186: a change from a 20-bit memory bus to a 24-bit. That's the only real change. Of course, there *is* protected mode...
It didn't have to be a 16bit processor, if they went to a new architecture. They could have made it 64 if they wanted to. You don't need segmented memory to access > 64k if your architecture is 32 or 64bit.
Should have dropped real mode, had the CPU start out in protected mode, and today we'd all have protected mode only BIOSs. Oh well, such is life.
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