Re: Openbios code for IRQ or interrupt handling?

[Jd Lyons]

I can’t figure out this race condition but it causes an IRQ storm. I feel like I’m in the old days of PC’s when to had IRQ conflicts and had to sort them yourself deep in the bios. As a Mac person I only had to deal with that on a few friends PC’s. Starting the second CPU in a on state rather than halted just makes the race condition worse, twice as fast, and Openbios doesn’t want to get to the prompt, but throwing 3, 8, or 9 CPUs at it in a running state gets me to the prompt, but it ignores -prom-env setting with anything more that three.

300% cpu usage just speeds up the race condition and IRQ storm so IDE craps out before you can load BootX or a linux kernel.

Then noting happens but the IRG storm and GPIO 1 asserting 0, likely to all the other CPUs, and that is likely the race conditions and pulling that low trigger the IRQ storm.

I can’t make it stop, I even tied all IRQ and Interrupts handling to CPU0, and that working until the OS Kenral loads and starts sending stuff to CPU1, which is still in a halted state unless I start it with my hack. Even with only CPU0 dealing with IRQs and Interrupts the race condition is still there and the IRQ storm.

I have to figure out why GPIO 1keeps getting triggered in a loop to pull low????
> On Feb 19, 2025, at 1:29 AM, Jd Lyons  wrote:
>
> Thanks Mark, I got side traced thinking open-pic when I should have been looking at GPIO because it is the one that is the gpio-parent there should be no interrupt-parent property. I think the gpio phandle is 7.
>
> Can you tell me how IRQ’s get assigned to CPU0?
>
> Interrupts?
> > On Feb 18, 2025, at 5:00 PM, Mark Cave-Ayland  wrote:
> >
> > On 18/02/2025 21:34, Jd Lyons via OpenBIOS wrote:
> > > I don’t know why, I can’t seem to get Openbios to set and interrupt-parent in the init.c for any /cpus, this code should work, no?
> > > void add_cpu_nodes(void) {
> > >     int num_cpus = fw_cfg_read_i32(FW_CFG_NB_CPUS);
> > >     printk("Detected %d CPUs\n", num_cpus);
> > >     /* Ensure /cpus node exists */
> > >     phandle cpus_node = dt_find_by_path("/cpus");
> > >     if (!cpus_node) {
> > >         printk("ERROR: /cpus node not found! Delaying CPU setup.\n");
> > >         return;
> > >     }
> > >     /* Wait until the interrupt controller exists */
> > >     phandle intc_node = NULL;
> > >     int retries = 5;
> > >     while (retries-- > 0) {
> > >         intc_node = dt_find_by_path("/pci/mac-io/@40000");
> >
> > Is this for the mac99 machine? If so you probably want /pci@f2000000/mac-io@c/interrupt-controller@40000 (see the output of show-devs for the full device paths).
> > >     if (intc_node) {
> > >         break;
> > >     }
> > >     printk("Waiting for /pci/mac-io/@40000...\\n");
> > >     msleep(100);  // Wait 100ms before retrying
> > > }
> > > if (!intc_node) {
> > >     printk("ERROR: Interrupt controller (/pci/mac-io/@40000) not found! SMP will not work.\\n");
> > >     return;
> > > }
> > > for (int i = 0; i < num_cpus; i++) {
> > >     phandle cpu_node = dt_new_node(cpus_node);
> > >     if (!cpu_node) {
> > >         printk("ERROR: Failed to create CPU node for CPU %d!\\n", i);
> > >         continue;
> > >     }
> > >     dt_set_property_string(cpu_node, "device_type", "cpu");
> > >     dt_set_property_string(cpu_node, "compatible", "PowerPC,G4");
> > >     /* Assign a unique CPU interrupt */
> > >     int cpu_irq[2] = { 16 + i, 0 };
> > >     dt_set_property_cells(cpu_node, "interrupts", cpu_irq, 2);
> > >     printk("CPU %d assigned IRQ %d\\n", i, cpu_irq[0]);
> > >     /* Ensure interrupt-parent is set */
> > >     dt_set_property_phandle(cpu_node, "interrupt-parent", intc_node);
> > >     printk("CPU %d linked to interrupt-parent /pci/mac-io/@40000\\n", i);
> > >     /* Register CPU ID */
> > >     PUSH(i);
> > >     fword("encode-int");
> > >     push_str("reg");
> > >     fword("property");
> > >     fword("finish-device");
> > >     printk("Initialized CPU %d\\n", i);
> > > }
> > >
> > > }
> >
> > ATB,
> >
> > Mark.

Openbios code for IRQ or interrupt handling?

[Jd Lyons]

emu-system-ppc64-unsigned: info: Core0: Set IDR 49 to 0x00000000<————THIS IS AN IRQ STORM
qemu-system-ppc64-unsigned: info: Core0: Set IDR 50 to 0x00000000
qemu-system-ppc64-unsigned: info: Core0: Set IDR 51 to 0x00000000
qemu-system-ppc64-unsigned: info: Core0: Set IDR 52 to 0x00000000
qemu-system-ppc64-unsigned: info: Core0: Set IDR 53 to 0x00000000
qemu-system-ppc64-unsigned: info: Core0: Set IDR 54 to 0x00000000
qemu-system-ppc64-unsigned: info: Core0: Set IDR 55 to 0x00000000
qemu-system-ppc64-unsigned: info: Core0: Set IDR 56 to 0x00000000
qemu-system-ppc64-unsigned: info: Core0: Set IDR 57 to 0x00000000
qemu-system-ppc64-unsigned: info: Core0: Set IDR 58 to 0x00000000
qemu-system-ppc64-unsigned: info: Core0: Set IDR 59 to 0x00000000
qemu-system-ppc64-unsigned: info: Core0: Set IDR 60 to 0x00000000
qemu-system-ppc64-unsigned: info: Core0: Set IDR 61 to 0x00000000
qemu-system-ppc64-unsigned: info: Core0: Set IDR 62 to 0x00000000
qemu-system-ppc64-unsigned: info: Core0: Set IDR 63 to 0x00000000
qemu-system-ppc64-unsigned: info: Core0: Set IDR 64 to 0x00000000
qemu-system-ppc64-unsigned: info: Core0: Set IDR 65 to 0x00000000
qemu-system-ppc64-unsigned: info: Core0: Set IDR 66 to 0x00000000
qemu-system-ppc64-unsigned: info: Core0: Set IDR 67 to 0x00000000
qemu-system-ppc64-unsigned: info: Core0: openpic_gbl_read: addr 0x1020<——————THIS IS WHERE WE GET mach_kernal
qemu-system-ppc64-unsigned: info: Core0: openpic_gbl_read: => 0x00000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 0 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 0 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 0 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x20 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 1 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 1 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 1 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x40 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 2 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 2 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 2 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x60 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 3 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 3 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 3 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x80 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 4 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 4 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 4 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0xa0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 5 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 5 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 5 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0xc0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 6 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 6 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 6 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0xe0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 7 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 7 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 7 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x100 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 8 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 8 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 8 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x120 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 9 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 9 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 9 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x140 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 10 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 10 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 10 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x160 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 11 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 11 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 11 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x180 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 12 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 12 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 12 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x1a0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 13 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 13 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 13 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x1c0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 14 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 14 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 14 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x1e0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 15 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 15 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 15 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x200 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 16 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 16 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 16 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x220 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 17 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 17 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 17 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x240 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 18 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 18 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 18 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x260 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 19 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 19 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 19 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x280 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 20 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 20 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 20 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x2a0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 21 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 21 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 21 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x2c0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 22 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 22 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 22 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x2e0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 23 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 23 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 23 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x300 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 24 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 24 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 24 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x320 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 25 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 25 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 25 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x340 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 26 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 26 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 26 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x360 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 27 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 27 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 27 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x380 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 28 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 28 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 28 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x3a0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 29 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 29 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 29 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x3c0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 30 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 30 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 30 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x3e0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 31 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 31 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 31 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x400 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 32 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 32 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 32 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x420 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 33 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 33 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 33 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x440 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 34 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 34 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 34 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x460 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 35 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 35 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 35 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x480 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 36 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 36 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 36 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x4a0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 37 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 37 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 37 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x4c0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 38 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 38 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 38 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x4e0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 39 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 39 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 39 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x500 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 40 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 40 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 40 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x520 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 41 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 41 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 41 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x540 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 42 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 42 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 42 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x560 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 43 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 43 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 43 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x580 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 44 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 44 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 44 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x5a0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 45 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 45 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 45 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x5c0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 46 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 46 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 46 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x5e0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 47 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 47 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 47 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x600 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 48 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 48 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 48 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x620 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 49 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 49 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 49 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x640 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 50 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 50 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 50 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x660 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 51 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 51 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 51 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x680 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 52 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 52 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 52 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x6a0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 53 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 53 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 53 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x6c0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 54 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 54 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 54 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x6e0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 55 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 55 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 55 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x700 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 56 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 56 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 56 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x720 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 57 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 57 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 57 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x740 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 58 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 58 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 58 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x760 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 59 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 59 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 59 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x780 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 60 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 60 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 60 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x7a0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 61 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 61 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 61 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x7c0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 62 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 62 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 62 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x7e0 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 63 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 63 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 63 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x800 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 64 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 64 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 64 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x820 <= 80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 65 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 65 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 65 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_gbl_write: addr 0x10e0 <= 000000ff
qemu-system-ppc64-unsigned: info: Core0: openpic_gbl_write: addr 0x1020 <= 20000000
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x390 <= 00000001
qemu-system-ppc64-unsigned: info: Core0: Set IDR 28 to 0x00000001
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x380 <= 8048001c
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 28 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 28 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 28 to 0x8048001c -> 0x8048001c
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x6f0 <= 00000001
qemu-system-ppc64-unsigned: info: Core0: Set IDR 55 to 0x00000001
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x6e0 <= 80080037
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 55 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 55 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 55 to 0x80080037 -> 0x80080037
qemu-system-ppc64-unsigned: info: Core0: openpic_src_read: addr 0x6e0
qemu-system-ppc64-unsigned: info: Core0: openpic_src_read: => 0x80080037
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x6e0 <= 00080037
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 55 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 55 to 0x00080037 -> 0x00080037
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x330 <= 00000001
qemu-system-ppc64-unsigned: info: Core0: Set IDR 25 to 0x00000001
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x320 <= 80480019
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 25 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 25 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 25 to 0x80480019 -> 0x80480019
qemu-system-ppc64-unsigned: info: Core0: openpic_src_read: addr 0x320
qemu-system-ppc64-unsigned: info: Core0: openpic_src_read: => 0x80480019
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x320 <= 00480019
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 25 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 25 to 0x00480019 -> 0x00480019
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x5f0 <= 00000001
qemu-system-ppc64-unsigned: info: Core0: Set IDR 47 to 0x00000001
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x5e0 <= 8048002f
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 47 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 47 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 47 to 0x8048002f -> 0x8048002f
qemu-system-ppc64-unsigned: info: Core0: openpic_src_read: addr 0x5e0
qemu-system-ppc64-unsigned: info: Core0: openpic_src_read: => 0x8048002f
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x5e0 <= 0048002f
qemu-system-ppc64-unsigned: info: Core0: IRQ_local_pipe: IRQ 47 active 1 was 0
qemu-system-ppc64-unsigned: info: Core0: IRQ_check: irq 47 set ivpr_pr=8 pr=-1
qemu-system-ppc64-unsigned: info: Core0: IRQ_local_pipe: IRQ 47 priority 8 too low for ctpr 15 on CPU 0
qemu-system-ppc64-unsigned: info: Core0: IRQ_local_pipe: IRQ 47 inactive, current prio 15/-1, CPU 0
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 47 to 0x0048002f -> 0x4048002f
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x50 <= 00000001
qemu-system-ppc64-unsigned: info: Core0: Set IDR 2 to 0x00000001
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x40 <= 80080002
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 2 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 2 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 2 to 0x80080002 -> 0x80080002
qemu-system-ppc64-unsigned: info: Core0: openpic_src_read: addr 0x40
qemu-system-ppc64-unsigned: info: Core0: openpic_src_read: => 0x80080002
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x40 <= 00080002
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 2 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 2 to 0x00080002 -> 0x00080002
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x1b0 <= 00000001
qemu-system-ppc64-unsigned: info: Core0: Set IDR 13 to 0x00000001
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x1a0 <= 8048000d
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 13 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 13 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 13 to 0x8048000d -> 0x8048000d
qemu-system-ppc64-unsigned: info: Core0: openpic_src_read: addr 0x1a0
qemu-system-ppc64-unsigned: info: Core0: openpic_src_read: => 0x8048000d
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x1a0 <= 0048000d
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 13 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 13 to 0x0048000d -> 0x0048000d
qemu-system-ppc64-unsigned: info: Core0: openpic: set irq 13 = 0 ivpr=0x0048000d
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 13 is already inactive
qemu-system-ppc64-unsigned: info: Core0: openpic: set irq 13 = 1 ivpr=0x0048000d
qemu-system-ppc64-unsigned: info: Core0: IRQ_local_pipe: IRQ 13 active 1 was 0
qemu-system-ppc64-unsigned: info: Core0: IRQ_check: irq 13 set ivpr_pr=8 pr=-1
qemu-system-ppc64-unsigned: info: Core0: IRQ_check: irq 47 set ivpr_pr=8 pr=8
qemu-system-ppc64-unsigned: info: Core0: IRQ_local_pipe: IRQ 13 priority 8 too low for ctpr 15 on CPU 0
qemu-system-ppc64-unsigned: info: Core0: IRQ_local_pipe: IRQ 13 inactive, current prio 15/-1, CPU 0
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x70 <= 00000001
qemu-system-ppc64-unsigned: info: Core0: Set IDR 3 to 0x00000001
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x60 <= 80080003
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 3 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 3 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 3 to 0x80080003 -> 0x80080003
qemu-system-ppc64-unsigned: info: Core0: openpic_src_read: addr 0x60
qemu-system-ppc64-unsigned: info: Core0: openpic_src_read: => 0x80080003
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x60 <= 00080003
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 3 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 3 to 0x00080003 -> 0x00080003
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x1d0 <= 00000001
qemu-system-ppc64-unsigned: info: Core0: Set IDR 14 to 0x00000001
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x1c0 <= 8048000e
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 14 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 14 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 14 to 0x8048000e -> 0x8048000e
qemu-system-ppc64-unsigned: info: Core0: openpic_src_read: addr 0x1c0
qemu-system-ppc64-unsigned: info: Core0: openpic_src_read: => 0x8048000e
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x1c0 <= 0048000e
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 14 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 14 to 0x0048000e -> 0x0048000e
qemu-system-ppc64-unsigned: info: Core0: openpic: set irq 14 = 0 ivpr=0x0048000e
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 14 is already inactive
qemu-system-ppc64-unsigned: info: Core0: openpic: set irq 14 = 1 ivpr=0x0048000e
qemu-system-ppc64-unsigned: info: Core0: IRQ_local_pipe: IRQ 14 active 1 was 0
qemu-system-ppc64-unsigned: info: Core0: IRQ_check: irq 13 set ivpr_pr=8 pr=-1
qemu-system-ppc64-unsigned: info: Core0: IRQ_check: irq 14 set ivpr_pr=8 pr=8
qemu-system-ppc64-unsigned: info: Core0: IRQ_check: irq 47 set ivpr_pr=8 pr=8
qemu-system-ppc64-unsigned: info: Core0: IRQ_local_pipe: IRQ 14 priority 8 too low for ctpr 15 on CPU 0
qemu-system-ppc64-unsigned: info: Core0: IRQ_local_pipe: IRQ 14 inactive, current prio 15/-1, CPU 0
qemu-system-ppc64-unsigned: info: Core0: openpic_gbl_write: addr 0x10b0 <= 800e0041
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 65 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 65 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 65 to 0x800e0041 -> 0x800e0041
qemu-system-ppc64-unsigned: info: Core0: openpic_gbl_read: addr 0x10b0
qemu-system-ppc64-unsigned: info: Core0: openpic_gbl_read: => 0x800e0041
qemu-system-ppc64-unsigned: info: Core0: openpic_gbl_write: addr 0x10b0 <= 000e0041
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 65 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 65 to 0x000e0041 -> 0x000e0041
qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: cpu 0 addr 0x80 <= 0x00000000
qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: set CPU 0 ctpr to 0, raised 8 servicing -1
qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: Raise OpenPIC INT output cpu 0 irq 13
qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: cpu 1 addr 0x1080 <= 0x00000000
qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: set CPU 1 ctpr to 0, raised 0 servicing 0
qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: Lower OpenPIC INT output cpu 1 due to ctpr
qemu-system-ppc64-unsigned: info: Core0: openpic_gbl_read: addr 0x10b0
qemu-system-ppc64-unsigned: info: Core0: openpic_gbl_read: => 0x000e0041
qemu-system-ppc64-unsigned: info: Core0: openpic_gbl_write: addr 0x10b0 <= 800e0041
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 65 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 65 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 65 to 0x800e0041 -> 0x800e0041
qemu-system-ppc64-unsigned: info: Core0: openpic_gbl_read: addr 0x10b0
qemu-system-ppc64-unsigned: info: Core0: openpic_gbl_read: => 0x800e0041
qemu-system-ppc64-unsigned: info: Core0: openpic_gbl_write: addr 0x10b0 <= 000e0041
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 65 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 65 to 0x000e0041 -> 0x000e0041
qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: cpu 0 addr 0x80 <= 0x00000000
qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: set CPU 0 ctpr to 0, raised 8 servicing -1
qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: Raise OpenPIC INT output cpu 0 irq 13
qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: cpu 1 addr 0x1080 <= 0x00000000
qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: set CPU 1 ctpr to 0, raised 0 servicing 0
qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: Lower OpenPIC INT output cpu 1 due to ctpr
qemu-system-ppc64-unsigned: info: Core0: openpic_src_read: addr 0x380
qemu-system-ppc64-unsigned: info: Core0: openpic_src_read: => 0x8048001c
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x380 <= 0048001c
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 28 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 28 to 0x0048001c -> 0x0048001c
qemu-system-ppc64-unsigned: info: Core0: openpic: set irq 25 = 0 ivpr=0x00480019
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 25 is already inactive
qemu-system-ppc64-unsigned: info: Core0: openpic: set irq 25 = 0 ivpr=0x00480019
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 25 is already inactive
qemu-system-ppc64-unsigned: info: Core0: openpic: set irq 25 = 0 ivpr=0x00480019
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 25 is already inactive
qemu-system-ppc64-unsigned: info: Core0: openpic: set irq 25 = 0 ivpr=0x00480019
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 25 is already inactive
qemu-system-ppc64-unsigned: info: Core0: openpic: set irq 25 = 0 ivpr=0x00480019
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 25 is already inactive
qemu-system-ppc64-unsigned: info: Core0: openpic: set irq 25 = 1 ivpr=0x00480019
qemu-system-ppc64-unsigned: info: Core0: IRQ_local_pipe: IRQ 25 active 1 was 0
qemu-system-ppc64-unsigned: info: Core0: IRQ_check: irq 13 set ivpr_pr=8 pr=-1
qemu-system-ppc64-unsigned: info: Core0: IRQ_check: irq 14 set ivpr_pr=8 pr=8
qemu-system-ppc64-unsigned: info: Core0: IRQ_check: irq 25 set ivpr_pr=8 pr=8
qemu-system-ppc64-unsigned: info: Core0: IRQ_check: irq 47 set ivpr_pr=8 pr=8
qemu-system-ppc64-unsigned: info: Core0: IRQ_local_pipe: Raise OpenPIC INT output cpu 0 irq 25/13
qemu-system-ppc64-unsigned: info: Core0: openpic: set irq 25 = 1 ivpr=0x40480019
qemu-system-ppc64-unsigned: info: Core0: IRQ_local_pipe: IRQ 25 active 1 was 1
qemu-system-ppc64-unsigned: info: Core0: IRQ_check: irq 13 set ivpr_pr=8 pr=-1
qemu-system-ppc64-unsigned: info: Core0: IRQ_check: irq 14 set ivpr_pr=8 pr=8
qemu-system-ppc64-unsigned: info: Core0: IRQ_check: irq 25 set ivpr_pr=8 pr=8
qemu-system-ppc64-unsigned: info: Core0: IRQ_check: irq 47 set ivpr_pr=8 pr=8
qemu-system-ppc64-unsigned: info: Core0: IRQ_local_pipe: Raise OpenPIC INT output cpu 0 irq 25/13
qemu-system-ppc64-unsigned: info: Core-1: openpic: set irq 28 = 1 ivpr=0x0048001c<—THIS IS WHERE OS X BRINGS UP THE SECOND CPU
qemu-system-ppc64-unsigned: info: Core-1: IRQ_local_pipe: IRQ 28 active 1 was 0
qemu-system-ppc64-unsigned: info: Core-1: IRQ_check: irq 13 set ivpr_pr=8 pr=-1
qemu-system-ppc64-unsigned: info: Core-1: IRQ_check: irq 14 set ivpr_pr=8 pr=8
qemu-system-ppc64-unsigned: info: Core-1: IRQ_check: irq 25 set ivpr_pr=8 pr=8
qemu-system-ppc64-unsigned: info: Core-1: IRQ_check: irq 28 set ivpr_pr=8 pr=8
qemu-system-ppc64-unsigned: info: Core-1: IRQ_check: irq 47 set ivpr_pr=8 pr=8
qemu-system-ppc64-unsigned: info: Core-1: IRQ_local_pipe: Raise OpenPIC INT output cpu 0 irq 28/13
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x3d0 <= 00000001
qemu-system-ppc64-unsigned: info: Core0: Set IDR 30 to 0x00000001
qemu-system-ppc64-unsigned: info: Core0: openpic_src_write: addr 0x3c0 <= 8048001e
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 30 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 30 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 30 to 0x8048001e -> 0x8048001e<<<————THIS IS WHERE WE HALT
> On Feb 19, 2025, at 1:50 AM, Jd Lyons via OpenBIOS  wrote:
>
> I can’t figure out this race condition but it causes an IRQ storm. I feel like I’m in the old days of PC’s when to had IRQ conflicts and had to sort them yourself deep in the bios. As a Mac person I only had to deal with that on a few friends PC’s. Starting the second CPU in a on state rather than halted just makes the race condition worse, twice as fast, and Openbios doesn’t want to get to the prompt, but throwing 3, 8, or 9 CPUs at it in a running state gets me to the prompt, but it ignores -prom-env setting with anything more that three.
>
> 300% cpu usage just speeds up the race condition and IRQ storm so IDE craps out before you can load BootX or a linux kernel.
>
> Then noting happens but the IRG storm and GPIO 1 asserting 0, likely to all the other CPUs, and that is likely the race conditions and pulling that low trigger the IRQ storm.
>
> I can’t make it stop, I even tied all IRQ and Interrupts handling to CPU0, and that working until the OS Kenral loads and starts sending stuff to CPU1, which is still in a halted state unless I start it with my hack. Even with only CPU0 dealing with IRQs and Interrupts the race condition is still there and the IRQ storm.
>
> I have to figure out why GPIO 1keeps getting triggered in a loop to pull low????
> > On Feb 19, 2025, at 1:29 AM, Jd Lyons  wrote:
> >
> > Thanks Mark, I got side traced thinking open-pic when I should have been looking at GPIO because it is the one that is the gpio-parent there should be no interrupt-parent property. I think the gpio phandle is 7.
> >
> > Can you tell me how IRQ’s get assigned to CPU0?
> >
> > Interrupts?
> > > On Feb 18, 2025, at 5:00 PM, Mark Cave-Ayland  wrote:
> > >
> > > On 18/02/2025 21:34, Jd Lyons via OpenBIOS wrote:
> > > > I don’t know why, I can’t seem to get Openbios to set and interrupt-parent in the init.c for any /cpus, this code should work, no?
> > > > void add_cpu_nodes(void) {
> > > >     int num_cpus = fw_cfg_read_i32(FW_CFG_NB_CPUS);
> > > >     printk("Detected %d CPUs\n", num_cpus);
> > > >     /* Ensure /cpus node exists */
> > > >     phandle cpus_node = dt_find_by_path("/cpus");
> > > >     if (!cpus_node) {
> > > >         printk("ERROR: /cpus node not found! Delaying CPU setup.\n");
> > > >         return;
> > > >     }
> > > >     /* Wait until the interrupt controller exists */
> > > >     phandle intc_node = NULL;
> > > >     int retries = 5;
> > > >     while (retries-- > 0) {
> > > >         intc_node = dt_find_by_path("/pci/mac-io/@40000");
> > >
> > > Is this for the mac99 machine? If so you probably want /pci@f2000000/mac-io@c/interrupt-controller@40000 (see the output of show-devs for the full device paths).
> > > >     if (intc_node) {
> > > >         break;
> > > >     }
> > > >     printk("Waiting for /pci/mac-io/@40000...\\n");
> > > >     msleep(100);  // Wait 100ms before retrying
> > > > }
> > > > if (!intc_node) {
> > > >     printk("ERROR: Interrupt controller (/pci/mac-io/@40000) not found! SMP will not work.\\n");
> > > >     return;
> > > > }
> > > > for (int i = 0; i < num_cpus; i++) {
> > > >     phandle cpu_node = dt_new_node(cpus_node);
> > > >     if (!cpu_node) {
> > > >         printk("ERROR: Failed to create CPU node for CPU %d!\\n", i);
> > > >         continue;
> > > >     }
> > > >     dt_set_property_string(cpu_node, "device_type", "cpu");
> > > >     dt_set_property_string(cpu_node, "compatible", "PowerPC,G4");
> > > >     /* Assign a unique CPU interrupt */
> > > >     int cpu_irq[2] = { 16 + i, 0 };
> > > >     dt_set_property_cells(cpu_node, "interrupts", cpu_irq, 2);
> > > >     printk("CPU %d assigned IRQ %d\\n", i, cpu_irq[0]);
> > > >     /* Ensure interrupt-parent is set */
> > > >     dt_set_property_phandle(cpu_node, "interrupt-parent", intc_node);
> > > >     printk("CPU %d linked to interrupt-parent /pci/mac-io/@40000\\n", i);
> > > >     /* Register CPU ID */
> > > >     PUSH(i);
> > > >     fword("encode-int");
> > > >     push_str("reg");
> > > >     fword("property");
> > > >     fword("finish-device");
> > > >     printk("Initialized CPU %d\\n", i);
> > > > }
> > > >
> > > > }
> > >
> > > ATB,
> > >
> > > Mark.
>
> OpenBIOS mailing list -- [e-mail]
> To unsubscribe send an email to [e-mail]

Openbios code for IRQ or interrupt handling?

[Mark Cave-Ayland]

On 19/02/2025 06:50, Jd Lyons via OpenBIOS wrote:
> I can’t figure out this race condition but it causes an IRQ storm. I feel like I’m in 
> the old days of PC’s when to had IRQ conflicts and had to sort them yourself deep in 
> the bios. As a Mac person I only had to deal with that on a few friends PC’s. 
> Starting the second CPU in a on state rather than halted just makes the race 
> condition worse, twice as fast, and Openbios doesn’t want to get to the prompt, but 
> throwing 3, 8, or 9 CPUs at it in a running state gets me to the prompt, but it 
> ignores -prom-env setting with anything more that three.
>
> 300% cpu usage just speeds up the race condition and IRQ storm so IDE craps out 
> before you can load BootX or a linux kernel.
>
> Then noting happens but the IRG storm and GPIO 1 asserting 0, likely to all the other 
> CPUs, and that is likely the race conditions and pulling that low trigger the IRQ storm.
>
> I can’t make it stop, I even tied all IRQ and Interrupts handling to CPU0, and that 
> working until the OS Kenral loads and starts sending stuff to CPU1, which is still in 
> a halted state unless I start it with my hack. Even with only CPU0 dealing with IRQs 
> and Interrupts the race condition is still there and the IRQ storm.
>
> I have to figure out why GPIO 1keeps getting triggered in a loop to pull low????

Specifically can you narrow it down to which patch or patches to QEMU/OpenBIOS cause 
the IRQ storm to start? It's almost impossible to provide some pointers without 
seeing all your changes. Perhaps push them to github or a somewhere similar?

ATB,

Mark.

Openbios code for IRQ or interrupt handling?

[Jd Lyons]

My local branch is mixed with attempted work arounds that just made the IRQ situation worse, this is the original patch to Openbios…

diff --git a/arch/ppc/qemu/init.c b/arch/ppc/qemu/init.c
index 253394c..7b7b09d 100644
--- a/arch/ppc/qemu/init.c
+++ b/arch/ppc/qemu/init.c
@@ -348,8 +348,9 @@ cpu_add_pir_property(void)
     unsigned long pir;

asm("mfspr %0, 1023\n"
-        : "=r"(pir) :);
+        : "=r"(pir) :);;
     PUSH(pir);
+    printk("Pir = %lu \n", pir);
     fword("encode-int");
     push_str("reg");
     fword("property");
@@ -381,9 +382,9 @@ static void
 cpu_g4_init(const struct cpudef *cpu)
 {
     cpu_generic_init(cpu);
-    cpu_add_pir_property();
+        //cpu_add_pir_property();

-    fword("finish-device");
+    //fword("finish-device");
 }

#ifdef CONFIG_PPC_64BITSUPPORT
@@ -1073,13 +1074,23 @@ arch_of_init(void)
     push_str("reg");
     fword("property");

+    int i;
+
+    for (i= 0; i<temp; i++) {
     cpu = id_cpu();
     cpu->initfn(cpu);
-    printk("CPU type %s\n", cpu->name);

-    snprintf(buf, sizeof(buf), "/cpus/%s", cpu->name);
+    printk("CPU type %s\n", cpu->name);
+        snprintf(buf, sizeof(buf), "/cpus/%s", cpu->name);
+       PUSH(i);
+        fword("encode-int");
+        push_str("reg");
+        fword("property");
+        fword("finish-device");
+    }
     ofmem_register(find_dev("/memory"), find_dev(buf));
     node_methods_init(buf);
+

#ifdef CONFIG_RTAS
     /* OldWorld Macs don't have an /rtas node. */

Let me do some house keeping and I’ll get you the diff for Qemu….
> On Feb 19, 2025, at 4:40 AM, Mark Cave-Ayland  wrote:
>
> On 19/02/2025 06:50, Jd Lyons via OpenBIOS wrote:
> > I can’t figure out this race condition but it causes an IRQ storm. I feel like I’m in the old days of PC’s when to had IRQ conflicts and had to sort them yourself deep in the bios. As a Mac person I only had to deal with that on a few friends PC’s. Starting the second CPU in a on state rather than halted just makes the race condition worse, twice as fast, and Openbios doesn’t want to get to the prompt, but throwing 3, 8, or 9 CPUs at it in a running state gets me to the prompt, but it ignores -prom-env setting with anything more that three.
> > 300% cpu usage just speeds up the race condition and IRQ storm so IDE craps out before you can load BootX or a linux kernel.
> > Then noting happens but the IRG storm and GPIO 1 asserting 0, likely to all the other CPUs, and that is likely the race conditions and pulling that low trigger the IRQ storm.
> > I can’t make it stop, I even tied all IRQ and Interrupts handling to CPU0, and that working until the OS Kenral loads and starts sending stuff to CPU1, which is still in a halted state unless I start it with my hack. Even with only CPU0 dealing with IRQs and Interrupts the race condition is still there and the IRQ storm.
> > I have to figure out why GPIO 1keeps getting triggered in a loop to pull low????
>
> Specifically can you narrow it down to which patch or patches to QEMU/OpenBIOS cause the IRQ storm to start? It's almost impossible to provide some pointers without seeing all your changes. Perhaps push them to github or a somewhere similar?
>
> ATB,
>
> Mark.

Openbios code for IRQ or interrupt handling?

[Jd Lyons]

This is the patch against the current master of qemu, it should apply clean now, but things changed a little a few days ago and I had to fix the patch.

--- /home/guest/botva/src/src/qemu/hw/ppc/mac_newworld.c    2024-03-27 06:44:12.068828324 +0300
+++ /hw/ppc/mac_newworld.c    2024-05-18 20:48:32.709184875 +0300
@@ -128,6 +128,15 @@
     cpu->env.nip = PROM_BASE + 0x100;
 }

+
+static void ppc_core99_reset_sec(void *opaque)
+{
+    PowerPCCPU *cpu = opaque;
+    CPUState *cs = CPU(cpu);
+    cpu_reset(cs);
+    cs->exception_index = EXCP_HLT;
+}
+
 /* PowerPC Mac99 hardware initialisation */
 static void ppc_core99_init(MachineState *machine)
 {
@@ -160,10 +169,27 @@
     for (i = 0; i < machine->smp.cpus; i++) {
         cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
         env = &cpu->env;
+    CPUState *cs;
+    cs = CPU(cpu);
+
+    /*
+    * Secondary CPU starts in halted state for now. Needs to change
+     * when implementing non-kernel boot.
+         */
+         object_property_set_bool(OBJECT(cs), "start-powered-off", i != 0,
+                                 &error_abort);
+        //qdev_realize_and_unref(DEVICE(cs), NULL, &error_fatal);

/* Set time-base frequency to 100 Mhz */
         cpu_ppc_tb_init(env, TBFREQ);
+
+        if(!i)
         qemu_register_reset(ppc_core99_reset, cpu);
+        else
+        /* Secondary CPUs */
+        qemu_register_reset(ppc_core99_reset_sec, cpu);
+
+        env->spr_cb[SPR_PIR].default_value  = i + 15;
     }

/* allocate RAM */
@@ -368,9 +394,13 @@
     qdev_prop_set_chr(dev, "chrA", serial_hd(0));
     qdev_prop_set_chr(dev, "chrB", serial_hd(1));

+pic_dev = DEVICE(object_resolve_path_component(macio, "pic"));
+    qdev_prop_set_uint32(pic_dev, "nb_cpus", machine->smp.cpus);
+
+
     pci_realize_and_unref(PCI_DEVICE(macio), pci_bus, &error_fatal);

-    pic_dev = DEVICE(object_resolve_path_component(macio, "pic"));
+
     for (i = 0; i < 4; i++) {
         qdev_connect_gpio_out(uninorth_pci_dev, i,
                               qdev_get_gpio_in(pic_dev, 0x1b + i));
@@ -575,7 +605,7 @@
     mc->init = ppc_core99_init;
     mc->block_default_type = IF_IDE;
     /* SMP is not supported currently */
-    mc->max_cpus = 1;
+    mc->max_cpus = 4;
     mc->default_boot_order = "cd";
     mc->default_display = "std";
     mc->default_nic = "sungem";
--- /home/guest/botva/src/src/qemu/hw/intc/openpic.c    2024-01-06 05:14:26.186344157 +0300
+++ /hw/intc/openpic.c    2024-05-18 05:51:47.360312824 +0300
@@ -1573,6 +1573,11 @@
         opp->nb_irqs = KEYLARGO_MAX_EXT;
         opp->vid = VID_REVISION_1_2;
         opp->vir = VIR_GENERIC;
+
+    opp->frr = ((opp->nb_irqs - 1) << FRR_NIRQ_SHIFT) |
+               ((opp->nb_cpus - 1) << FRR_NCPU_SHIFT) |
+               (opp->vid << FRR_VID_SHIFT);
+
         opp->vector_mask = 0xFF;
         opp->tfrr_reset = 4160000;
         opp->ivpr_reset = IVPR_MASK_MASK | IVPR_MODE_MASK;
@@ -1582,10 +1587,15 @@
         opp->irq_tim0 = KEYLARGO_TMR_IRQ;
         opp->brr1 = -1;
         opp->mpic_mode_mask = GCR_MODE_MIXED;
+
+        for (i = KEYLARGO_MAX_EXT; i < KEYLARGO_MAX_IRQ; i++) {
+        opp->src[i].type = IRQ_TYPE_NORMAL;
+        opp->src[i].level = false;
+    }

if (opp->nb_cpus != 1) {
-            error_setg(errp, "Only UP supported today");
-            return;
+            //error_setg(errp, "Only UP supported today");
+            //return;
         }

map_list(opp, list_le, &list_count);
I’m thinking we already had a race condition on mac99,via=pmu and smp just made it worse. The IPI code in OpenPIC likely needs some work too to clear some issues with smp. These patches are NOT Ready For Primetime by any means, I didn’t write them, they came from the list and emasculation forums.

I’ve looked them over and tested them and made a bunch of changes trying to get IDE working so we can boot an OS, but no luck, the IRQ storm and race condition screws up everything but video and you can’t mount any media on the IDE bus once you load a kernel, even OS 9’s nonaKernel.

Set debug to true in the openpic.c and you’ll get spammed with the IRQ storm.
> On Feb 19, 2025, at 7:26 AM, Jd Lyons via OpenBIOS  wrote:
>
> My local branch is mixed with attempted work arounds that just made the IRQ situation worse, this is the original patch to Openbios…
>
> diff --git a/arch/ppc/qemu/init.c b/arch/ppc/qemu/init.c
> index 253394c..7b7b09d 100644
> --- a/arch/ppc/qemu/init.c
> +++ b/arch/ppc/qemu/init.c
> @@ -348,8 +348,9 @@ cpu_add_pir_property(void)
>     unsigned long pir;
> asm("mfspr %0, 1023\n"
>    : "=r"(pir) :);
>    : "=r"(pir) :);;
> PUSH(pir);
> printk("Pir = %lu \n", pir);
> fword("encode-int");
> push_str("reg");
> fword("property");
>
> @@ -381,9 +382,9 @@ static void
> cpu_g4_init(const struct cpudef *cpu)
> {
>     cpu_generic_init(cpu);
> cpu_add_pir_property();
>    //cpu_add_pir_property();
>
> fword("finish-device");
> //fword("finish-device");
>
> }
>
> #ifdef CONFIG_PPC_64BITSUPPORT
> @@ -1073,13 +1074,23 @@ arch_of_init(void)
>     push_str("reg");
>     fword("property");
> int i;
> for (i= 0; i<temp; i++) {
> cpu = id_cpu();
> cpu->initfn(cpu);
>
> printk("CPU type %s\n", cpu->name);
>
> snprintf(buf, sizeof(buf), "/cpus/%s", cpu->name);
> printk("CPU type %s\n", cpu->name);
>    snprintf(buf, sizeof(buf), "/cpus/%s", cpu->name);
>   PUSH(i);
>    fword("encode-int");
>    push_str("reg");
>    fword("property");
>    fword("finish-device");
> }
> ofmem_register(find_dev("/memory"), find_dev(buf));
> node_methods_init(buf);
>
> #ifdef CONFIG_RTAS
>     /* OldWorld Macs don't have an /rtas node. */
>
> Let me do some house keeping and I’ll get you the diff for Qemu….
> > On Feb 19, 2025, at 4:40 AM, Mark Cave-Ayland  wrote:
> >
> > On 19/02/2025 06:50, Jd Lyons via OpenBIOS wrote:
> > > I can’t figure out this race condition but it causes an IRQ storm. I feel like I’m in the old days of PC’s when to had IRQ conflicts and had to sort them yourself deep in the bios. As a Mac person I only had to deal with that on a few friends PC’s. Starting the second CPU in a on state rather than halted just makes the race condition worse, twice as fast, and Openbios doesn’t want to get to the prompt, but throwing 3, 8, or 9 CPUs at it in a running state gets me to the prompt, but it ignores -prom-env setting with anything more that three.
> > > 300% cpu usage just speeds up the race condition and IRQ storm so IDE craps out before you can load BootX or a linux kernel.
> > > Then noting happens but the IRG storm and GPIO 1 asserting 0, likely to all the other CPUs, and that is likely the race conditions and pulling that low trigger the IRQ storm.
> > > I can’t make it stop, I even tied all IRQ and Interrupts handling to CPU0, and that working until the OS Kenral loads and starts sending stuff to CPU1, which is still in a halted state unless I start it with my hack. Even with only CPU0 dealing with IRQs and Interrupts the race condition is still there and the IRQ storm.
> > > I have to figure out why GPIO 1keeps getting triggered in a loop to pull low????
> >
> > Specifically can you narrow it down to which patch or patches to QEMU/OpenBIOS cause the IRQ storm to start? It's almost impossible to provide some pointers without seeing all your changes. Perhaps push them to github or a somewhere similar?
> >
> > ATB,
> >
> > Mark.
>
> OpenBIOS mailing list -- [e-mail]
> To unsubscribe send an email to [e-mail]

Openbios code for IRQ or interrupt handling?

[BALATON Zoltan]

On Wed, 19 Feb 2025, Jd Lyons wrote:
> This is the patch against the current master of qemu, it should apply 
> clean now, but things changed a little a few days ago and I had to fix 
> the patch.

[patch cut]
> I’m thinking we already had a race condition on mac99,via=pmu and smp 
> just made it worse.

What makes you think that?
> The IPI code in OpenPIC likely needs some work too to clear some issues 
> with smp.

The openpic code apparently works with the ppce500 machine with multiple 
CPUs so unless the Mac does something different or has a different openpic 
implementation it should be generally working even with SMP so I'm not 
sure it's within openpic or somewhere else. (Although e500 uses a 
different variant so it could be the problem is only with the variant Mac 
machines use. This would be selected by the mpic_version in openpic 
emulation so code guarded by that could be inspected.)
> These patches are NOT Ready For Primetime by any means, I didn’t write 
> them, they came from the list and emasculation forums.

Who wrote the patch? If they are not cc'd not much use to comment on it. I 
also did not find the discussion on the emaculation.com/forum so can't 
guess how you ended up with this patch.
> I’ve looked them over and tested them and made a bunch of changes trying 
> to get IDE working so we can boot an OS, but no luck, the IRQ storm and 
> race condition screws up everything but video and you can’t mount any 
> media on the IDE bus once you load a kernel, even OS 9’s nonaKernel.
>
> Set debug to true in the openpic.c and you’ll get spammed with the IRQ storm.

It's not an error in itself to see a lot of interrupts especially when 
loading something from a disk where in PIO mode you can get an interrupt 
for each sector or transfer so the question is rather if these interrupts 
end up at the right CPU and handled there correctly. Hopefully Linux would 
log if there was something off but I don't know and haven't seen the logs.

I also don't see anything in the patch to connect the GPIO to CPU reset. 
How did you solve the stuck CPU problem then?

Regards,
BALATON Zoltan

Openbios code for IRQ or interrupt handling?

[Jd Lyons]

> On Feb 19, 2025, at 12:52 PM, BALATON Zoltan  wrote:
>
> On Wed, 19 Feb 2025, Jd Lyons wrote:
> > This is the patch against the current master of qemu, it should apply clean now, but things changed a little a few days ago and I had to fix the patch.
>
> [patch cut]
> > I’m thinking we already had a race condition on mac99,via=pmu and smp just made it worse.
>
> What makes you think that?
> > The IPI code in OpenPIC likely needs some work too to clear some issues with smp.
>
> The openpic code apparently works with the ppce500 machine with multiple CPUs so unless the Mac does something different or has a different openpic implementation it should be generally working even with SMP so I'm not sure it's within openpic or somewhere else. (Although e500 uses a different variant so it could be the problem is only with the variant Mac machines use. This would be selected by the mpic_version in openpic emulation so code guarded by that could be inspected.)

I’ll have to check, I think the race condition is there even without these patches, or more CPUs trying to come out of reset, causes the race condition.

Thanks for pointing out the e500 machine I’ll look into the code and see if I can glean anything from it.
> > These patches are NOT Ready For Primetime by any means, I didn’t write them, they came from the list and emasculation forums.
>
> Who wrote the patch? If they are not cc'd not much use to comment on it. I also did not find the discussion on the emaculation.com/forum so can't guess how you ended up with this patch.

It was Andrew R., he posted the patch to qemu in the thread you two had last year at Qemu-ppc mailing list of the same name as this subject you pointed me too, but I had already read to start this In the first place. I thought I was replying to that thread over there but I must have started a duplicate thread. He posted the Openbios patch in a code box in the qemu subform at Emacultion.

https://www.emaculation.com/forum/viewtopic.php?t=12169

Not sure that link will serve the list.
> > I’ve looked them over and tested them and made a bunch of changes trying to get IDE working so we can boot an OS, but no luck, the IRQ storm and race condition screws up everything but video and you can’t mount any media on the IDE bus once you load a kernel, even OS 9’s nonaKernel.
> >
> > Set debug to true in the openpic.c and you’ll get spammed with the IRQ storm.
>
> It's not an error in itself to see a lot of interrupts especially when loading something from a disk where in PIO mode you can get an interrupt for each sector or transfer so the question is rather if these interrupts end up at the right CPU and handled there correctly. Hopefully Linux would log if there was something off but I don't know and haven't seen the logs.
>
> I also don't see anything in the patch to connect the GPIO to CPU reset. How did you solve the stuck CPU problem then?

I can’t figure out if the CPUs have conflating IRQs or the extra cpus have conflicting IRQs with the systems bus items, but IRQ 37 seem to hang in a loop while in Openbios and IRQ 13( IDE ) seem to hang in a loop while booting a kernel. I’m not sure I ever get additional cpus fully working, I stared the additional CPUs without them halted, but that made the race condition so fast I can’t even load a full boot loader to get a kernel up before IDE dies.

I did see 800% cpu usage out of qemu-system-ppc64 and it dipped down around 500% before the system just hung. So 5 cores of 8 were likely stuck in the race condition.

The additional cores will respond to IRQ/Interrupt changes, or that’s what the log shows.

I saw this before 10 or so years ago when I tried to hack in smp support. All the cores just maxed out all the time and you could not load a boot loader from Openbios.
> Regards,
> BALATON Zoltan

Openbios code for IRQ or interrupt handling?

[BALATON Zoltan]

I'm currently not getting messages from the openbios list so can only see 
your reply in the list archive (which is not very convenient) so I can't 
reply in detail but I saw this:
> I stared the additional CPUs without them halted, but that made the race 
> condition so fast I can’t even load a full boot loader to get a kernel 
> up before IDE dies.
>
> I did see 800% cpu usage out of qemu-system-ppc64 and it dipped down 
> around 500% before the system just hung. So 5 cores of 8 were likely 
> stuck in the race condition.

Starting with all CPUs running is certainly wrong. That means all of them 
will execute the OpenBIOS and kernel boot in parallel and step on each 
other's toes as they can't poke the same IDE device without mixing it up 
completely. This is not how it should work and as you've found it doesn't. 
Apparently it works as I explained in the thead last year and now at least 
two or three times again, that is to keep the secondary CPU halted and 
connect the right GPIO line to the reset line of the secondary CPU so the 
kernel can start it when it has set it up to run the code it's intended to 
run. All other than the first CPU should stay stopped until the kernel 
pokes the GPIO line to release it from reset and only the first CPU should 
run the OpenBIOS and kernel boot. If you haven't solved that GPIO 
connection yet then it's still the issue to solve before patching anything 
else.

Maybe you just need to change the code that connects OPENPIC_OUTPUT_RESET 
with PPC6xx_INPUT_HRESET in qemu/hw/ppc/mac_newworld.c to connect 
PPC6xx_INPUT_HRESET to some gpio line of the macio gpio part instead. That 
means instead of connecting PPC6xx_INPUT_HRESET to the openpic when the 
CPU is created it should do this later after macio is created and access 
the gpio lines there and connect them to the PPC6xx_INPUT_HRESET lines of 
the CPUs corresponding to what the Linux kernel expects so the right line 
resets the right CPU. I don't know if that's all that's wrong but we have 
already found out that at least this reset connection is wrong and needs 
to be fixed.

Regards,
BALATON Zoltan

Openbios code for IRQ or interrupt handling?

[BALATON Zoltan]

On Thu, 20 Feb 2025, BALATON Zoltan wrote:
> I'm currently not getting messages from the openbios list so can only see

I got this message back now so hopefully the list delivery is now 
resolved.

Regards,
BALATON Zoltan

Openbios code for IRQ or interrupt handling?

[BALATON Zoltan]

On Thu, 20 Feb 2025, BALATON Zoltan wrote:
> Maybe you just need to change the code that connects OPENPIC_OUTPUT_RESET 
> with PPC6xx_INPUT_HRESET in qemu/hw/ppc/mac_newworld.c to connect 
> PPC6xx_INPUT_HRESET to some gpio line of the macio gpio part instead. That

Searching for OPENPIC_OUTPUT_RESET shows it's related to OpenPIC PIR 
register:

qemu/hw/intc/openpic.c::openpic_gbl_write()
     case 0x1090: /* PIR */
         for (idx = 0; idx < opp->nb_cpus; idx++) {
             if ((val & (1 << idx)) && !(opp->pir & (1 << idx))) {
                 DPRINTF("Raise OpenPIC RESET output for CPU %d", idx);
                 dst = &opp->dst[idx];
                 qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]);
             } else if (!(val & (1 << idx)) && (opp->pir & (1 << idx))) {
                 DPRINTF("Lower OpenPIC RESET output for CPU %d", idx);
                 dst = &opp->dst[idx];
                 qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]);
             }
         }

so you can uncomment /* #define DEBUG_OPENPIC */ in this file and look for 
logs from above DPRINTFs when you run your SMP Linux kernel. If you don't 
see any of these in the log then this means this register is not used and 
the Mac likely does not use this but does the CPU resets through the GPIOs 
of the macio chip. I don't know if those are directly connected to the 
CPUs on the real machine or somehow cause the openpic PIR to be changed 
but connecting the CPU resets to the GPIO lines seems to be more likely 
and probably easier to do in QEMU as well. Maybe this PIR thing is what 
Motorola SoCs do to reset the cores within the SoC as comments on top of 
openpic.c says it was based on that. You could also check the openpic docs 
referenced in the comments to see how this should work or what PIR means 
at all. Maybe that would help understanding it. I don't know so I also 
don't understand but I'm too lazy to look up docs so I just keep guessing 
instead.

Or I can check Linux source to see if this is different on e500. It seems 
linux/arch/powerpc/platforms/85xx/smp.c calls mpic_reset_core() to do the 
same that the Mac does with GPIOs and and in 
linux/arch/powerpc/sysdev/mpic.c it seems mpic_reset_core() is poking the 
PIR which now I guess means Processor Init Register maybe. So I think my 
guess is correct, currently QEMU is wired for e500 but that's not correct 
for the Mac which does this with GPIOs in macio instead so that should be 
fixed. The Linux sources is the proof for this theory.

Regards,
BALATON Zoltan

Openbios code for IRQ or interrupt handling?

[Jd Lyons]

> On Feb 19, 2025, at 7:38 PM, BALATON Zoltan  wrote:
>
> On Thu, 20 Feb 2025, BALATON Zoltan wrote:
> > Maybe you just need to change the code that connects OPENPIC_OUTPUT_RESET with PPC6xx_INPUT_HRESET in qemu/hw/ppc/mac_newworld.c to connect PPC6xx_INPUT_HRESET to some gpio line of the macio gpio part instead. That
>
> Searching for OPENPIC_OUTPUT_RESET shows it's related to OpenPIC PIR register:
>
> qemu/hw/intc/openpic.c::openpic_gbl_write()
>    case 0x1090: /* PIR */
>        for (idx = 0; idx < opp->nb_cpus; idx++) {
>            if ((val & (1 << idx)) && !(opp->pir & (1 << idx))) {
>                DPRINTF("Raise OpenPIC RESET output for CPU %d", idx);
>                dst = &opp->dst[idx];
>                qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]);
>            } else if (!(val & (1 << idx)) && (opp->pir & (1 << idx))) {
>                DPRINTF("Lower OpenPIC RESET output for CPU %d", idx);
>                dst = &opp->dst[idx];
>                qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]);
>            }
>        }
>
> so you can uncomment /* #define DEBUG_OPENPIC */ in this file and look for logs from above DPRINTFs when you run your SMP Linux kernel. If you don't see any of these in the log then this means this register is not used and the Mac likely does not use this but does the CPU resets through the GPIOs of the macio chip. I don't know if those are directly connected to the CPUs on the real machine or somehow cause the openpic PIR to be changed but connecting the CPU resets to the GPIO lines seems to be more likely and probably easier to do in QEMU as well. Maybe this PIR thing is what Motorola SoCs do to reset the cores within the SoC as comments on top of openpic.c says it was based on that. You could also check the openpic docs referenced in the comments to see how this should work or what PIR means at all. Maybe that would help understanding it. I don't know so I also don't understand but I'm too lazy to look up docs so I just keep guessing instead.
>
> Or I can check Linux source to see if this is different on e500. It seems linux/arch/powerpc/platforms/85xx/smp.c calls mpic_reset_core() to do the same that the Mac does with GPIOs and and in linux/arch/powerpc/sysdev/mpic.c it seems mpic_reset_core() is poking the PIR which now I guess means Processor Init Register maybe. So I think my guess is correct, currently QEMU is wired for e500 but that's not correct for the Mac which does this with GPIOs in macio instead so that should be fixed. The Linux sources is the proof for this theory.
>
> Regards,
> BALATON Zoltan

Thanks Balaton, I’m working on the PIR code in the Openpic.c to see if I can resolve some of the issues with resets of the additional cpus. The limit for qemu ppc seems to be 32 cores but Openbios only seems to read 20 of them. At any rate, if I can get 2 or 4 cores working things will be that much faster, I just like to see all those cores in the device tree. I’m just toying around with more than 2 cores because that is all a PowerMac G4 ever had anyway.

On a side note, not unrelated I looked at my Dual CPU MDD PowerMac and found the GPIO has several nodes in the device tree, like 8 or 9 of them, I did not count. Anyways, it looks like only the top device pci/Mac-io/@50 is the GPIO for the CPUs and maybe some other stuff, and it has an extended gpio that looks like it may handle the other CPU or just some other system stuff, all the other GPIO entries in the deice tree below it on the Mac-io/ node say they are for audio.

A rather complex setup for builtin audio if you ask me, but if I have too I’ll probe the main gpio@50 and see if I can find how the cpus are brought out of reset.

Likely the code you pointed to is all we need to property reset the second cpu in qemu so that linux, OS 9, and OS X can bring it up and use it.

Openbios code for IRQ or interrupt handling?

[Jd Lyons]

Making some progress with spm as far as getting some useful debug info.

I seem to be raising an exception state when Mac OS X 10.4.11 Kernel loads and tries to reset and wake the additional cores

qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 255 is disabled
qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 255 is already inactive
qemu-system-ppc64-unsigned: info: Core0: Set IVPR 255 to 0x80000000 -> 0x80000000
qemu-system-ppc64-unsigned: info: Core0: openpic_gbl_write: addr 0x10e0 <= 000000ff
qemu-system-ppc64-unsigned: info: Core0: openpic_gbl_write: addr 0x1020 <= 20000000
qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: cpu 0 addr 0x80 <= 0x00000000
qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: set CPU 0 ctpr to 0, raised 0 servicing 0
qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: Lower OpenPIC INT output cpu 0 due to ctpr
qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: cpu 1 addr 0x1080 <= 0x00000000
qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: set CPU 1 ctpr to 0, raised 0 servicing 0
qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: Lower OpenPIC INT output cpu 1 due to ctpr
qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: cpu 2 addr 0x2080 <= 0x00000000
qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: set CPU 2 ctpr to 0, raised 0 servicing 0
qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: Lower OpenPIC INT output cpu 2 due to ctpr
qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: cpu 3 addr 0x3080 <= 0x00000000
qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: set CPU 3 ctpr to 0, raised 0 servicing 0
qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: Lower OpenPIC INT output cpu 3 due to ctpr<—exception state starts here and terminal output ends after the kernel tries to enable the additional cores but accesses the non-existent L2 CR( SPR 1012 )

Raise exception at 00000000fff10698 => DSI (2) error=00
Raise exception at 00000000fff17098 => ISI (3) error=40000000
Raise exception at 00000000fff0ad08 => DSI (2) error=00
Raise exception at 00000000fff171f4 => DSI (2) error=00
Trying to read invalid spr 1012 (0x3f4) at 0000000000092884 <———————Here from the qemu log that we raise an exception state when the kernel tries to read the L2 cache cr

Raise exception at 00000000000af72c => SYSCALL (8) error=00
syscall r0=0000000000007ff4 r3=0000000000000000 r4=0000000000000000 r5=0000000000000000 r6=0000000000000000 r7=0000000000000000 r8=0000000072696e67 nip=00000000000af72c
Raise exception at 000000000009cefc => SYSCALL (8) error=00
syscall r0=0000000000007ff4 r3=0000000000000000 r4=0000000000000000 r5=0000000000959000 r6=0000000000000000 r7=ffffffffff77d000 r8=0000000000000883 nip=000000000009cefc
Raise exception at 000000000009cefc => SYSCALL (8) error=00
syscall r0=0000000000007ff4 r3=0000000000000000 r4=0000000000883c80 r5=0000000000000000 r6=0000000000000006 r7=0000000000000000 r8=0000000000000884 nip=000000000009cefc
Raise exception at 000000000009cefc => SYSCALL (8) error=00
syscall r0=0000000000007ff4 r3=0000000000000000 r4=0000000000884c80 r5=0000000000000000 r6=000000000000000c r7=0000000000883000 r8=0000000000000885 nip=000000000009cefc
Raise exception at 000000000009cefc => SYSCALL (8) error=00
syscall r0=0000000000007ff4 r3=0000000000000000 r4=0000000000885c80 r5=0000000000000000 r6=0000000000000012 r7=0000000000884000 r8=0000000000000886 nip=000000000009cefc
Raise exception at 000000000009cefc => SYSCALL (8) error=00
syscall r0=0000000000007ff4 r3=0000000000000000 r4=0000000000886c80 r5=0000000000000000 r6=0000000000000018 r7=0000000000885000 r8=0000000000000887 nip=000000000009cefc
Raise exception at 000000000009cefc => SYSCALL (8) error=00
syscall r0=0000000000007ff4 r3=0000000000000000 r4=0000000000887c80 r5=0000000000000000 r6=000000000000001e r7=0000000000886000 r8=0000000000000888 nip=000000000009cefc
Raise exception at 000000000009cefc => SYSCALL (8) error=00
syscall r0=0000000000007ff4 r3=0000000000000000 r4=0000000000888c80 r5=0000000000000000 r6=0000000000000024 r7=0000000000887000 r8=0000000000000889 nip=000000000009cefc
Raise exception at 000000000009cefc => SYSCALL (8) error=00
syscall r0=0000000000007ff4 r3=0000000000000000 r4=0000000000889c80 r5=0000000000000000 r6=000000000000002a r7=0000000000888000 r8=000000000000088a nip=000000000009cefc
Raise exception at 000000000009cefc => SYSCALL (8) error=00
syscall r0=0000000000007ff4 r3=0000000000000000 r4=00000000003d91c0 r5=00000000ffffffe8 r6=0000000000005140 r7=0000000000000000 r8=000000000000088b nip=000000000009cefc
Raise exception at 000000000009cefc => SYSCALL (8) error=00
> On Feb 20, 2025, at 8:41 AM, Jd Lyons via OpenBIOS  wrote:
> > On Feb 19, 2025, at 7:38 PM, BALATON Zoltan  wrote:
> >
> > On Thu, 20 Feb 2025, BALATON Zoltan wrote:
> > > Maybe you just need to change the code that connects OPENPIC_OUTPUT_RESET with PPC6xx_INPUT_HRESET in qemu/hw/ppc/mac_newworld.c to connect PPC6xx_INPUT_HRESET to some gpio line of the macio gpio part instead. That
> >
> > Searching for OPENPIC_OUTPUT_RESET shows it's related to OpenPIC PIR register:
> >
> > qemu/hw/intc/openpic.c::openpic_gbl_write()
> >   case 0x1090: /* PIR */
> >       for (idx = 0; idx < opp->nb_cpus; idx++) {
> >           if ((val & (1 << idx)) && !(opp->pir & (1 << idx))) {
> >               DPRINTF("Raise OpenPIC RESET output for CPU %d", idx);
> >               dst = &opp->dst[idx];
> >               qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]);
> >           } else if (!(val & (1 << idx)) && (opp->pir & (1 << idx))) {
> >               DPRINTF("Lower OpenPIC RESET output for CPU %d", idx);
> >               dst = &opp->dst[idx];
> >               qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]);
> >           }
> >       }
> >
> > so you can uncomment /* #define DEBUG_OPENPIC */ in this file and look for logs from above DPRINTFs when you run your SMP Linux kernel. If you don't see any of these in the log then this means this register is not used and the Mac likely does not use this but does the CPU resets through the GPIOs of the macio chip. I don't know if those are directly connected to the CPUs on the real machine or somehow cause the openpic PIR to be changed but connecting the CPU resets to the GPIO lines seems to be more likely and probably easier to do in QEMU as well. Maybe this PIR thing is what Motorola SoCs do to reset the cores within the SoC as comments on top of openpic.c says it was based on that. You could also check the openpic docs referenced in the comments to see how this should work or what PIR means at all. Maybe that would help understanding it. I don't know so I also don't understand but I'm too lazy to look up docs so I just keep guessing instead.
> >
> > Or I can check Linux source to see if this is different on e500. It seems linux/arch/powerpc/platforms/85xx/smp.c calls mpic_reset_core() to do the same that the Mac does with GPIOs and and in linux/arch/powerpc/sysdev/mpic.c it seems mpic_reset_core() is poking the PIR which now I guess means Processor Init Register maybe. So I think my guess is correct, currently QEMU is wired for e500 but that's not correct for the Mac which does this with GPIOs in macio instead so that should be fixed. The Linux sources is the proof for this theory.
> >
> > Regards,
> > BALATON Zoltan
>
> Thanks Balaton, I’m working on the PIR code in the Openpic.c to see if I can resolve some of the issues with resets of the additional cpus. The limit for qemu ppc seems to be 32 cores but Openbios only seems to read 20 of them. At any rate, if I can get 2 or 4 cores working things will be that much faster, I just like to see all those cores in the device tree. I’m just toying around with more than 2 cores because that is all a PowerMac G4 ever had anyway.
>
> On a side note, not unrelated I looked at my Dual CPU MDD PowerMac and found the GPIO has several nodes in the device tree, like 8 or 9 of them, I did not count. Anyways, it looks like only the top device pci/Mac-io/@50 is the GPIO for the CPUs and maybe some other stuff, and it has an extended gpio that looks like it may handle the other CPU or just some other system stuff, all the other GPIO entries in the deice tree below it on the Mac-io/ node say they are for audio.
>
> A rather complex setup for builtin audio if you ask me, but if I have too I’ll probe the main gpio@50 and see if I can find how the cpus are brought out of reset.
>
> Likely the code you pointed to is all we need to property reset the second cpu in qemu so that linux, OS 9, and OS X can bring it up and use it.
>
> OpenBIOS mailing list -- [e-mail]
> To unsubscribe send an email to [e-mail]

Openbios code for IRQ or interrupt handling?

[BALATON Zoltan]

On Thu, 20 Feb 2025, Jd Lyons wrote:
> Making some progress with spm as far as getting some useful debug info.
>
> I seem to be raising an exception state when Mac OS X 10.4.11 Kernel loads and tries to reset and wake the additional cores
>
> qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 255 is disabled
> qemu-system-ppc64-unsigned: info: Core0: openpic_update_irq: IRQ 255 is already inactive
> qemu-system-ppc64-unsigned: info: Core0: Set IVPR 255 to 0x80000000 -> 0x80000000
> qemu-system-ppc64-unsigned: info: Core0: openpic_gbl_write: addr 0x10e0 <= 000000ff
> qemu-system-ppc64-unsigned: info: Core0: openpic_gbl_write: addr 0x1020 <= 20000000
> qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: cpu 0 addr 0x80 <= 0x00000000
> qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: set CPU 0 ctpr to 0, raised 0 servicing 0
> qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: Lower OpenPIC INT output cpu 0 due to ctpr
> qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: cpu 1 addr 0x1080 <= 0x00000000
> qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: set CPU 1 ctpr to 0, raised 0 servicing 0
> qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: Lower OpenPIC INT output cpu 1 due to ctpr
> qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: cpu 2 addr 0x2080 <= 0x00000000
> qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: set CPU 2 ctpr to 0, raised 0 servicing 0
> qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: Lower OpenPIC INT output cpu 2 due to ctpr
> qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: cpu 3 addr 0x3080 <= 0x00000000
> qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: set CPU 3 ctpr to 0, raised 0 servicing 0
> qemu-system-ppc64-unsigned: info: Core0: openpic_cpu_write_internal: Lower OpenPIC INT output cpu 3 due to ctpr<—exception state starts here and terminal output ends after the kernel tries to enable the additional cores but accesses the non-existent L2 CR( SPR 1012 )

Is there anyting inbetween here and the logs below? It's hard to tell what 
happens if you don't include logs and the patches you're using.
> Raise exception at 00000000fff10698 => DSI (2) error=00
> Raise exception at 00000000fff17098 => ISI (3) error=40000000
> Raise exception at 00000000fff0ad08 => DSI (2) error=00
> Raise exception at 00000000fff171f4 => DSI (2) error=00
> Trying to read invalid spr 1012 (0x3f4) at 0000000000092884 <———————Here from the qemu log that we raise an exception state when the kernel tries to read the L2 cache cr

Do you get this same message when booting with only one CPU? I think 
accessing L2 cache control is not related to SMP so you could see this 
without -smp and if that works maybe it's not a problem. But it could be 
SMP needs something else with the cache that's not emulated and it crashes 
due to that. You'd have to check the CPU docs what this register does and 
see what the kernel tries to do then check what QEMU does and correct if 
needed. (And stick to -smp 2 at first, I'll ignore anything with more than 
2 CPUs from now on.)
> Raise exception at 00000000000af72c => SYSCALL (8) error=00
> syscall r0=0000000000007ff4 r3=0000000000000000 r4=0000000000000000 r5=0000000000000000 r6=0000000000000000 r7=0000000000000000 r8=0000000072696e67 nip=00000000000af72c

While syscall is called exception this is just how it's implemented on PPC 
CPUs, getting these are normal when executing the 'sc' opcode which is 
when something calls the kernel so seeing a lot of these just means the 
system is running and something accessing the kernel. Unfortunately it can 
flood the log and make it harder to spot the relevant info there so maybe 
you can filter it out in some way.

Regards,
BALATON Zoltan

Openbios code for IRQ or interrupt handling?

[BALATON Zoltan]

On Thu, 20 Feb 2025, Jd Lyons wrote:
> Thanks Balaton, I’m working on the PIR code in the Openpic.c to see if I 
> can resolve some of the issues with resets of the additional cpus. The

You don't have to change the PIR code in openpic. That's correct for e500. 
I just said you can verify if this register is written at all on the Mac 
by enabling the DPRINTFs and see if you see any logs. Likely you won't see 
any for the PIR reset bits because on the Mac the CPU resets are connected 
to GPIO instead so Linux pokes there not the openpic PIR which is how e500 
does it. So having the CPU resets connected to PIR in mac_newworld.c is 
probably code copied from e500 but it's not correct for Mac. You have to 
change that in mac_newworld.c to connect the CPU reset to the macio GPIO 
instead and openpic.c likely does not need patching at this point. I don't 
know how more detailed to explain this to get this through. There must be 
somebody on the list by now who could come up with a patch.
> limit for qemu ppc seems to be 32 cores but Openbios only seems to read 
> 20 of them. At any rate, if I can get 2 or 4 cores working things will 
> be that much faster, I just like to see all those cores in the device 
> tree. I’m just toying around with more than 2 cores because that is all 
> a PowerMac G4 ever had anyway.

Forget about these for a minute. Just stick to -smp 2 at first to make it 
simpler to do and debug. You won't be able to get more than 4 CPUs anyway 
according to the Linux source which says only that many GPIO lines exist 
so it won't even try more and that's also what Mac OS X would also 
support. Was there any PPC Mac with more than 4 CPU cores? If not then you 
would likely need to also patch the kernel for that so it's not something 
to try to do at first if you don't want to make your own job harder than 
it needs to be and not get distracted by trying to debug problems you 
would not get with -smp 2. Once you can get 2 CPUs working you can try 4 
and after that's working you can think about if there could be more but 
maybe you'll find that adding more CPUs won't make things faster beyond 4 
CPUs. But that's something to try later when it works with 2 CPUs already.

Regards,
BALATON Zoltan
> On a side note, not unrelated I looked at my Dual CPU MDD PowerMac and 
> found the GPIO has several nodes in the device tree, like 8 or 9 of 
> them, I did not count. Anyways, it looks like only the top device 
> pci/Mac-io/@50 is the GPIO for the CPUs and maybe some other stuff, and 
> it has an extended gpio that looks like it may handle the other CPU or 
> just some other system stuff, all the other GPIO entries in the deice 
> tree below it on the Mac-io/ node say they are for audio.
>
> A rather complex setup for builtin audio if you ask me, but if I have 
> too I’ll probe the main gpio@50 and see if I can find how the cpus are 
> brought out of reset.
>
> Likely the code you pointed to is all we need to property reset the 
> second cpu in qemu so that linux, OS 9, and OS X can bring it up and use 
> it.