Cc: Alexander Graf agraf@suse.de Signed-off-by: Andreas Färber andreas.faerber@web.de --- arch/ppc/qemu/ofmem.c | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/arch/ppc/qemu/ofmem.c b/arch/ppc/qemu/ofmem.c index 9c60841..e8b0b24 100644 --- a/arch/ppc/qemu/ofmem.c +++ b/arch/ppc/qemu/ofmem.c @@ -25,6 +25,12 @@
#define BIT(n) (1U<<(31-(n)))
+#ifdef __powerpc64__ +#define MTMSR "mtmsrd" +#else +#define MTMSR "mtmsr" +#endif + /* called from assembly */ extern void dsi_exception( void ); extern void isi_exception( void ); @@ -417,7 +423,7 @@ setup_mmu( unsigned long ramsize )
asm volatile("mfmsr %0" : "=r" (msr) : ); msr |= MSR_IR | MSR_DR; - asm volatile("mtmsr %0" :: "r" (msr) ); + asm volatile(MTMSR " %0" :: "r" (msr) ); }
void
On 16.11.2010, at 00:25, Andreas Färber wrote:
Cc: Alexander Graf agraf@suse.de Signed-off-by: Andreas Färber andreas.faerber@web.de
arch/ppc/qemu/ofmem.c | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/arch/ppc/qemu/ofmem.c b/arch/ppc/qemu/ofmem.c index 9c60841..e8b0b24 100644 --- a/arch/ppc/qemu/ofmem.c +++ b/arch/ppc/qemu/ofmem.c @@ -25,6 +25,12 @@
#define BIT(n) (1U<<(31-(n)))
+#ifdef __powerpc64__ +#define MTMSR "mtmsrd" +#else +#define MTMSR "mtmsr" +#endif
/* called from assembly */ extern void dsi_exception( void ); extern void isi_exception( void ); @@ -417,7 +423,7 @@ setup_mmu( unsigned long ramsize )
asm volatile("mfmsr %0" : "=r" (msr) : ); msr |= MSR_IR | MSR_DR;
- asm volatile("mtmsr %0" :: "r" (msr) );
- asm volatile(MTMSR " %0" :: "r" (msr) );
Is that the only occurence of mtmsr in all the code? Better replace all at once or you'll be chasing bugs later on :).
Alex
Am 16.11.2010 um 00:27 schrieb Alexander Graf:
On 16.11.2010, at 00:25, Andreas Färber wrote:
Cc: Alexander Graf agraf@suse.de Signed-off-by: Andreas Färber andreas.faerber@web.de
arch/ppc/qemu/ofmem.c | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/arch/ppc/qemu/ofmem.c b/arch/ppc/qemu/ofmem.c index 9c60841..e8b0b24 100644 --- a/arch/ppc/qemu/ofmem.c +++ b/arch/ppc/qemu/ofmem.c @@ -25,6 +25,12 @@
#define BIT(n) (1U<<(31-(n)))
+#ifdef __powerpc64__ +#define MTMSR "mtmsrd" +#else +#define MTMSR "mtmsr" +#endif
/* called from assembly */ extern void dsi_exception( void ); extern void isi_exception( void ); @@ -417,7 +423,7 @@ setup_mmu( unsigned long ramsize )
asm volatile("mfmsr %0" : "=r" (msr) : ); msr |= MSR_IR | MSR_DR;
- asm volatile("mtmsr %0" :: "r" (msr) );
- asm volatile(MTMSR " %0" :: "r" (msr) );
Is that the only occurence of mtmsr in all the code? Better replace all at once or you'll be chasing bugs later on :).
The only one in inline assembler. The question would be how to go about turning this into a header-capable macro. For simplicity I defined it as a string literal here, doesn't work for real assembler obviously.
Andreas
On 16.11.2010, at 00:30, Andreas Färber wrote:
Am 16.11.2010 um 00:27 schrieb Alexander Graf:
On 16.11.2010, at 00:25, Andreas Färber wrote:
Cc: Alexander Graf agraf@suse.de Signed-off-by: Andreas Färber andreas.faerber@web.de
arch/ppc/qemu/ofmem.c | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/arch/ppc/qemu/ofmem.c b/arch/ppc/qemu/ofmem.c index 9c60841..e8b0b24 100644 --- a/arch/ppc/qemu/ofmem.c +++ b/arch/ppc/qemu/ofmem.c @@ -25,6 +25,12 @@
#define BIT(n) (1U<<(31-(n)))
+#ifdef __powerpc64__ +#define MTMSR "mtmsrd" +#else +#define MTMSR "mtmsr" +#endif
/* called from assembly */ extern void dsi_exception( void ); extern void isi_exception( void ); @@ -417,7 +423,7 @@ setup_mmu( unsigned long ramsize )
asm volatile("mfmsr %0" : "=r" (msr) : ); msr |= MSR_IR | MSR_DR;
- asm volatile("mtmsr %0" :: "r" (msr) );
- asm volatile(MTMSR " %0" :: "r" (msr) );
Is that the only occurence of mtmsr in all the code? Better replace all at once or you'll be chasing bugs later on :).
The only one in inline assembler. The question would be how to go about turning this into a header-capable macro. For simplicity I defined it as a string literal here, doesn't work for real assembler obviously.
Real assembler needs a different define. I'd again suggest to stick to Linux nomenclatures:
#ifdef CONFIG_PPC_BOOK3S_64 #define RFI rfid #define MTMSRD(r) mtmsrd r #else #define RFI rfi #define MTMSRD(r) mtmsr r #endif
For C, please go with something like
static inline unsigned long mfmsr(void) { unsigned long msr; asm volatile("mfmsr %0" : "=r" (msr) : ); return msr; }
static inline void mtmsr(unsigned long msr) { #ifdef __powerpc64__ asm volatile("mtmsrd %0" :: "r" (msr) : ); #else asm volatile("mtmsr %0" :: "r" (msr) : ); #endif return msr; }
in a globally defined place and use that:
mtmsr(mfmsr() | MSR_IR | MSR_DR);
Alex
On ppc64 the mtmsr instruction only sets the low 32 bits of the MSR. mtmsrd must be used to set the high bits such as Sixty-Four Bit Mode as well.
v2: * Introduce MTMSRD macro as seen on Linux, suggested by Alex. * Introduce inline functions {mfmsr,mtmsr}, suggested by Alex.
Cc: Alexander Graf agraf@suse.de Signed-off-by: Andreas Färber andreas.faerber@web.de --- Alex, mind to add your SoB for the functions? Thanks.
arch/ppc/qemu/ofmem.c | 6 ++---- include/arch/ppc/asmdefs.h | 2 ++ include/arch/ppc/processor.h | 20 ++++++++++++++++++++ 3 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/arch/ppc/qemu/ofmem.c b/arch/ppc/qemu/ofmem.c index 6f2b86d..ac3e049 100644 --- a/arch/ppc/qemu/ofmem.c +++ b/arch/ppc/qemu/ofmem.c @@ -396,7 +396,7 @@ void setup_mmu( unsigned long ramsize ) { ofmem_t *ofmem; - unsigned long sdr1, sr_base, msr; + unsigned long sdr1, sr_base; unsigned long hash_base; unsigned long hash_mask = ~0x000fffffUL; /* alignment for ppc64 */ int i; @@ -428,9 +428,7 @@ setup_mmu( unsigned long ramsize )
/* Enable MMU */
- asm volatile("mfmsr %0" : "=r" (msr) : ); - msr |= MSR_IR | MSR_DR; - asm volatile("mtmsr %0" :: "r" (msr) ); + mtmsr(mfmsr() | MSR_IR | MSR_DR); }
void diff --git a/include/arch/ppc/asmdefs.h b/include/arch/ppc/asmdefs.h index 4e22156..51570ea 100644 --- a/include/arch/ppc/asmdefs.h +++ b/include/arch/ppc/asmdefs.h @@ -90,8 +90,10 @@
#ifdef __powerpc64__ #define RFI rfid +#define MTMSRD(r) mtmsrd r #else #define RFI rfi +#define MTMSRD(r) mtmsr r #endif
#ifndef __darwin__ diff --git a/include/arch/ppc/processor.h b/include/arch/ppc/processor.h index 3afb03f..c7d5be6 100644 --- a/include/arch/ppc/processor.h +++ b/include/arch/ppc/processor.h @@ -403,8 +403,28 @@
/* C helpers */
+#ifndef __ASSEMBLER__ + #define __stringify_1(x) #x #define __stringify(x) __stringify_1(x) #define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
+static inline unsigned long mfmsr(void) +{ + unsigned long msr; + asm volatile("mfmsr %0" : "=r" (msr)); + return msr; +} + +static inline void mtmsr(unsigned long msr) +{ +#ifdef __powerpc64__ + asm volatile("mtmsrd %0" :: "r" (msr)); +#else + asm volatile("mtmsr %0" :: "r" (msr)); +#endif +} + +#endif /* !__ASSEMBLER__ */ + #endif /* _H_PROCESSOR */
On 21.11.2010, at 01:49, Andreas Färber wrote:
On ppc64 the mtmsr instruction only sets the low 32 bits of the MSR. mtmsrd must be used to set the high bits such as Sixty-Four Bit Mode as well.
v2:
- Introduce MTMSRD macro as seen on Linux, suggested by Alex.
- Introduce inline functions {mfmsr,mtmsr}, suggested by Alex.
Cc: Alexander Graf agraf@suse.de Signed-off-by: Andreas Färber andreas.faerber@web.de
Signed-off-by: Alexander Graf agraf@suse.de
Alex
Am 21.11.2010 um 02:14 schrieb Alexander Graf:
On 21.11.2010, at 01:49, Andreas Färber wrote:
On ppc64 the mtmsr instruction only sets the low 32 bits of the MSR. mtmsrd must be used to set the high bits such as Sixty-Four Bit Mode as well.
v2:
- Introduce MTMSRD macro as seen on Linux, suggested by Alex.
- Introduce inline functions {mfmsr,mtmsr}, suggested by Alex.
Cc: Alexander Graf agraf@suse.de Signed-off-by: Andreas Färber andreas.faerber@web.de
Signed-off-by: Alexander Graf agraf@suse.de
Thanks, applied as r963.
Andreas
-
Alexander Graf -
Andreas Färber