An error in the logic related to FREE_BASE meant that instead of mapping the RAM for the loader at load-base, a small section was being mapped at the bottom of RAM instead.
Fix this by deferring the mapping of the load-base RAM to arch_init() when we can access the load-base variable and map 8MB RAM with a 1:1 phys to virt mapping.
Signed-off-by: Mark Cave-Ayland mark.cave-ayland@ilande.co.uk --- arch/ppc/qemu/init.c | 8 ++++++++ arch/ppc/qemu/ofmem.c | 12 ------------ 2 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/arch/ppc/qemu/init.c b/arch/ppc/qemu/init.c index af15682..f5acf87 100644 --- a/arch/ppc/qemu/init.c +++ b/arch/ppc/qemu/init.c @@ -844,6 +844,7 @@ arch_of_init(void) uint32_t temp = 0; char *boot_device; ofmem_t *ofmem = ofmem_arch_get_private(); + ucell load_base;
openbios_init(); modules_init(); @@ -1105,4 +1106,11 @@ arch_of_init(void)
bind_func("platform-boot", boot); bind_func("(arch-go)", arch_go); + + /* Allocate 8MB memory at load-base */ + fword("load-base"); + load_base = POP(); + ofmem_claim_phys(load_base, 0x800000, 0); + ofmem_claim_virt(load_base, 0x800000, 0); + ofmem_map(load_base, load_base, 0x800000, 0); } diff --git a/arch/ppc/qemu/ofmem.c b/arch/ppc/qemu/ofmem.c index 7b8ced0..7a78a1e 100644 --- a/arch/ppc/qemu/ofmem.c +++ b/arch/ppc/qemu/ofmem.c @@ -46,7 +46,6 @@ extern void setup_mmu(unsigned long code_base); * */
-#define FREE_BASE 0x00004000UL #define OF_CODE_START 0xfff00000UL #define OF_CODE_SIZE 0x00100000 #define IO_BASE 0x80000000UL @@ -81,12 +80,6 @@ get_ram_top(void) return get_hash_base() - (32 + 64 + 64) * 1024 - OFMEM_SIZE; }
-static unsigned long -get_ram_bottom(void) -{ - return FREE_BASE; -} - static unsigned long get_heap_top(void) { return get_hash_base() - (32 + 64 + 64) * 1024; @@ -578,11 +571,6 @@ ofmem_init(void) { ofmem_t *ofmem = ofmem_arch_get_private();
- /* Map the memory (don't map page 0 to allow catching of NULL dereferences) */ - ofmem_claim_phys(PAGE_SIZE, get_ram_bottom() - PAGE_SIZE, 0); - ofmem_claim_virt(PAGE_SIZE, get_ram_bottom() - PAGE_SIZE, 0); - ofmem_map(PAGE_SIZE, PAGE_SIZE, get_ram_bottom() - PAGE_SIZE, 0); - /* Mark the first page as non-free */ ofmem_claim_phys(0, PAGE_SIZE, 0); ofmem_claim_virt(0, PAGE_SIZE, 0);
For reasons lost in the history of time, the SPARC64 endian accessors were given the opposite names to their function i.e. out_le32() would use a standard load whilst out_be32() would use a little-endian load. Switch them around so that their implementation matches their name (and also that of all other architectures).
Note that since the references in the inb/inw/inl and outb/outw/outl wrappers are also swapped around then these accessors for legacy ioports (i.e. little endian) will still behave exactly the same as before.
Signed-off-by: Mark Cave-Ayland mark.cave-ayland@ilande.co.uk --- include/arch/sparc64/io.h | 33 ++++++++++++++++----------------- include/arch/sparc64/pci.h | 8 ++++---- 2 files changed, 20 insertions(+), 21 deletions(-)
diff --git a/include/arch/sparc64/io.h b/include/arch/sparc64/io.h index 0f1a732..2812793 100644 --- a/include/arch/sparc64/io.h +++ b/include/arch/sparc64/io.h @@ -30,14 +30,13 @@ extern unsigned long isa_io_base;
#define inb(port) in_8((uint8_t *)((port)+isa_io_base)) #define outb(val, port) out_8((uint8_t *)((port)+isa_io_base), (val)) -#define inw(port) in_be16((uint16_t *)((port)+isa_io_base)) -#define outw(val, port) out_be16((uint16_t *)((port)+isa_io_base), (val)) -#define inl(port) in_be32((uint32_t *)((port)+isa_io_base)) -#define outl(val, port) out_be32((uint32_t *)((port)+isa_io_base), (val)) +#define inw(port) in_le16((uint16_t *)((port)+isa_io_base)) +#define outw(val, port) out_le16((uint16_t *)((port)+isa_io_base), (val)) +#define inl(port) in_le32((uint32_t *)((port)+isa_io_base)) +#define outl(val, port) out_le32((uint32_t *)((port)+isa_io_base), (val))
/* * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. - * On Sparc64, BE versions must swap bytes using LE access ASI. */ static inline int in_8(volatile unsigned char *addr) { @@ -59,7 +58,7 @@ static inline void out_8(volatile unsigned char *addr, int val) : "memory"); }
-static inline int in_le16(volatile unsigned short *addr) +static inline int in_be16(volatile unsigned short *addr) { int ret;
@@ -71,7 +70,7 @@ static inline int in_le16(volatile unsigned short *addr) return ret; }
-static inline int in_be16(volatile unsigned short *addr) +static inline int in_le16(volatile unsigned short *addr) { int ret;
@@ -83,7 +82,7 @@ static inline int in_be16(volatile unsigned short *addr) return ret; }
-static inline void out_le16(volatile unsigned short *addr, int val) +static inline void out_be16(volatile unsigned short *addr, int val) {
__asm__ __volatile__("stha %0, [%1] %2\n\t" @@ -92,7 +91,7 @@ static inline void out_le16(volatile unsigned short *addr, int val) : "memory"); }
-static inline void out_be16(volatile unsigned short *addr, int val) +static inline void out_le16(volatile unsigned short *addr, int val) { __asm__ __volatile__("stha %0, [%1] %2\n\t" : @@ -100,7 +99,7 @@ static inline void out_be16(volatile unsigned short *addr, int val) : "memory"); }
-static inline unsigned in_le32(volatile unsigned *addr) +static inline unsigned in_be32(volatile unsigned *addr) { unsigned ret;
@@ -112,7 +111,7 @@ static inline unsigned in_le32(volatile unsigned *addr) return ret; }
-static inline unsigned in_be32(volatile unsigned *addr) +static inline unsigned in_le32(volatile unsigned *addr) { unsigned ret;
@@ -123,7 +122,7 @@ static inline unsigned in_be32(volatile unsigned *addr) return ret; }
-static inline void out_le32(volatile unsigned *addr, int val) +static inline void out_be32(volatile unsigned *addr, int val) { __asm__ __volatile__("stwa %0, [%1] %2\n\t" : @@ -131,7 +130,7 @@ static inline void out_le32(volatile unsigned *addr, int val) : "memory"); }
-static inline void out_be32(volatile unsigned *addr, int val) +static inline void out_le32(volatile unsigned *addr, int val) { __asm__ __volatile__("stwa %0, [%1] %2\n\t" : @@ -144,7 +143,7 @@ static inline void _insw_ns(volatile uint16_t * port, void *buf, int ns) uint16_t *b = (uint16_t *) buf;
while (ns > 0) { - *b++ = in_le16(port); + *b++ = in_be16(port); ns--; } } @@ -155,7 +154,7 @@ static inline void _outsw_ns(volatile uint16_t * port, const void *buf, uint16_t *b = (uint16_t *) buf;
while (ns > 0) { - out_le16(port, *b++); + out_be16(port, *b++); ns--; } } @@ -165,7 +164,7 @@ static inline void _insw(volatile uint16_t * port, void *buf, int ns) uint16_t *b = (uint16_t *) buf;
while (ns > 0) { - *b++ = in_be16(port); + *b++ = in_le16(port); ns--; } } @@ -176,7 +175,7 @@ static inline void _outsw(volatile uint16_t * port, const void *buf, uint16_t *b = (uint16_t *) buf;
while (ns > 0) { - out_be16(port, *b++); + out_le16(port, *b++); ns--; } } diff --git a/include/arch/sparc64/pci.h b/include/arch/sparc64/pci.h index c7509af..2389a5d 100644 --- a/include/arch/sparc64/pci.h +++ b/include/arch/sparc64/pci.h @@ -35,14 +35,14 @@ static inline uint8_t pci_config_read8(pci_addr dev, uint8_t reg) static inline uint16_t pci_config_read16(pci_addr dev, uint8_t reg) { uint16_t res; - res = in_be16((uint16_t *)(PCI_CONFIG(dev) + reg)); + res = in_le16((uint16_t *)(PCI_CONFIG(dev) + reg)); return res; }
static inline uint32_t pci_config_read32(pci_addr dev, uint8_t reg) { uint32_t res; - res = in_be32((uint32_t *)(PCI_CONFIG(dev) + reg)); + res = in_le32((uint32_t *)(PCI_CONFIG(dev) + reg)); return res; }
@@ -53,12 +53,12 @@ static inline void pci_config_write8(pci_addr dev, uint8_t reg, uint8_t val)
static inline void pci_config_write16(pci_addr dev, uint8_t reg, uint16_t val) { - out_be16((uint16_t *)(PCI_CONFIG(dev) + reg), val); + out_le16((uint16_t *)(PCI_CONFIG(dev) + reg), val); }
static inline void pci_config_write32(pci_addr dev, uint8_t reg, uint32_t val) { - out_be32((uint32_t *)(PCI_CONFIG(dev) + reg), val); + out_le32((uint32_t *)(PCI_CONFIG(dev) + reg), val); } #else /* !PCI_CONFIG_1 */ #error PCI Configuration Mechanism is not specified or implemented
On 26/08/18 15:45, Mark Cave-Ayland wrote:
For reasons lost in the history of time, the SPARC64 endian accessors were given the opposite names to their function i.e. out_le32() would use a standard load whilst out_be32() would use a little-endian load. Switch them around so that their implementation matches their name (and also that of all other architectures).
Note that since the references in the inb/inw/inl and outb/outw/outl wrappers are also swapped around then these accessors for legacy ioports (i.e. little endian) will still behave exactly the same as before.
Signed-off-by: Mark Cave-Ayland mark.cave-ayland@ilande.co.uk
include/arch/sparc64/io.h | 33 ++++++++++++++++----------------- include/arch/sparc64/pci.h | 8 ++++---- 2 files changed, 20 insertions(+), 21 deletions(-)
diff --git a/include/arch/sparc64/io.h b/include/arch/sparc64/io.h index 0f1a732..2812793 100644 --- a/include/arch/sparc64/io.h +++ b/include/arch/sparc64/io.h @@ -30,14 +30,13 @@ extern unsigned long isa_io_base;
#define inb(port) in_8((uint8_t *)((port)+isa_io_base)) #define outb(val, port) out_8((uint8_t *)((port)+isa_io_base), (val)) -#define inw(port) in_be16((uint16_t *)((port)+isa_io_base)) -#define outw(val, port) out_be16((uint16_t *)((port)+isa_io_base), (val)) -#define inl(port) in_be32((uint32_t *)((port)+isa_io_base)) -#define outl(val, port) out_be32((uint32_t *)((port)+isa_io_base), (val)) +#define inw(port) in_le16((uint16_t *)((port)+isa_io_base)) +#define outw(val, port) out_le16((uint16_t *)((port)+isa_io_base), (val)) +#define inl(port) in_le32((uint32_t *)((port)+isa_io_base)) +#define outl(val, port) out_le32((uint32_t *)((port)+isa_io_base), (val))
/*
- 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
*/
- On Sparc64, BE versions must swap bytes using LE access ASI.
static inline int in_8(volatile unsigned char *addr) { @@ -59,7 +58,7 @@ static inline void out_8(volatile unsigned char *addr, int val) : "memory"); }
-static inline int in_le16(volatile unsigned short *addr) +static inline int in_be16(volatile unsigned short *addr) { int ret;
@@ -71,7 +70,7 @@ static inline int in_le16(volatile unsigned short *addr) return ret; }
-static inline int in_be16(volatile unsigned short *addr) +static inline int in_le16(volatile unsigned short *addr) { int ret;
@@ -83,7 +82,7 @@ static inline int in_be16(volatile unsigned short *addr) return ret; }
-static inline void out_le16(volatile unsigned short *addr, int val) +static inline void out_be16(volatile unsigned short *addr, int val) {
__asm__ __volatile__("stha %0, [%1] %2\n\t"@@ -92,7 +91,7 @@ static inline void out_le16(volatile unsigned short *addr, int val) : "memory"); }
-static inline void out_be16(volatile unsigned short *addr, int val) +static inline void out_le16(volatile unsigned short *addr, int val) { __asm__ __volatile__("stha %0, [%1] %2\n\t" : @@ -100,7 +99,7 @@ static inline void out_be16(volatile unsigned short *addr, int val) : "memory"); }
-static inline unsigned in_le32(volatile unsigned *addr) +static inline unsigned in_be32(volatile unsigned *addr) { unsigned ret;
@@ -112,7 +111,7 @@ static inline unsigned in_le32(volatile unsigned *addr) return ret; }
-static inline unsigned in_be32(volatile unsigned *addr) +static inline unsigned in_le32(volatile unsigned *addr) { unsigned ret;
@@ -123,7 +122,7 @@ static inline unsigned in_be32(volatile unsigned *addr) return ret; }
-static inline void out_le32(volatile unsigned *addr, int val) +static inline void out_be32(volatile unsigned *addr, int val) { __asm__ __volatile__("stwa %0, [%1] %2\n\t" : @@ -131,7 +130,7 @@ static inline void out_le32(volatile unsigned *addr, int val) : "memory"); }
-static inline void out_be32(volatile unsigned *addr, int val) +static inline void out_le32(volatile unsigned *addr, int val) { __asm__ __volatile__("stwa %0, [%1] %2\n\t" : @@ -144,7 +143,7 @@ static inline void _insw_ns(volatile uint16_t * port, void *buf, int ns) uint16_t *b = (uint16_t *) buf;
while (ns > 0) {
*b++ = in_le16(port);
*b++ = in_be16(port);} @@ -155,7 +154,7 @@ static inline void _outsw_ns(volatile uint16_t * port, const void *buf, uint16_t *b = (uint16_t *) buf;
while (ns > 0) {
out_le16(port, *b++);
out_be16(port, *b++);} @@ -165,7 +164,7 @@ static inline void _insw(volatile uint16_t * port, void *buf, int ns) uint16_t *b = (uint16_t *) buf;
while (ns > 0) {
*b++ = in_be16(port);
*b++ = in_le16(port);} @@ -176,7 +175,7 @@ static inline void _outsw(volatile uint16_t * port, const void *buf, uint16_t *b = (uint16_t *) buf;
while (ns > 0) {
out_be16(port, *b++);
out_le16(port, *b++);} diff --git a/include/arch/sparc64/pci.h b/include/arch/sparc64/pci.h index c7509af..2389a5d 100644 --- a/include/arch/sparc64/pci.h +++ b/include/arch/sparc64/pci.h @@ -35,14 +35,14 @@ static inline uint8_t pci_config_read8(pci_addr dev, uint8_t reg) static inline uint16_t pci_config_read16(pci_addr dev, uint8_t reg) { uint16_t res;
res = in_be16((uint16_t *)(PCI_CONFIG(dev) + reg));
res = in_le16((uint16_t *)(PCI_CONFIG(dev) + reg));}
static inline uint32_t pci_config_read32(pci_addr dev, uint8_t reg) { uint32_t res;
res = in_be32((uint32_t *)(PCI_CONFIG(dev) + reg));
res = in_le32((uint32_t *)(PCI_CONFIG(dev) + reg));}
@@ -53,12 +53,12 @@ static inline void pci_config_write8(pci_addr dev, uint8_t reg, uint8_t val)
static inline void pci_config_write16(pci_addr dev, uint8_t reg, uint16_t val) {
out_be16((uint16_t *)(PCI_CONFIG(dev) + reg), val);
out_le16((uint16_t *)(PCI_CONFIG(dev) + reg), val);}
static inline void pci_config_write32(pci_addr dev, uint8_t reg, uint32_t val) {
out_be32((uint32_t *)(PCI_CONFIG(dev) + reg), val);
out_le32((uint32_t *)(PCI_CONFIG(dev) + reg), val);} #else /* !PCI_CONFIG_1 */ #error PCI Configuration Mechanism is not specified or implemented
Applied to master.
ATB,
Mark.
On 26/08/18 15:45, Mark Cave-Ayland wrote:
An error in the logic related to FREE_BASE meant that instead of mapping the RAM for the loader at load-base, a small section was being mapped at the bottom of RAM instead.
Fix this by deferring the mapping of the load-base RAM to arch_init() when we can access the load-base variable and map 8MB RAM with a 1:1 phys to virt mapping.
Signed-off-by: Mark Cave-Ayland mark.cave-ayland@ilande.co.uk
arch/ppc/qemu/init.c | 8 ++++++++ arch/ppc/qemu/ofmem.c | 12 ------------ 2 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/arch/ppc/qemu/init.c b/arch/ppc/qemu/init.c index af15682..f5acf87 100644 --- a/arch/ppc/qemu/init.c +++ b/arch/ppc/qemu/init.c @@ -844,6 +844,7 @@ arch_of_init(void) uint32_t temp = 0; char *boot_device; ofmem_t *ofmem = ofmem_arch_get_private();
ucell load_base;
openbios_init(); modules_init();
@@ -1105,4 +1106,11 @@ arch_of_init(void)
bind_func("platform-boot", boot); bind_func("(arch-go)", arch_go);
- /* Allocate 8MB memory at load-base */
- fword("load-base");
- load_base = POP();
- ofmem_claim_phys(load_base, 0x800000, 0);
- ofmem_claim_virt(load_base, 0x800000, 0);
- ofmem_map(load_base, load_base, 0x800000, 0);
} diff --git a/arch/ppc/qemu/ofmem.c b/arch/ppc/qemu/ofmem.c index 7b8ced0..7a78a1e 100644 --- a/arch/ppc/qemu/ofmem.c +++ b/arch/ppc/qemu/ofmem.c @@ -46,7 +46,6 @@ extern void setup_mmu(unsigned long code_base);
*/
-#define FREE_BASE 0x00004000UL #define OF_CODE_START 0xfff00000UL #define OF_CODE_SIZE 0x00100000 #define IO_BASE 0x80000000UL @@ -81,12 +80,6 @@ get_ram_top(void) return get_hash_base() - (32 + 64 + 64) * 1024 - OFMEM_SIZE; }
-static unsigned long -get_ram_bottom(void) -{
- return FREE_BASE;
-}
static unsigned long get_heap_top(void) { return get_hash_base() - (32 + 64 + 64) * 1024; @@ -578,11 +571,6 @@ ofmem_init(void) { ofmem_t *ofmem = ofmem_arch_get_private();
- /* Map the memory (don't map page 0 to allow catching of NULL dereferences) */
- ofmem_claim_phys(PAGE_SIZE, get_ram_bottom() - PAGE_SIZE, 0);
- ofmem_claim_virt(PAGE_SIZE, get_ram_bottom() - PAGE_SIZE, 0);
- ofmem_map(PAGE_SIZE, PAGE_SIZE, get_ram_bottom() - PAGE_SIZE, 0);
- /* Mark the first page as non-free */ ofmem_claim_phys(0, PAGE_SIZE, 0); ofmem_claim_virt(0, PAGE_SIZE, 0);
Applied to master.
ATB,
Mark.
-
Mark Cave-Ayland