Ronald G Minnich rminnich@lanl.gov writes:
Ron unless you have something better I'd suggest using one of the upcoming dual Itanium/P4 chipsets as a starting point. Then you could be certain the chipset worked before on x86 before trying to reverse engineer the cpu initialization for the Itanium...
do we have a vendor name yet?
I have seen reports that both Intel and IBM are working on chipsets that will support that. I think the reports were talking many way SMP but possibly that is because where Itanium is positioned. This looks like it may be in the McKinley time frame. I have a strange hunch that McKinley will be bus compatible with the P4. This is what I am picking up through osmosis reading the reviews.
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I was just at LinuxWorld in SF and Intel had a running Itanium box in what looked like a compactPCI chassis. They said it was a development platform and was named 'bluebox'.
Don't know about the chipset, tho'.
Chris.
On 29 Aug 2001, Eric W. Biederman wrote:
Ronald G Minnich rminnich@lanl.gov writes:
Ron unless you have something better I'd suggest using one of the upcoming dual Itanium/P4 chipsets as a starting point. Then you could be certain the chipset worked before on x86 before trying to reverse engineer the cpu initialization for the Itanium...
do we have a vendor name yet?
I have seen reports that both Intel and IBM are working on chipsets that will support that. I think the reports were talking many way SMP but possibly that is because where Itanium is positioned. This looks like it may be in the McKinley time frame. I have a strange hunch that McKinley will be bus compatible with the P4. This is what I am picking up through osmosis reading the reviews.
Eric
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(Slightly OT speculation...)
Date: 29 Aug 2001 12:22:23 -0600 From: Eric W. Biederman ebiederman@lnxi.com
I have seen reports that both Intel and IBM are working on chipsets that will support that. I think the reports were talking many way SMP but possibly that is because where Itanium is positioned. This
I'd have to dig up the article, but I recall a ComputerWorld tidbit on IBM planning 32-way SMP, IIRC. I probably should post that link.
looks like it may be in the McKinley time frame. I have a strange hunch that McKinley will be bus compatible with the P4. This is what I am picking up through osmosis reading the reviews.
I suppose that this makes sense. IMHO, the P4 chip is a disaster... it would make sense for Intel to get $$$ from the "bleeding edge" crowd who wants the latest-and-not-so-greatest, helping to get the new bus technology in volume production.
Eddy
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Sorry to respond to my own post...
Date: Thu, 30 Aug 2001 01:44:13 +0000 (GMT) From: E.B. Dreger eddy@everquick.net
Date: 29 Aug 2001 12:22:23 -0600 From: Eric W. Biederman ebiederman@lnxi.com
I have seen reports that both Intel and IBM are working on chipsets that will support that. I think the reports were talking many way SMP but possibly that is because where Itanium is positioned. This
I'd have to dig up the article, but I recall a ComputerWorld tidbit on IBM planning 32-way SMP, IIRC. I probably should post that link.
http://computerworld.com/nlt/1%2C3590%2CNAV47_STO63083_NLTPM%2C00.html
In summary:
* IBM "Summit" chipset * 16-way, _not_ 32-way like I thought * Can run as multiple shared-resource machines.
Eddy
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