Author: wmb Date: 2007-04-25 09:18:07 +0200 (Wed, 25 Apr 2007) New Revision: 321
Modified: cpu/x86/pc/olpc/fw.bth cpu/x86/pc/olpc/rmstart.fth cpu/x86/pc/olpc/romreset.bth Log: OLPC memory init: a) Added workaround for LX errata 34 b) Changed LX memory timings according to calculations by John Watlington and Tom Sylla c) Added a facility to temporarily test new timings by setting values in CMOS RAM.
Modified: cpu/x86/pc/olpc/fw.bth =================================================================== --- cpu/x86/pc/olpc/fw.bth 2007-04-25 07:07:59 UTC (rev 320) +++ cpu/x86/pc/olpc/fw.bth 2007-04-25 07:18:07 UTC (rev 321) @@ -453,6 +453,12 @@ [then] ;
+: set-mc ( 19-val 1a-val -- ) + lbsplit h# 66 h# 69 do i cmos! -1 +loop + lbsplit h# 62 h# 65 do i cmos! -1 +loop + 1 h# 61 cmos! 1 h# 60 cmos! +; + : interpreter-init ( -- ) hex warning on
Modified: cpu/x86/pc/olpc/rmstart.fth =================================================================== --- cpu/x86/pc/olpc/rmstart.fth 2007-04-25 07:07:59 UTC (rev 320) +++ cpu/x86/pc/olpc/rmstart.fth 2007-04-25 07:18:07 UTC (rev 321) @@ -139,12 +139,20 @@ h# 0017 # cx mov rdmsr \ Read CHIP_REVID h# 0014 # cx mov \ Restore RSTPLL MSR number h# 30 # al cmp >= if \ LX CPU - rdmsr \ Get base MSR value with divisors - op: h# 04de.0000 # ax or \ Set the startup time (de) and breadcrumb (4) - op: h# 0000.03d9 # dx mov \ PLL value for 133 MB clk, 433 CPU -\ op: h# 0000.04d9 # dx mov \ PLL value for 167 MB clk, 433 CPU + h# 60 # al mov al h# 70 # out h# 71 # al in \ Read CMOS 0x60 + al al test 0= if + rdmsr \ Get base MSR value with divisors + op: h# 04de.0000 # ax or \ Set the startup time (de) and breadcrumb (4) + op: h# 0000.04d9 # dx mov \ PLL value for 133 MB clk, 433 CPU + else + al dec al h# 71 # out \ Decrement safety counter + rdmsr \ Get base MSR value with divisors + op: h# 04de.0000 # ax or \ Set the startup time (de) and breadcrumb (4) + op: h# 0000.04d9 # dx mov \ PLL value for 167 MB clk, 433 CPU + then wrmsr \ Put in the base value op: h# 0000.1800 invert # ax and \ Turn off the BYPASS bits + else \ GX CPU op: dx dx xor \ Clear high bits op: h# 04de.0000 # ax mov \ Low MSR bits
Modified: cpu/x86/pc/olpc/romreset.bth =================================================================== --- cpu/x86/pc/olpc/romreset.bth 2007-04-25 07:07:59 UTC (rev 320) +++ cpu/x86/pc/olpc/romreset.bth 2007-04-25 07:18:07 UTC (rev 321) @@ -137,20 +137,53 @@ 00000106.83104104. 00001983 set-msr \ Memory delay values 00000000.00000001. 00001980 set-msr \ Enable memory delays
- 18000100.3b8332a3. 20000019 set-msr + h# 61 # al mov al h# 70 # out h# 71 # al in \ Read CMOS 0x61 + al al test 0= if + 18000100.6a7332a0. 20000019 set-msr
- \ The RAM controller is now set up + \ The RAM controller is now set up
- \ Init the SDRAMs - \ sdram_enable,src/northbridge/amd/gx2/raminit.c + \ Init the SDRAMs + \ sdram_enable,src/northbridge/amd/gx2/raminit.c
- \ Clock gating for PMode - \ Clocks always on in mode 1, hardware gating in mode 0 -\ 20002004 rmsr 4 bitclr 1 bitset 20002004 wmsr \ GX p 199 - 1. 20002004 set-msr \ GX p 199 + \ Clock gating for PMode + \ Clocks always on in mode 1, hardware gating in mode 0 + \ 20002004 rmsr 4 bitclr 1 bitset 20002004 wmsr \ GX p 199 + 1. 20002004 set-msr \ GX p 199
- \ Delay on exit from power mode 1, use unbuffered RAM - 140dd101. 2000001a set-msr \ MC_CF1017_DATA LX p 231 + \ Delay on exit from power mode 1, use unbuffered RAM + 130cd801. 2000001a set-msr \ MC_CF1017_DATA LX p 231 + else + al dec al h# 71 # out \ Decrement safety counter + + h# 64 # al mov al h# 70 # out h# 71 # al in al bl mov + h# 65 # al mov al h# 70 # out h# 71 # al in al bh mov + d# 16 # bx shl + h# 62 # al mov al h# 70 # out h# 71 # al in al bl mov + h# 63 # al mov al h# 70 # out h# 71 # al in al bh mov + + h# 18000100 # dx mov bx ax mov h# 20000019 wmsr + + \ The RAM controller is now set up + + \ Init the SDRAMs + \ sdram_enable,src/northbridge/amd/gx2/raminit.c + + \ Clock gating for PMode + \ Clocks always on in mode 1, hardware gating in mode 0 + \ 20002004 rmsr 4 bitclr 1 bitset 20002004 wmsr \ GX p 199 + 1. 20002004 set-msr \ GX p 199 + + \ Delay on exit from power mode 1, use unbuffered RAM + h# 68 # al mov al h# 70 # out h# 71 # al in al bl mov + h# 69 # al mov al h# 70 # out h# 71 # al in al bh mov + d# 16 # bx shl + h# 66 # al mov al h# 70 # out h# 71 # al in al bl mov + h# 67 # al mov al h# 70 # out h# 71 # al in al bh mov + + dx dx xor bx ax mov 2000001a wmsr \ MC_CF1017_DATA LX p 231 + then + 00000200.00000000. 20000020 set-msr \ Power mode entry and exit delays
\ Unmask CKE1 and CKE0 @@ -292,6 +325,15 @@
fload ${BP}/cpu/x86/pc/olpc/draminit.fth
+ \ Last-minute check for LX erratum 34 - reset if the DLL didn't start correctly + h# 4c000017 rmsr h# 10 bitand 0<> if \ LX branch + h# 4c00000f rmsr h# 7ff bitclr h# 4 bitset h# 4c00000f wmsr \ Set DLL_OV + h# 4c00000f rmsr h# 7ff # ax and h# 104 # ax cmp = if \ Check the result + \ The value 104 indicates that the DLL did not start, so we must reset + 1. 5140.0017 set-msr + then + then + \ Now we can use the stack and do conventional subroutine calls
h# 1f # al mov al h# 80 # out