Author: afaerber Date: Sun Feb 13 21:54:47 2011 New Revision: 1029 URL: http://tracker.coreboot.org/trac/openbios/changeset/1029
Log: ppc64: Re-enable SF bit after returning from ELF binary
When returning from the binary, enable Sixty-Four Bit Mode. Leave it disabled on entry, as enabling it breaks multiple guests.
Signed-off-by: Andreas Färber andreas.faerber@web.de
Modified: trunk/openbios-devel/arch/ppc/qemu/start.S trunk/openbios-devel/include/arch/ppc/processor.h
Modified: trunk/openbios-devel/arch/ppc/qemu/start.S ============================================================================== --- trunk/openbios-devel/arch/ppc/qemu/start.S Sun Feb 13 21:31:14 2011 (r1028) +++ trunk/openbios-devel/arch/ppc/qemu/start.S Sun Feb 13 21:54:47 2011 (r1029) @@ -494,6 +494,11 @@ MTMSRD(r0) blrl
+#ifdef CONFIG_PPC64 + /* Restore SF bit */ + LOAD_REG_IMMEDIATE(r0, MSR_SF | MSR_FP | MSR_ME | MSR_DR | MSR_IR) + MTMSRD(r0) +#endif LOAD_REG_IMMEDIATE(r8, saved_stack) // restore stack pointer mr r1,r8 PPC_LL r0, (STACKFRAME_MINSIZE + PPC_LR_STKOFF)(r1)
Modified: trunk/openbios-devel/include/arch/ppc/processor.h ============================================================================== --- trunk/openbios-devel/include/arch/ppc/processor.h Sun Feb 13 21:31:14 2011 (r1028) +++ trunk/openbios-devel/include/arch/ppc/processor.h Sun Feb 13 21:54:47 2011 (r1029) @@ -40,6 +40,8 @@
#ifndef MSR_VEC
+#define MSR_SF (1 << 63) /* Sixty-Four Bit Mode */ + #define MSR_VEC (1<<25) /* 6: Enable AltiVec */ #define MSR_POW (1<<18) /* 13: Enable Power Management */ #define MSR_TGPR (1<<17) /* 14: TLB Update registers in use */