On Sat, 22 Feb 2025, Jd Lyons wrote:
I did not see your patch until I had already hacked in some code to read the level register just to see if my trace of macio* would log the reads.
It seem to me the state of the level registers should not be zero at boot, that Linux would read the level registers first to we the state of the gpio so it would know what registers to write to when it tries to kick the second cpu?
No, in linux/arch/powerpc/platforms/powermac/feature.c::core99_reset_cpu() it just does
(void)MACIO_IN8(reset_io);
which does a read discarding the result so maybe this is just needed for the chip to update the value or have a write take effect as this seems to be done after each write. Also it seems to change the output enable bit and not the data bit so maybe it actually lowers this line by doing that as the reset line may be active low. I don't know how QEMU models the reset line so I don't know what should this do there. You need to find that out from QEMU sources.
(Do you think it helps people trying to follow the thread to randomly cc qemu-ppc or openbios lists or why do you do that?)
Regards, BALATON Zoltan