RE: [OpenBIOS] where I'm at with the 440gx and reading nvram

[David Christensen]

What about the Chip Select on the NVRAM part?  Do you know what drives it?
There might be a GPIO from the PIIX4 or even the SIO that you have to enable
first.  I've also seen designs with custom security ASICs to control access
to the flash part to prevent the flash from being overwritten by a virus.

Dave

-----Original Message-----
From: [e-mail]
[mailto:[e-mail]]On Behalf Of
Ronald G. Minnich
Sent: Monday, January 24, 2000 3:39 PM
To: [e-mail]
Subject: [OpenBIOS] where I'm at with the 440gx and reading nvram

440gx agpset, page 4-2 has a nice map of the memory. 4-4 shows the
extended bios at 4GB-2M. When I do this:
 unsigned long l = 0xffe00000;
  unsigned long flashsize = 0x200000;
  void *v;
  v = ioremap_nocache (l, flashsize);
  if (! v) {
        printk("ioremap failed\n");
        return;
  }

And I probe that memory I only read 0xff. Bad. It's acting like I'm
getting all 1's due to some control chip rejecting the memory cycle. I'd
be happier with a trap ...

So I check the PIIX4E manual, page 60 (section 4.1.9), it shows that
register 4f controls what happens with accesses to the high 2MB of the 4GB
region. If you set bit 2 of 4f, requests should be forwarded. This bit is
set on my machine, but no dice anyway.

Any other thoughts welcome. This is really annoying. We have to get this
working ...

ron

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