On Fri, 20 Jun 2014, Mark Cave-Ayland wrote:
On 19/06/14 22:19, BALATON Zoltan wrote:
With the patch below I don't get DSI-s but it crashes in an ISI while trying to replace the sr registers. How could this possibly work on real hardware without getting any exceptions during replacing the vectors? Is there a way to preload the TLB with code addresses too so we can avoid the crash? How? (For data accessing it before calling the boot code is enough to preload translations but how to avoid ISI-s?)
Unfortunately, as far as I know there are only a few PPC processors that allow you to lock entries in the TLB and none of them were used in Macs.
As for the code that generates the ISIs, is this in MorphOS as opposed to OpenBIOS? I guess something must have previously accessed an entry on the same page before the registers were updated, or maybe there is some kind of hardware readahead?
The code is in the MorphOS boot loader and what it does is trying to take over memory management. Unfortunately it seems there is a period when it already replaced the vectors but have not set up the TLB hash table yet so it cannot actually handle exceptions. I could prevent DSIs but running the code during this period generates ISI-s. If the code is run in the same order on real hardware then it's not likely that the page is accessed there and not on QEMU. A readahead could explain it but I don't know if that happens. I have no better idea now than manually generating faults for all pages where the client code is loaded before calling it. I'll try to implement that unless someone can suggest a better solution.
Regards, BALATON Zoltan