James Oakley wrote:
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Glue is, however, required for POST and GPIO. There are two ways to go with this, and this has been discussed to some degree. Using a GAL is definitely the cleanest solution. However, is there anybody who wants one of these who doesn't have access to a programmer? Traditional logic chips are more accessible to these people. It's still really cheap even though chip count will increase.
Who agrees/disagrees?
I don't see any advantage of using GAL for the simple purpose of decoding the address. I don't have a GAL programmer and I don't think most people do.
There are two senarios for address decoding: memory (eprom, etc) and device (POST card, printer port, etc). For memory type, there are 20 address lines (SA0-SA19). I am attching a schematic for an ISA address decoder circuit using only two chips: one 138 and one 139 (might need high speed HCT type). You can set jumpers to select the base address. This is a very typical decoder ciucuit. (I cut it out from a larger application so I am not claiming credit for it).
The other type is device. I believe only 64k can be addressed (16 lines). An address decoder can easily be done using similar scheme as the above. I have the schematic of an original IBM PC printer card if anybody is interested.
Thanks, Qiwei
