Robert Reif wrote:
The Breakpoint ACTION Register ASI=0x4c is 64 bits wide but only 13 bits are used. The remainder are ignored on write and read as 0.
See page 15-11 of the SuperSPARC and MultiCache Controller User's Manual.
This manual was available on the sun website prior to the Oracle buy out. I have a paper copy and I may still have the PDF if someone really need it.
Okay and it's also documented as 64 bits in the SuperSPARC II Addendum page A-45 (google for STP1021UG) with a similar 13 valid bits.
Still doesn't mean that we need to carry around about 50 bits of zeros just to match the documentation, when zero extending from a lower precision number will give the same result. In QEMU, the value will be correctly zero-extended, so it doesn't matter what is used internally.
Bob