Andreas Färber wrote:
Since r945 everything except for the trampoline issue should be in SVN.
Cool! :)
I've made no more progress throughout the week though:
Directly after we set the MSR_IR|MSR_DR bits in the MSR (arch/ppc/qemu/ofmem.c:setup_mmu), we get an ISI exception and end up in arch/ppc/qemu/start.S:vector__0x400 (the 0xfffxxxxx one). We proceed up to the bctrl which should take us to arch/ppc/qemu/ofmem.c:isi_exception, but then get a 0x700 program exception. The value in ctr looks sensible, it's some 0xfffxxxxx address.
Hmmm this sounds similar to a SPARC32 issue I was finding over the weekend whereby everything died after the MMU was enabled because the context table wasn't correctly aligned. Could it be possible that the MMU hash tables aren't aligned correctly in memory?
ATB,
Mark.