Author: wmb Date: 2007-05-30 08:07:35 +0200 (Wed, 30 May 2007) New Revision: 423
Modified: cpu/x86/pc/olpc/lxmsrs.fth Log: OLPC - changed the PCI latency timer to 0x40 to conform to the setting that the kernel tries to establish by writing to (nonexistent) PCI config header registers.
Modified: cpu/x86/pc/olpc/lxmsrs.fth =================================================================== --- cpu/x86/pc/olpc/lxmsrs.fth 2007-05-29 18:47:52 UTC (rev 422) +++ cpu/x86/pc/olpc/lxmsrs.fth 2007-05-30 06:07:35 UTC (rev 423) @@ -107,7 +107,7 @@ msr: 5000.2003 00000000.00370037. \ No ERRs msr: 5000.2004 00000000.00000015. \ Clock gating for 3 clocks msr: 5000.2005 00000000.00000000. \ Enable some PCI errors - msr: 5000.2010 fff01120.001a021d. \ PCI timings - LB has the latency timer at max + msr: 5000.2010 fff01140.001a021d. \ PCI timings - LB has the latency timer at max msr: 5000.2011 04000300.00800f01. \ GLPCI_ARB - LX page 581
\ I don't think we need to do anything special for the DOS hole from PCI