Author: wmb Date: 2008-05-21 23:05:04 +0200 (Wed, 21 May 2008) New Revision: 823
Modified: cpu/x86/pc/olpc/rmstart.fth cpu/x86/pc/olpc/romreset.bth Log:
Put "[ifdef] cmos-startup-control" around the startup code that changes memory and clock timing settings based on CMOS RAM values. That symbol is not defined by default, so with this change, bad CMOS RAM contents won't prevent the system from starting. The CMOS override feature can be reinstated for test builds by defining that symbol in config.fth .
Modified: cpu/x86/pc/olpc/rmstart.fth =================================================================== --- cpu/x86/pc/olpc/rmstart.fth 2008-04-18 08:20:31 UTC (rev 822) +++ cpu/x86/pc/olpc/rmstart.fth 2008-05-21 21:05:04 UTC (rev 823) @@ -183,17 +183,21 @@ h# 0017 # cx mov rdmsr \ Read CHIP_REVID h# 0014 # cx mov \ Restore RSTPLL MSR number h# 30 # al cmp >= if \ LX CPU +[ifdef] cmos-startup-control h# 60 # al mov al h# 70 # out h# 71 # al in \ Read CMOS 0x60 al al test 0= if +[then] rdmsr \ Get base MSR value with divisors op: h# 04de.0000 # ax or \ Set the startup time (de) and breadcrumb (4) op: h# 0000.04d9 # dx mov \ PLL value for 333 MB clk, 433 CPU +[ifdef] cmos-startup-control else al dec al h# 71 # out \ Decrement safety counter rdmsr \ Get base MSR value with divisors op: h# 04de.0000 # ax or \ Set the startup time (de) and breadcrumb (4) op: h# 0000.04d3 # dx mov \ PLL value for 333 MB clk, 333 CPU then +[then] wrmsr \ Put in the base value op: h# 0000.1800 invert # ax and \ Turn off the BYPASS bits
Modified: cpu/x86/pc/olpc/romreset.bth =================================================================== --- cpu/x86/pc/olpc/romreset.bth 2008-04-18 08:20:31 UTC (rev 822) +++ cpu/x86/pc/olpc/romreset.bth 2008-05-21 21:05:04 UTC (rev 823) @@ -147,8 +147,10 @@ 00000106.83104104. 00001983 set-msr \ Memory delay values 00000000.00000001. 00001980 set-msr \ Enable memory delays
+[ifdef] cmos-startup-control h# 61 # al mov al h# 70 # out h# 71 # al in \ Read CMOS 0x61 al al test 0= if +[then] 18000100.6a7332a0. 20000019 set-msr
\ The RAM controller is now set up @@ -163,6 +165,7 @@
\ Delay on exit from power mode 1, use unbuffered RAM 130cd801. 2000001a set-msr \ MC_CF1017_DATA LX p 231 +[ifdef] cmos-startup-control else al dec al h# 71 # out \ Decrement safety counter
@@ -193,6 +196,7 @@
dx dx xor bx ax mov 2000001a wmsr \ MC_CF1017_DATA LX p 231 then +[then]
00000200.00000000. 20000020 set-msr \ Power mode entry and exit delays