Implement flush_dcache_range() similar to flush_icache_range() in preparation for adding dma command support.
Signed-off-by: Mark Cave-Ayland mark.cave-ayland@ilande.co.uk --- arch/ppc/qemu/kernel.h | 1 + arch/ppc/qemu/start.S | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+)
diff --git a/arch/ppc/qemu/kernel.h b/arch/ppc/qemu/kernel.h index fe9be83..3e25a56 100644 --- a/arch/ppc/qemu/kernel.h +++ b/arch/ppc/qemu/kernel.h @@ -21,6 +21,7 @@ extern void exit( int status ) __attribute__ ((noreturn));
/* start.S */ extern void flush_icache_range( char *start, char *stop ); +extern void flush_dcache_range( char *start, char *stop ); extern char of_rtas_start[], of_rtas_end[]; extern void call_elf( unsigned long arg1, unsigned long arg2, unsigned long elf_entry );
diff --git a/arch/ppc/qemu/start.S b/arch/ppc/qemu/start.S index fed1b55..c679230 100644 --- a/arch/ppc/qemu/start.S +++ b/arch/ppc/qemu/start.S @@ -660,6 +660,27 @@ _GLOBAL(flush_icache_range): isync blr
+/* flush_dcache_range( unsigned long start, unsigned long stop) */ +_GLOBAL(flush_dcache_range): + li r5,CACHE_LINE_SIZE-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,LG_CACHE_LINE_SIZE + beqlr + mtctr r4 + mr r6,r3 +1: dcbst 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + sync /* wait for dcbst's to get to ram */ + mtctr r4 +2: dcbi 0,r6 + addi r6,r6,CACHE_LINE_SIZE + bdnz 2b + sync + blr + /* Get RAM size from QEMU configuration device */
#define CFG_ADDR 0xf0000510