Re: [OpenBIOS] SPARC32 : Fix SMP Boot

[Mark Cave-Ayland]

On 25/11/16 22:45, Olivier Danet wrote:
> Only the first CPU should clear the RAM
> Signed-off-by: Olivier Danet
>
> diff --git a/arch/sparc32/entry.S b/arch/sparc32/entry.S
> index 82aa88e..0374f0c 100644
> --- a/arch/sparc32/entry.S
> +++ b/arch/sparc32/entry.S
> @@ -125,6 +125,17 @@ entry:
>          sll     %g3, 24, %g3
>          or      %g3, %g4, %g1
>          ! %g1 contains end of memory
>    ! Get CPU number
>    ! XXX: not all CPUs should have MXCC
>    set     0x1c00f00, %g2
>    ldda    [%g2] ASI_CONTROL, %g2
>    srl     %g3, 24, %g7
>    subcc   %g7, 8, %g7
>    ! Only the first CPU clears memory
>    bnz     clear_done
>     nop
>
>    ! Get kernel address from configuration device
>    ! NB: little endian format
>
> @@ -146,6 +157,9 @@ entry:
>          sll     %g3, 24, %g3
>          or      %g3, %g4, %g4
>    mov     0,%l0
>    mov     0,%l1
>    
>    ! If kernel address is set, don't clear from base of RAM in order to
>    ! leave the kernel image intact
>    mov     0, %g6
>
> @@ -157,8 +171,8 @@ entry:
>          set     0x1000000, %g6
>
> clear_mem:
>    sta     %g0, [%g6] ASI_M_BYPASS
>    add     %g6, 0x4, %g6
>    stda    %l0, [%g6] ASI_M_BYPASS
>    add     %g6, 0x8, %g6
>    cmp     %g6, %g1
>    bl      clear_mem
>     nop
>
> @@ -168,23 +182,6 @@ clear_done:
>          set     0x2000, %g3
>          sub     %g1, %g3, %g6
>    ! Check if this is the boot CPU and skip SMP table check if yes
>    ! XXX: not all CPUs should have MXCC
>    set     0x1c00f00, %g2
>    ldda    [%g2] ASI_CONTROL, %g2
>    srl     %g3, 24, %g7
>    sub     %g7, 8, %g7
>    tst     %g7
>    bz      skip_table
>     nop
>    ! Calculate SMP table location
> set	0x1f0c, %g2
>    add     %g6, %g2, %g2                 ! valid?
>    lda     [%g2] ASI_M_BYPASS, %g7
>    sta     %g0, [%g2] ASI_M_BYPASS
>
> -skip_table:
>          ! Get machine ID from configuration device
>          mov     FW_CFG_MACHINE_ID, %g2
>          sub     %g5, 2, %g5
> @@ -205,36 +202,39 @@ skip_table:
>          blu     ss2
>           nop
>    ! Ok, this is SS-5
>    ! Ok, this is SS-5, uniprocessor
>    ba      first_cpu
>     nop
>
> +ss10:
>    ! Ok, this is SS-10/20 or SS-600MP
>    tst     %g7
>    bz      first_cpu
>     nop
>
>    ! Clear softints used for SMP CPU startup
>    set     PHYS_JJ_INTR0 + 0x04, %g1
>    sll     %g2, 12, %g2
>    ! SMP init, clear softints, which are used for starting non-boot CPUs
>    set     PHYS_SS10_INTR0 + 0x04, %g1
>    sll     %g7, 12, %g2
>    add     %g1, %g2, %g2
>    set     0xffffffff, %g1
>    sta     %g1, [%g2] ASI_M_BYPASS         ! clear softints
>    sta     %g1, [%g2] ASI_M_CTL            ! clear softints
>    add     %g2, 4, %g2
>    sta     %g0, [%g2] ASI_M_BYPASS         ! clear softints
>    sta     %g0, [%g2] ASI_M_CTL            ! clear softints
>
> -load_ctx:
>          ! SMP init, jump to user specified address
> set	0x1f04, %g5
>    set     0x1f04, %g5
>    add     %g6, %g5, %g5                 ! ctxtbl
>    lda     [%g5] ASI_M_BYPASS, %g2
>    sta     %g0, [%g5] ASI_M_BYPASS
>    set     AC_M_CTPR, %g1
>    sta     %g2, [%g1] ASI_M_MMUREGS        ! set ctx table ptr
> set	0x1f00, %g5
>    set     0x1f00, %g5
>    add     %g6, %g5, %g5                 ! ctx
>    lda     [%g5] ASI_M_BYPASS, %g2
>    sta     %g0, [%g5] ASI_M_BYPASS
>    set     AC_M_CXR, %g1
>    sta     %g2, [%g1] ASI_M_MMUREGS        ! set context
> set	0x1f08, %g5
>    set     0x1f08, %g5
>    add     %g6, %g5, %g5                 ! entry
>    lda     [%g5] ASI_M_BYPASS, %g2
>    sta     %g0, [%g5] ASI_M_BYPASS
>
> @@ -242,22 +242,6 @@ load_ctx:
>          jmp     %g2                             ! jump to kernel
>           sta    %g1, [%g0] ASI_M_MMUREGS        ! enable mmu
>
> -ss10:
>    ! Ok, this is SS-10 or SS-600MP
>    tst     %g7
>    bz      first_cpu
>     nop
>    ! Clear softints used for SMP CPU startup
>    set     PHYS_SS10_INTR0 + 0x04, %g1
>    sll     %g2, 12, %g2
>    add     %g1, %g2, %g2
>    set     0xffffffff, %g1
>    sta     %g1, [%g2] ASI_M_CTL            ! clear softints
>    add     %g2, 4, %g2
>    b       load_ctx
>     sta    %g0, [%g2] ASI_M_CTL            ! clear softints
>
> ss2:
>          ! Ok, this is SS-2
>          set     ss2_error, %o2

Hi Olivier,

Thanks for the patch!

It looks like this does a bit more than bypass the memory clearing for
CPU IDs != 0, e.g.

-        sta     %g1, [%g2] ASI_M_BYPASS         ! clear softints
+        sta     %g1, [%g2] ASI_M_CTL            ! clear softints
         add     %g2, 4, %g2
-        sta     %g0, [%g2] ASI_M_BYPASS         ! clear softints
+        sta     %g0, [%g2] ASI_M_CTL            ! clear softints

Could you augment the commit the message to explain a bit more about this?

Also can you confirm how you were able to test the patch - was it
booting in QEMU with -smp 2 or similar?

ATB,

Mark.