Author: wmb Date: 2007-05-03 09:51:00 +0200 (Thu, 03 May 2007) New Revision: 344
Modified: cpu/x86/pc/olpc/chipinit.fth cpu/x86/pc/olpc/vsapci.fth Log: OLPC B3 - Added interrupt line and interrupt pin reporting for the LX display, and changed the display interrupt to IRQ14 so it doesn't share with the CaFe interrupt.
Modified: cpu/x86/pc/olpc/chipinit.fth =================================================================== --- cpu/x86/pc/olpc/chipinit.fth 2007-05-01 16:45:44 UTC (rev 343) +++ cpu/x86/pc/olpc/chipinit.fth 2007-05-03 07:51:00 UTC (rev 344) @@ -551,7 +551,7 @@ msr: 5140.0020 00000000.bb350a00. \ IRQM_YLOW msr: 5140.0021 00000000.04000000. \ IRQM_YHIGH msr: 5140.0022 00000000.00002222. \ IRQM_ZLOW - msr: 5140.0023 00000000.60baa5b2. \ IRQM_ZHIGH + msr: 5140.0023 00000000.60baa5e2. \ IRQM_ZHIGH msr: 5140.0025 00000000.00001002. \ IRQM_LPC \ msr: 5140.0028 00000000.00000000. \ MFGPT_IRQ off - default \ msr: 5140.0040 00000000.00000000. \ DMA_MAP - default
Modified: cpu/x86/pc/olpc/vsapci.fth =================================================================== --- cpu/x86/pc/olpc/vsapci.fth 2007-05-01 16:45:44 UTC (rev 343) +++ cpu/x86/pc/olpc/vsapci.fth 2007-05-03 07:51:00 UTC (rev 344) @@ -38,7 +38,7 @@ fd000000 , fe000000 , fe004000 , fe008000 , \ FB, GP, VG, DF 0 , 0 , 0 , 30100b , \ VIP (LX only) 0 , 0 , 0 , 0 , - 0 , 0 , 0 , 0 , + 0 , 0 , 0 , 0 , \ Interrupt goes at 5c for LX 3d0 , 3c0 , a0000 , 0 , \ VG IO, VG IO, EGA FB, MONO FB 0 , 0 , 0 , 0 ,
@@ -203,6 +203,7 @@ h# ffffc000 gxfb-hdr h# 10 + l! \ BAR4 MASK - VIP h# 20811022 gxfb-hdr h# 20 + l! \ Vendor/device ID - AMD h# fe00c000 gxfb-hdr h# 40 + l! \ BAR4 address - VIP + h# 10e gxfb-hdr h# 5c + w! \ Interrupt pin and line - INTA, IRQ 14 then
[ifdef] lx-devel exit [then]