Le 28/01/2022 à 13:14, Fabiano Rosas a écrit :
Christophe Leroy christophe.leroy@csgroup.eu writes:
Unlike the 604 core, the 603 doesn't perform table search in HW. When a TLB Miss occurs, the 603 generates one of three specific TLB Miss exception:
- Instruction TLB Miss
- Data read TLB Miss
- Data store TLB Miss
The associated exception handlers have to search the match page table entry and load it in a TLB entry.
This patch implements the exemple provided in the reference manual (with a couple of errors corrected).
Signed-off-by: Christophe Leroy christophe.leroy@csgroup.eu Cc: Fabiano Rosas farosas@linux.ibm.com Cc: Cédric Le Goater clg@kaod.org Cc: Mark Cave-Ayland mark.cave-ayland@ilande.co.uk
arch/ppc/qemu/start.S | 158 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 155 insertions(+), 3 deletions(-)
diff --git a/arch/ppc/qemu/start.S b/arch/ppc/qemu/start.S index c679230..3d4102d 100644 --- a/arch/ppc/qemu/start.S +++ b/arch/ppc/qemu/start.S @@ -25,6 +25,14 @@ #define ILLEGAL_VECTOR( v ) .org __vectors + v ; vector__##v: bl trap_error ; #define VECTOR( v, dummystr ) .org __vectors + v ; vector__##v
+#define SPR_DMISS 976 +#define SPR_DCMP 977 +#define SPR_HASH1 978 +#define SPR_HASH2 979 +#define SPR_IMISS 980 +#define SPR_ICMP 981 +#define SPR_RPA 982
#ifdef CONFIG_PPC_64BITSUPPORT
/* We're trying to use the same code for the ppc32 and ppc64 handlers here.
@@ -329,9 +337,153 @@ ILLEGAL_VECTOR( 0xd00 ) ILLEGAL_VECTOR( 0xe00 ) ILLEGAL_VECTOR( 0xf00 ) ILLEGAL_VECTOR( 0xf20 ) -ILLEGAL_VECTOR( 0x1000 ) -ILLEGAL_VECTOR( 0x1100 ) -ILLEGAL_VECTOR( 0x1200 )
+VECTOR( 0x1000, "IFTLB" ):
Won't these vectors clobber r0-r3? You might need an EXCEPTION_PREAMBLE here and use exception_return instead of rfi. At least I did in the 7450 patch:
No they don't clobber r0-r3 on the 603, that's one of the features of the 603 MMU hardware assist.
Extract from reference manual (https://www.nxp.com/docs/en/reference-manual/MPC603EUM.pdf)
Shadow registers for GPR0–GPR3 that allow miss code to execute without corrupting the state of any of the existing GPRs. Shadow registers are used only for servicing a TLB miss.
Christophe