Ronald G Minnich rminnich@lanl.gov writes:
Ron unless you have something better I'd suggest using one of the upcoming dual Itanium/P4 chipsets as a starting point. Then you could be certain the chipset worked before on x86 before trying to reverse engineer the cpu initialization for the Itanium...
do we have a vendor name yet?
I have seen reports that both Intel and IBM are working on chipsets that will support that. I think the reports were talking many way SMP but possibly that is because where Itanium is positioned. This looks like it may be in the McKinley time frame. I have a strange hunch that McKinley will be bus compatible with the P4. This is what I am picking up through osmosis reading the reviews.
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