OpenBIOS

openbios@openbios.org

4297 discussions

[RFC PATCH v2 0/4] QEMU/openbios: PPC Software TLB support in the G4 family
by Fabiano Rosas 15 Dec '21

15 Dec '21

Hi all, Recap: - QEMU enables 7450 SW TLB search by default; - OpenBIOS does not know about SW TLB (vectors 0x1000, 0x1100, 0x1200); - OpenBIOS does not know about 7450s PVRs. Proposed solutions: a) find another firmware/guest OS code that supports the feature; b) implement the switching of the feature in QEMU and have the guest code enable it only when supported. That would take some fiddling with the MMU code to: merge POWERPC_MMU_SOFT_74xx into POWERPC_MMU_32B, check the HID0[STEN] bit, figure out how to switch from HW TLB miss to SW TLB miss on demand, block access to the TLBMISS register (and others) when the feature is off, and so on; c) leave the feature enabled in QEMU and implement the software TLB miss handlers in openbios. The UM provides sample code, so this is easy; d) remove support for software TLB search for the 7450 family and switch the cpus to the POWERPC_MMU_32B model. This is by far the easiest solution, but could cause problems for any (which?) guest OS code that actually uses the feature. All of the existing code for the POWERPC_MMU_SOFT_74xx MMU model would probably be removed since it would be dead code then; v1: https://lists.nongnu.org/archive/html/qemu-ppc/2021-11/msg00289.html v2: This series corresponds to option d) above. - patch 1 moves all of the 7450 CPUs* into the POWERPC_MMU_32B MMU model, which does the same as the POWERPC_MMU_SOFT_74xx minus the software TLB handling. It also removes the instructions (tlbld, tlbli) and SPRs (TLBMISS, PTEHI, PTELO) from the 7450s as these facilities are only used along with the software TLB. *- except for 7448, which is seen by QEMU as a 7400. - patch 2 removes the instructions and SPRs just like above, but from the e600 CPU. The e600 already uses the POWERPC_MMU_32B MMU model, so it already has software TLB disabled. - patch 3 removes all of the now dead code for the 74xx software TLB. I left a note in the code with keywords to help with grep in case people search for the feature in the future. - patch 4 adds smoke tests for all of the 74xx CPUs. These are broken pending the OpenBIOS patch. For OpenBIOS: We'd need to merge the patch 2/2 from the previous series: https://lists.nongnu.org/archive/html/qemu-ppc/2021-11/msg00290.html Message ID: 20211119134431.406753-3-farosas(a)linux.ibm.com this is just for the new PVRs. There is no need to add the handlers. Thanks! Fabiano Rosas (4): target/ppc: Disable software TLB for the 7450 family target/ppc: Disable unused facilities in the e600 CPU target/ppc: Remove the software TLB model of 7450 CPUs tests/avocado: ppc: Add smoke tests for MPC7400 and MPC7450 families target/ppc/cpu-qom.h | 6 +- target/ppc/cpu.h | 4 +- target/ppc/cpu_init.c | 57 ++++-------------- target/ppc/excp_helper.c | 29 --------- target/ppc/helper.h | 2 - target/ppc/mmu_common.c | 19 ------ target/ppc/mmu_helper.c | 31 ---------- target/ppc/translate.c | 26 -------- tests/avocado/ppc_74xx.py | 123 ++++++++++++++++++++++++++++++++++++++ 9 files changed, 140 insertions(+), 157 deletions(-) create mode 100644 tests/avocado/ppc_74xx.py -- 2.33.1

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[PATCH v8] arch/ppc/qemu: Add a node for the empty first PCI bus to the device tree
by BALATON Zoltan 20 Nov '21

20 Nov '21

3 24

[PATCH v9] arch/ppc/qemu: Add a node for the empty first PCI bus to the device tree
by BALATON Zoltan 06 Nov '21

06 Nov '21

QEMU mac99 emulates two of the three PCI buses found on real PowerMac3,1 but OpenBIOS currently only handles a single PCI bus and inits and puts info in the device tree of the second PCI bus only (which is where devices are connected). However, some clients (e.g. MorphOS) may have hardcoded assumptions and erroneously use the address of the first bus to access PCI config registers for devices on the second bus if the first bus is missing from the device tree, which silently fails as these requests will go to the other empty bus emulated and return invalid values as the device they address are not present there. As a result devices mapped via MMIO still appear to work but they may not be correctly initialised and some cards are not detected because of this. One such case might be enabling bus master bit for network cards which the OS should do but OpenBIOS has workaround for it now. Once both PCI buses appear in device tree those workarounds may not be needed any more. Until proper support for multiple PCI buses is implemented add an empty node in the device tree for the first bus on QEMU mac99 to let OSes know about it. This fixes detecting PCI devices (such as USB) under MorphOS and allows it to boot. Signed-off-by: BALATON Zoltan <balaton(a)eik.bme.hu> --- arch/ppc/qemu/init.c | 113 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 113 insertions(+) diff --git a/arch/ppc/qemu/init.c b/arch/ppc/qemu/init.c index 45cd77e..2bee848 100644 --- a/arch/ppc/qemu/init.c +++ b/arch/ppc/qemu/init.c @@ -716,6 +716,116 @@ static void kvm_of_init(void) fword("finish-device"); } +static void encode_int_plus(int n, ...) +{ + int i; + ucell v; + va_list ap; + + va_start(ap, n); + for (i = 0; i < n; i++) { + v = va_arg(ap, ucell); + PUSH(v); + fword("encode-int"); + if (i > 0) { + fword("encode+"); + } + } + va_end(ap); +} + +static void empty_pci_bus_init(void) +{ + if (machine_id != ARCH_MAC99) { + return; + } + fword("new-device"); + push_str("pci"); + fword("device-name"); + push_str("pci"); + fword("device-type"); + push_str("AAPL,UniNorth"); + fword("encode-string"); + push_str("model"); + fword("property"); + push_str("uni-north"); + fword("encode-string"); + push_str("compatible"); + fword("property"); + encode_int_plus(2, 0xf0000000, 0x02000000); + push_str("reg"); + fword("property"); + PUSH(3); + fword("encode-int"); + push_str("#address-cells"); + fword("property"); + PUSH(2); + fword("encode-int"); + push_str("#size-cells"); + fword("property"); + PUSH(1); + fword("encode-int"); + push_str("#interrupt-cells"); + fword("property"); + PUSH(66666666); + fword("encode-int"); + push_str("clock-frequency"); + fword("property"); + PUSH(0x800); + fword("encode-int"); + push_str("UNI-N"); + fword("encode-string"); + fword("encode+"); + push_str("built-in-names"); + fword("property"); + PUSH(0x10000); + fword("encode-int"); + push_str("SLOT-A"); + fword("encode-string"); + fword("encode+"); + push_str("slot-names"); + fword("property"); + encode_int_plus(18, + 0x02000000, 0, 0xf1000000, 0xf1000000, 0, 0x01000000, + 0x01000000, 0, 0, 0xf0000000, 0, 0x00800000, + 0x02000000, 0, 0x90000000, 0x90000000, 0, 0x10000000); + push_str("ranges"); + fword("property"); + encode_int_plus(2, 0, 0); + push_str("bus-range"); + fword("property"); + fword("finish-device"); +} + +static void empty_pci_bus_interrupts(void) +{ + phandle_t pic, dnode; + u32 props[8]; + + if (machine_id != ARCH_MAC99) { + return; + } + pic = dt_iterate_type(0, "open-pic"); + dnode = find_dev("/pci@f0000000"); + props[0] = 0x2d; + props[1] = 0x1; + set_property(dnode, "interrupts", (char *)props, 2 * sizeof(u32)); + set_int_property(dnode, "interrupt_patent", pic); + props[0] = 0x8000; + props[1] = 0; + props[2] = 0; + props[3] = 0; + props[4] = pic; + props[5] = 0x30; + props[6] = 0x1; + set_property(dnode, "interrupt-map", (char *)props, 7 * sizeof(u32)); + props[0] = 0xf800; + props[1] = 0; + props[2] = 0; + props[3] = 0; + set_property(dnode, "interrupt-map-mask", (char *)props, 4 * sizeof(u32)); +} + /* * filll ( addr bytes quad -- ) */ @@ -868,8 +978,11 @@ arch_of_init(void) case ARCH_MAC99_U3: /* The NewWorld NVRAM is not located in the MacIO device */ macio_nvram_init("/", 0); + /* We only handle 1 PCI bus but MorphOS needs info for both to boot */ + empty_pci_bus_init(); ob_pci_init(); ob_unin_init(); + empty_pci_bus_interrupts(); break; default: ob_pci_init(); -- 2.30.2

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Re: Installing OpenBIOS
by bernd1-1＠web.de 06 Nov '21

06 Nov '21

2 2

[PATCH] cuda: fix reset-all and power-off words
by Mark Cave-Ayland 30 Oct '21

30 Oct '21

There is a long-standing bug in the CUDA implementation of the reset-all and power-off words whereby an extra byte is written after the CUDA_RESET_SYSTEM and CUDA_POWERDOWN commands. This extra byte used to be ignored in QEMU until commits 017da0b568 ("cuda: port POWERDOWN command to new framework") and 54e894442e ("cuda: port RESET_SYSTEM command to new framework") added a check which rejects the command if the command length is incorrect. Fix the outgoing command length to remove the extra byte which allows the reset-all and power-off words to work in QEMU once again. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland(a)ilande.co.uk> Fixes: https://gitlab.com/qemu-project/qemu/-/issues/624 --- drivers/cuda.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cuda.c b/drivers/cuda.c index 56d73e1..c89b174 100644 --- a/drivers/cuda.c +++ b/drivers/cuda.c @@ -177,7 +177,7 @@ static cuda_t *main_cuda; static void ppc32_reset_all(void) { - uint8_t cmdbuf[2], obuf[64]; + uint8_t cmdbuf[1], obuf[64]; cmdbuf[0] = CUDA_RESET_SYSTEM; cuda_request(main_cuda, CUDA_PACKET, cmdbuf, sizeof(cmdbuf), obuf); @@ -186,7 +186,7 @@ ppc32_reset_all(void) static void ppc32_poweroff(void) { - uint8_t cmdbuf[2], obuf[64]; + uint8_t cmdbuf[1], obuf[64]; cmdbuf[0] = CUDA_POWERDOWN; cuda_request(main_cuda, CUDA_PACKET, cmdbuf, sizeof(cmdbuf), obuf); -- 2.20.1

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[PATCH 0/2] escc: reset fixes for sun keyboard/mouse
by Mark Cave-Ayland 30 Oct '21

30 Oct '21

The sun4m machine uses 2 ESCC devices: one for use as normal serial ports and another for use with a Sun keyboard/mouse. The previous ESCC fixes added new code to send the ESCC soft reset sequence for the normal serial ports but failed to do so for the keyboard/mouse serial ports. This worked fine for OpenBIOS and all of my SPARC32 test images except for my OpenBSD test image which hangs on boot: whilst the OS sends the reset sequence to the normal serial port, it tries to access the Sun keyboard/mouse serial ports without sending the reset sequence first causing it to get stuck in a polling loop waiting for the status register bits to be set correctly. This patchset updates the kbd_init() function which initialises the ESCC used by the Sun keyboard/mouse so that it now sends the ESCC soft reset sequence to both ports. This ensures that the status register bits are set to their expected reset defaults which allows OpenBSD SPARC32 to boot successfully once again. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland(a)ilande.co.uk> Mark Cave-Ayland (2): escc: add speed parameter to kbd_init() for sun keyboard/mouse serial ports escc: initialise sun keyboard/mouse serial ports in kbd_init() arch/sparc32/openbios.c | 2 +- drivers/escc.c | 4 +++- include/drivers/drivers.h | 2 +- 3 files changed, 5 insertions(+), 3 deletions(-) -- 2.20.1

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[PATCH] arch/ppc/qemu: Add a dummy device tree node for the first PCI bus
by BALATON Zoltan 24 Oct '21

24 Oct '21

Real PowerMac3,1 has two PCI and one AGP buses that are emulated in QEMU but OpenBIOS currently only handles a single PCI bus and inits and puts info in the device tree of the second PCI bus only (which is where devices are connected). MorphOS is confused by this and erroneously uses the address of the first bus to access PCI config registers for devices on the second bus if the first pci node is missing from the device tree, This results in either not booting at all or devices mapped via MMIO may still appear to work but they may not be correctly initialised and some cards are not detected because of this. However, adding the other /pci node causes problems with other guests such as NetBSD. Fortunately MorphOS is happy as long as any node of pci device-type comes before the actual /pci entry. Until proper support for multiple PCI buses is implemented, add such a dummy node in the device tree for QEMU mac99 to avoid this problem which fixes detecting PCI devices (such as USB) under MorphOS and allows it to boot. Signed-off-by: BALATON Zoltan <balaton(a)eik.bme.hu> --- arch/ppc/qemu/init.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/ppc/qemu/init.c b/arch/ppc/qemu/init.c index 45cd77e..ef8b27a 100644 --- a/arch/ppc/qemu/init.c +++ b/arch/ppc/qemu/init.c @@ -865,6 +865,16 @@ arch_of_init(void) switch (machine_id) { case ARCH_MAC99: + /* This adds a dummy node of pci device-type before the actual /pci + * node which is needed for MorphOS to find devices on PCI bus. + * (Real machine has 3 /pci nodes but we only have one.) */ + fword("new-device"); + push_str("dummy-pci"); + fword("device-name"); + push_str("pci"); + fword("device-type"); + fword("finish-device"); + /* fall through */ case ARCH_MAC99_U3: /* The NewWorld NVRAM is not located in the MacIO device */ macio_nvram_init("/", 0); -- 2.21.4

1 0

[PATCH v7] arch/ppc/qemu: Add a node for the empty first PCI bus to the device tree
by BALATON Zoltan 23 Oct '21

23 Oct '21

2 11

Installing OpenBIOS
by bernd1-1＠web.de 23 Oct '21

23 Oct '21

Hi. I've watched a television broadcast where a hacker or security expert suspected that the BIOS of ThinkPads has a backdoor and therefore he installed OpenBIOS. I read https://www.openfirmware.info/OpenBIOS. 1. Please tell me whether a user without knowledge in programming or Linux command lines in Terminal is able to install OpenBIOS. 2. Would you provide step by step instructions (especially for my case) how to install OpenBIOS on my system? Regards,

2 1

[PATCH 0/2] escc: add missing port reset
by Mark Cave-Ayland 08 Sep '21

08 Sep '21

An upcoming change to QEMU's ESCC device reset mechanism exposed a bug that OpenBIOS's ESCC driver doesn't actually reset the port before attempting to configure it. Whilst this has no effect for now, once the QEMU ESCC changes have been merged (which implement the reset as documented in the datasheet), this port reset must be sent so that the registers are set to their default values after power-on. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland(a)ilande.co.uk> Mark Cave-Ayland (2): escc: add port index to uart_init_line() escc: send software reset command before configuring the port drivers/escc.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) -- 2.20.1

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