OpenBIOS January 2009

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Re: [OpenBIOS] Fix boot-script parsing for openSUSE ppc media
by laurent＠vivier.eu 29 Jan '09

29 Jan '09

> Fix boot-script parsing for openSUSE ppc media applied, thanks Laurent

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r429 - openbios-devel/arch/ppc/qemu
by svn＠openbios.org 29 Jan '09

29 Jan '09

Author: laurent Date: 2009-01-29 11:51:25 +0100 (Thu, 29 Jan 2009) New Revision: 429 Modified: openbios-devel/arch/ppc/qemu/main.c Log: Add an enhancement to deal with configurations in /ppc/bootinfo.txt like <boot-script>boot &device;:1,\suseboot\yaboot.ibm</boot-script>. This would evaluate to boot cd:0,1\suseboot\yaboot.ibm which results in a file not found error (seen on many openSUSE ppc media). With this patch the above will evaluate to boot cd:0,\suseboot\yaboot.ibm and yaboot will load. Signed-off-by: Stefan Assmann <sassmann(a)suse.de> Modified: openbios-devel/arch/ppc/qemu/main.c =================================================================== --- openbios-devel/arch/ppc/qemu/main.c 2009-01-26 17:09:21 UTC (rev 428) +++ openbios-devel/arch/ppc/qemu/main.c 2009-01-29 10:51:25 UTC (rev 429) @@ -208,6 +208,8 @@ fword("2drop"); right = pop_fstr_copy(); left = pop_fstr_copy(); + while (right[0] != '\\' && right[0] != '\0') + right++; snprintf(bootscript, sizeof(bootscript), "%s%s,%s", left, path, right); ELF_DPRINTF("fixed bootscript %s\n", bootscript);

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Fix boot-script parsing for openSUSE ppc media
by Stefan Assmann 29 Jan '09

29 Jan '09

Subject: Fix boot-script parsing for openSUSE ppc media Add an enhancement to deal with configurations in /ppc/bootinfo.txt like <boot-script>boot &device;:1,\suseboot\yaboot.ibm</boot-script>. This would evaluate to boot cd:0,1\suseboot\yaboot.ibm which results in a file not found error (seen on many openSUSE ppc media). With this patch the above will evaluate to boot cd:0,\suseboot\yaboot.ibm and yaboot will load. Signed-off-by: Stefan Assmann <sassmann(a)suse.de> Index: arch/ppc/qemu/main.c =================================================================== --- arch/ppc/qemu/main.c (revision 418) +++ arch/ppc/qemu/main.c (working copy) @@ -208,6 +208,8 @@ fword("2drop"); right = pop_fstr_copy(); left = pop_fstr_copy(); + while (right[0] != '\\' && right[0] != '\0') + right++; snprintf(bootscript, sizeof(bootscript), "%s%s,%s", left, path, right); ELF_DPRINTF("fixed bootscript %s\n", bootscript); Stefan -- Stefan Assmann | SUSE LINUX Products GmbH Software Engineer | Maxfeldstr. 5, D-90409 Nuernberg Mail: sassmann(a)suse.de | GF: Markus Rex, HRB 16746 (AG Nuernberg)

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OpenBIOS SVN r416 breaks coreboot-v3
by Mark Cave-Ayland 28 Jan '09

28 Jan '09

Hi everyone, Whilst playing around with openbios to try and understand how it works on different platforms, I found that using coreboot-v3 with openbios SVN causes openbios to panic on boot under qemu SVN. The trace can be found here: http://pastebin.siriusit.co.uk/coreboot-v3-panic.txt With the help of some people on the coreboot mailing list, I've performed an SVN bisection and found that the panic starts appearing at r416 in openbios SVN for which the commit message can be found here: http://lists.openbios.org/pipermail/openbios/2009-January/003401.html However, I can't find any reference to the rationale behind the commit. Can anyone explain further explain whether is commit is correct or not? It would be really helpful if you could CC replies to the coreboot mailing list to help resolve this - the original thread can be found here: http://www.coreboot.org/pipermail/coreboot/2009-January/044462.html Many thanks, Mark. -- Mark Cave-Ayland Sirius Corporation - The Open Source Experts http://www.siriusit.co.uk T: +44 870 608 0063

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[Fwd: Re: [coreboot] OpenBIOS SVN r416 breaks coreboot-v3]
by Mark Cave-Ayland 28 Jan '09

28 Jan '09

[ Forwarding onto the OpenBIOS list ] Just for those people who aren't on the coreboot mailing list - the thinking so far is that SVN trunk qemu has a part in this, as the resulting bios.bin works fine on 0.9.1. ATB, Mark. -- Mark Cave-Ayland Sirius Corporation - The Open Source Experts http://www.siriusit.co.uk T: +44 870 608 0063

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Re: [OpenBIOS] [coreboot] OpenBIOS SVN r416 breaks coreboot-v3
by Mark Cave-Ayland 28 Jan '09

28 Jan '09

Myles Watson wrote: > That's actually what I would have expected. The IO address range is > only 16 bits from 0-64K. > > I guess we'll have to get more information from qemu so we know which > port address is being accessed when it dies. > > Myles Hi Myles, Here's my quick patch to qemu to dump out the address where the write is failing: Index: vl.c =================================================================== --- vl.c (revision 6426) +++ vl.c (working copy) @@ -389,7 +389,7 @@ for(i = start; i < start + length; i += size) { ioport_write_table[bsize][i] = func; if (ioport_opaque[i] != NULL && ioport_opaque[i] != opaque) - hw_error("register_ioport_write: invalid opaque"); + hw_error("register_ioport_write: invalid opaque: (start 0x%x, length 0x%x, address 0x%x)", start, length, i); ioport_opaque[i] = opaque; } return 0; And here is the result output: qemu: hardware error: register_ioport_write: invalid opaque: (start 0x510, length 0x1, address 0x510) HTH, Mark. -- Mark Cave-Ayland Sirius Corporation - The Open Source Experts http://www.siriusit.co.uk T: +44 870 608 0063

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r428 - in openbios-devel: config/examples include/openbios
by svn＠openbios.org 26 Jan '09

26 Jan '09

Author: blueswirl Date: 2009-01-26 18:09:21 +0100 (Mon, 26 Jan 2009) New Revision: 428 Modified: openbios-devel/config/examples/sparc32_config.xml openbios-devel/include/openbios/drivers.h Log: Fix native Sparc32 compile Modified: openbios-devel/config/examples/sparc32_config.xml =================================================================== --- openbios-devel/config/examples/sparc32_config.xml 2009-01-25 20:37:01 UTC (rev 427) +++ openbios-devel/config/examples/sparc32_config.xml 2009-01-26 17:09:21 UTC (rev 428) @@ -75,5 +75,6 @@ <option name="CONFIG_DRIVER_FLOPPY" type="boolean" value="true"/> <option name="CONFIG_DEBUG_FLOPPY" type="boolean" value="false"/> <option name="CONFIG_DRIVER_ESCC" type="boolean" value="true"/> + <option name="CONFIG_DRIVER_ESCC_SUN" type="boolean" value="true"/> </config> Modified: openbios-devel/include/openbios/drivers.h =================================================================== --- openbios-devel/include/openbios/drivers.h 2009-01-25 20:37:01 UTC (rev 427) +++ openbios-devel/include/openbios/drivers.h 2009-01-26 17:09:21 UTC (rev 428) @@ -16,6 +16,9 @@ #ifdef CONFIG_DRIVER_PCI /* drivers/pci.c */ int ob_pci_init(void); +#endif + +#if defined(CONFIG_DRIVER_PCI) || defined(CONFIG_DRIVER_ESCC) #ifdef CONFIG_PPC extern int is_apple(void); extern int is_oldworld(void);

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Re: [OpenBIOS] [sparc64] Problematic pci at 0 and pci nodes in the device tree
by Mark Cave-Ayland 25 Jan '09

25 Jan '09

> Hi, > > I have the following problem with the OpenBIOS device tree (the > current Qemu version): > In the root directory, there are currently two pci nodes: > > ffd97778 pci at 0 > ffd98808 pci > > The "screen" alias is defined as: > /pci/pci/pci/QEMU,VGA > > When HelenOS attempts to lookup this path, it fails, because it > matches /pci instead of /pci at 0 and /pci does not have any children. > HelenOS is normally designed to cope with ambiguous node names, but in > this case the /pci node matches and sends it to the wrong direction. I > think the "screen" alias should be either defined using the > non-ambiguous pci at 0 path components or the /pci node should not > exist at all. > > Can you confirm this is a problem in the tree? Hi Jakub, I too am interested in getting Sparc64 working in Qemu in order to resurrect some old Solaris disk images I have here. Can you explain some more about the debugging methods you are using to analyse the forth dictionaries? At the moment I am struggling in that when running Qemu with "-vnc :1" on the command line, qemu-system-sparc64 simply hangs :( Many thanks, Mark. -- Mark Cave-Ayland Sirius Corporation - The Open Source Experts http://www.siriusit.co.uk T: +44 870 608 0063

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r427 - openbios-devel/modules
by svn＠openbios.org 25 Jan '09

25 Jan '09

Author: blueswirl Date: 2009-01-25 21:37:01 +0100 (Sun, 25 Jan 2009) New Revision: 427 Modified: openbios-devel/modules/console_common.c Log: Fix console escape code problems with NetBSD 4.0 and Debian 3.1r1 Modified: openbios-devel/modules/console_common.c =================================================================== --- openbios-devel/modules/console_common.c 2009-01-25 12:20:12 UTC (rev 426) +++ openbios-devel/modules/console_common.c 2009-01-25 20:37:01 UTC (rev 427) @@ -21,6 +21,18 @@ #define NCOLS 80 #define NROWS 48 +// Warning: will hang on purpose when encountering unknown codes +//#define DEBUG_CONSOLE +#ifdef DEBUG_CONSOLE +#define DPRINTF(fmt, args...) \ + do { \ + printk(fmt , ##args); \ + for (;;); \ + } while (0) +#else +#define DPRINTF(fmt, args...) do {} while(0) +#endif + typedef enum { ESnormal, ESesc, ESsquare, ESgetpars, ESgotpars, ESfunckey, EShash, ESsetG0, ESsetG1, ESpercent, ESignore, ESnonstd, @@ -150,40 +162,86 @@ static void scroll1( void ) { - int x; + int x, y; - video_scroll( FONT_ADJ_HEIGHT ); + video_scroll(FONT_ADJ_HEIGHT); - for( x=0; x<cons.w; x++ ) - cons.buf[(cons.h-1)*cons.w + x] = 0; - draw_line(cons.h-1); + for (y = 1; y < cons.h - 1; y++) { + for (x = 0; x < cons.w; x++) + cons.buf[(y - 1) * cons.w + x] = cons.buf[y * cons.w + x]; + } + for (x = 0; x < cons.w; x++) + cons.buf[(cons.h - 1) * cons.w + x] = ' '; + draw_line(cons.h - 1); } +// Insert char +static void csi_at(unsigned int nr) +{ + unsigned int x; + + if (nr > cons.w - cons.x) + nr = cons.w - cons.x; + else if (!nr) + return; + + for (x = cons.x + nr; x < cons.w - 1; x++) + cons.buf[cons.y * cons.w + x - nr] = cons.buf[cons.y * cons.w + x]; + for (x = cons.x; x < cons.x + nr; x++) + cons.buf[cons.y * cons.w + x] = ' '; + draw_line(cons.y); +} + static void -do_con_trol(int ch) +do_con_trol(unsigned char ch) { unsigned int i, j; switch (ch) { + case 7: + // BEL + return; case 8: + // BS if (cons.x) cons.x--; return; - case 10 ... 12: + case 9: + // HT + cons.x = (cons.x + 8) & ~7; + return; + case 10: + // LF cons.x = 0; cons.y++; return; + case 12: + // FF + for (i = 0; i < cons.h; i++) { + for (j = 0; j < cons.w; j++) + cons.buf[i * cons.w + j] = ' '; + draw_line(i); + } + cons.x = cons.y = 0; + return; case 13: + // CR cons.x = 0; return; - case 24: - case 26: + case 25: + // EM + return; + case 24: // CAN + case 26: // SUB cons.vc_state = ESnormal; return; case 27: + // ESC cons.vc_state = ESesc; return; } + if (ch < 32) + DPRINTF("Unhandled control char %d\n", ch); switch (cons.vc_state) { case ESesc: @@ -196,7 +254,7 @@ scroll1(); return; default: - printk("Unhandled escape code '%c'\n", ch); + DPRINTF("Unhandled basic escape code '%c'\n", ch); return; } return; @@ -220,8 +278,37 @@ case ESgotpars: cons.vc_state = ESnormal; switch(ch) { + case 'A': + // Cursor up + if (cons.vc_par[0] == 0) + cons.vc_par[0] = 1; + if (cons.y - cons.vc_par[0] > 0) + cons.y -= cons.vc_par[0]; + return; + case 'B': + // Cursor down + if (cons.vc_par[0] == 0) + cons.vc_par[0] = 1; + if (cons.y + cons.vc_par[0] < cons.h - 1) + cons.y += cons.vc_par[0]; + return; + case 'C': + // Cursor right + if (cons.vc_par[0] == 0) + cons.vc_par[0] = 1; + if (cons.x + cons.vc_par[0] < cons.w - 1) + cons.x += cons.vc_par[0]; + return; + case 'D': + // Cursor left + if (cons.vc_par[0] == 0) + cons.vc_par[0] = 1; + if (cons.x - cons.vc_par[0] > 0) + cons.x -= cons.vc_par[0]; + return; case 'H': case 'f': + // Set cursor position if (cons.vc_par[0]) cons.vc_par[0]--; @@ -243,6 +330,8 @@ cons.buf[j * cons.w + i] = ' '; draw_line(j); } + } else { + DPRINTF("Unhandled CSI J code '%c'\n", cons.vc_par[0]); } return; case 'K': @@ -263,20 +352,26 @@ draw_line(cons.y); return; default: + DPRINTF("Unhandled CSI K code '%c'\n", cons.vc_par[0]); return; } return; case 'M': - scroll1(); + if (cons.vc_par[0] == 1) + scroll1(); + else + DPRINTF("Unhandled CSI M %d\n", cons.vc_par[0]); return; case 'm': + // Attributes are ignored return; case '@': + csi_at(cons.vc_par[0]); return; default: - printk("Unhandled escape code '%c', par[%d, %d, %d, %d, %d]\n", - ch, cons.vc_par[0], cons.vc_par[1], cons.vc_par[2], - cons.vc_par[3], cons.vc_par[4]); + DPRINTF("Unhandled escape code '%c', par[%d, %d, %d, %d, %d]\n", + ch, cons.vc_par[0], cons.vc_par[1], cons.vc_par[2], + cons.vc_par[3], cons.vc_par[4]); return; } return; @@ -290,7 +385,8 @@ int console_draw_str( const char *str ) { - int ch, y, x; + unsigned int y, x; + unsigned char ch; if( !cons.inited && console_init() ) return -1;

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r426 - in openbios-devel: arch/sparc32 drivers
by svn＠openbios.org 25 Jan '09

25 Jan '09

Author: blueswirl Date: 2009-01-25 13:20:12 +0100 (Sun, 25 Jan 2009) New Revision: 426 Modified: openbios-devel/arch/sparc32/entry.S openbios-devel/drivers/obio.c Log: Use RAM for SMP init instead of NVRAM Modified: openbios-devel/arch/sparc32/entry.S =================================================================== --- openbios-devel/arch/sparc32/entry.S 2009-01-25 09:56:08 UTC (rev 425) +++ openbios-devel/arch/sparc32/entry.S 2009-01-25 12:20:12 UTC (rev 426) @@ -10,25 +10,19 @@ #include "psr.h" #include "asm/asi.h" #include "asm/crs.h" -#define __ASSEMBLY__ -#include "openbios/firmware_abi.h" #define NO_QEMU_PROTOS #include "openbios/fw_cfg.h" #define CFG_ADDR 0x00000510 #define CFG_ASI 0x2d -#define PHYS_JJ_EEPROM 0x71200000 /* [2000] MK48T08 */ #define PHYS_JJ_INTR0 0x71E00000 /* CPU0 interrupt control registers */ -#define PHYS_SS10_EEPROM 0xf1200000 #define PHYS_SS10_INTR0 0xf1400000 -#define PHYS_SS2_EEPROM 0xf2000000 #define PHYS_SS2_INTR0 0xf5000000 #define SER_ADDR2 0xf1000004 -#define PHYS_SS1000_EEPROM 0x00280000 #define PHYS_SS1000_SBI 0x02800000 #define SER_ADDR1000 0x00200004 @@ -39,6 +33,40 @@ .section ".text", "ax" .align 8 + /* Memory map: + * + * Top +-------------------------+ + * | SMP CPU table | + * | s + 0xf00 ... 0xf0f | + * | s + 0xf0c valid | + * | s + 0xf08 entry | + * | s + 0xf04 ctxtbl | + * | s + 0xf00 ctx | + * +-------------------------+ + * | Bootstrap | + * | MMU L3 tables 5 * 0x100 | + * | s + 0xa00 ... 0xeff | + * +-------------------------+ + * | Bootstrap | + * | MMU L2 tables 2 * 0x100 | + * | s + 0x800 ... 0x9ff | + * +-------------------------+ + * | Bootstrap | + * | MMU L1 table 0x400 | + * | s + 0x400 ... 0x7ff | + * +-------------------------+ + * | Bootstrap | + * | MMU L0/ctx table 0x400 | + * | s + 0x000 ... 0x3ff | + * +-------------------------+ + * | | + * | ROM into RAM | + * | | + * +-------------------------+ + * : : + * Bottom + */ + /* * Entry point * We start execution from here. @@ -92,6 +120,16 @@ or %g3, %g4, %g1 ! %g1 contains end of memory + + ! Start of private memory in %g6 + set 0x1000, %g3 + sub %g1, %g3, %g6 + + ! Calculate SMP table location + add %g6, 0xf0c, %g2 ! valid? + lda [%g2] ASI_M_BYPASS, %g7 + sta %g0, [%g2] ASI_M_BYPASS + ! Get machine ID from configuration device mov FW_CFG_MACHINE_ID, %g2 sub %g5, 2, %g5 @@ -113,20 +151,12 @@ nop ! Ok, this is SS-5 - ! Find architecture specific part - set PHYS_JJ_EEPROM + OHW_ARCH_PTR, %g5 - lduha [%g5] ASI_M_BYPASS, %g2 - set PHYS_JJ_EEPROM, %g5 - add %g5, %g2, %g3 - ! Check if this not the first SMP CPU, if so, bypass PROM entirely - add %g3, SPARC_SMP_VALID, %g5 - lduba [%g5] ASI_M_BYPASS, %g2 - stba %g0, [%g5] ASI_M_BYPASS - tst %g2 + + tst %g7 bz first_cpu nop - ! SMP init, jump to user specified address + ! Clear softints used for SMP CPU startup set PHYS_JJ_INTR0 + 0x04, %g1 sll %g2, 12, %g2 add %g1, %g2, %g2 @@ -134,62 +164,41 @@ sta %g1, [%g2] ASI_M_BYPASS ! clear softints add %g2, 4, %g2 sta %g0, [%g2] ASI_M_BYPASS ! clear softints - add %g3, SPARC_SMP_CTXTBL, %g1 - lda [%g1] ASI_M_BYPASS, %g2 - sta %g0, [%g1] ASI_M_BYPASS + +load_ctx: + ! SMP init, jump to user specified address + add %g6, 0xf04, %g5 ! ctxtbl + lda [%g5] ASI_M_BYPASS, %g2 + sta %g0, [%g5] ASI_M_BYPASS set AC_M_CTPR, %g1 sta %g2, [%g1] ASI_M_MMUREGS ! set ctx table ptr - add %g3, SPARC_SMP_CTX, %g1 - lda [%g1] ASI_M_BYPASS, %g2 - sta %g0, [%g1] ASI_M_BYPASS + add %g6, 0xf00, %g5 ! ctx + lda [%g5] ASI_M_BYPASS, %g2 + sta %g0, [%g5] ASI_M_BYPASS set AC_M_CXR, %g1 sta %g2, [%g1] ASI_M_MMUREGS ! set context - add %g3, SPARC_SMP_ENTRY, %g1 - lda [%g1] ASI_M_BYPASS, %g2 - sta %g0, [%g1] ASI_M_BYPASS + add %g6, 0xf08, %g5 ! entry + lda [%g5] ASI_M_BYPASS, %g2 + sta %g0, [%g5] ASI_M_BYPASS set 1, %g1 jmp %g2 ! jump to kernel sta %g1, [%g0] ASI_M_MMUREGS ! enable mmu ss10: ! Ok, this is SS-10 or SS-600MP - ! Find architecture specific part - set PHYS_SS10_EEPROM + OHW_ARCH_PTR, %g5 - lduha [%g5] ASI_M_CTL, %g2 - set PHYS_SS10_EEPROM, %g5 - add %g5, %g2, %g3 - ! Check if this not the first SMP CPU, if so, bypass PROM entirely - add %g3, SPARC_SMP_VALID, %g5 - lduba [%g5] ASI_M_CTL, %g2 - stba %g0, [%g5] ASI_M_CTL - tst %g2 + tst %g7 bz first_cpu nop - ! SMP init, jump to user specified address + ! Clear softints used for SMP CPU startup set PHYS_SS10_INTR0 + 0x04, %g1 sll %g2, 12, %g2 add %g1, %g2, %g2 set 0xffffffff, %g1 - sta %g1, [%g2] ASI_M_CTL ! clear softints + sta %g1, [%g2] ASI_M_CTL ! clear softints add %g2, 4, %g2 - sta %g0, [%g2] ASI_M_CTL ! clear softints - add %g3, SPARC_SMP_CTXTBL, %g1 - lda [%g1] ASI_M_CTL, %g2 - sta %g0, [%g1] ASI_M_CTL - set AC_M_CTPR, %g1 - sta %g2, [%g1] ASI_M_MMUREGS ! set ctx table ptr - add %g3, SPARC_SMP_CTX, %g1 - lda [%g1] ASI_M_CTL, %g2 - sta %g0, [%g1] ASI_M_CTL - set AC_M_CXR, %g1 - sta %g2, [%g1] ASI_M_MMUREGS ! set context - add %g3, SPARC_SMP_ENTRY, %g1 - lda [%g1] ASI_M_CTL, %g2 - sta %g0, [%g1] ASI_M_CTL - set 1, %g1 - jmp %g2 ! jump to kernel - sta %g1, [%g0] ASI_M_MMUREGS ! enable mmu + b load_ctx + sta %g0, [%g2] ASI_M_CTL ! clear softints ss2: ! Ok, this is SS-2 @@ -206,16 +215,11 @@ first_cpu: /* Create temporary page tables and map the ROM area to end of RAM. This will be done properly in iommu.c later. */ - set _end, %g3 - set 0xfff, %g2 - add %g3, %g2, %g3 - andn %g3, %g2, %g3 - set _start, %g2 - sub %g3, %g2, %g3 - set 0x1000, %g4 ! add 0x1000 for page tables - add %g4, %g3, %g2 - sub %g1, %g2, %g2 ! start of private memory - srl %g2, 0x4, %g7 ! ctx table at s+0x0 + ! Calculate start of page tables etc. to %g6 + set 0x1000, %g4 + sub %g1, %g4, %g6 ! start of private memory + + mov %g6, %g2 ! ctx table at s+0x0 add %g2, 0x400, %g3 ! l1 table at s+0x400 srl %g3, 0x4, %g3 or %g3, 0x1, %g3 @@ -264,7 +268,7 @@ or %g3, 0x1, %g3 sta %g3, [%g2] ASI_M_BYPASS add %g2, 4, %g2 ! s+0x9e0 - add %g2, 0xd00 - 0x9e0, %g3 ! 5th l3 table for rom at s+0xe00 + add %g2, 0xe00 - 0x9e0, %g3 ! 5th l3 table for rom at s+0xe00 srl %g3, 0x4, %g3 or %g3, 0x1, %g3 sta %g3, [%g2] ASI_M_BYPASS @@ -275,10 +279,11 @@ set _end, %g6 set _start, %g4 sub %g6, %g4, %g6 + sub %g1, %g6, %g3 + set 0x1000, %g5 + sub %g3, %g5, %g3 ! start of ROM copy + mov %g3, %g7 ! save in %g7 srl %g6, 12, %g6 ! # of all pages - set 0x1000, %g5 - sll %g7, 0x4, %g3 - add %g5, %g3, %g3 ! ctx table + 0x1000 1: srl %g3, 0x4, %g4 or %g4, ((7 << 2) | 2), %g4 ! 7 = U: --- S: RWX sta %g4, [%g2] ASI_M_BYPASS @@ -291,10 +296,8 @@ mov %g1, %g6 ! %g6 = memory size /* Copy the code, rodata and data sections from ROM. */ - set 0x1000 - 4, %g4 - sll %g7, 0x4, %g3 - add %g4, %g3, %g3 ! ctx table + 0x1000 - 4 - set _start - 4, %g4 ! First address of TEXT + sub %g7, 4, %g3 + set _start - 4, %g4 ! First address of TEXT - 4 set _bss, %g5 ! Last address of DATA ba 2f nop @@ -307,8 +310,10 @@ bl 1b add %g4, 0x4, %g4 - + set 0x1000, %g3 + sub %g6, %g3, %g7 ! ctx table at s+0x0 set AC_M_CTPR, %g2 + srl %g7, 4, %g7 sta %g7, [%g2] ASI_M_MMUREGS ! set ctx table ptr set AC_M_CXR, %g2 sta %g0, [%g2] ASI_M_MMUREGS ! context 0 @@ -350,11 +355,15 @@ set qemu_mem_size, %g1 st %g6, [%g1] - sll %g7, 4, %g7 ! Store va->pa conversion factor - set _start - 0x1000, %g1 - sub %g1, %g7, %g7 + set _end, %o0 ! Store va->pa conversion factor + set _start, %o2 + sub %o0, %o2, %o0 + sub %g6, %o0, %o0 + set 0x1000, %o1 + sub %o0, %o1, %o0 ! start of ROM copy + sub %o2, %o0, %o0 ! start of ROM copy set va_shift, %g1 - st %g7, [%g1] + st %o0, [%g1] set qemu_machine_type, %g1 mov %y, %g2 Modified: openbios-devel/drivers/obio.c =================================================================== --- openbios-devel/drivers/obio.c 2009-01-25 09:56:08 UTC (rev 425) +++ openbios-devel/drivers/obio.c 2009-01-25 12:20:12 UTC (rev 426) @@ -1132,28 +1132,45 @@ fword("finish-device"); } +/* SMP CPU boot structure */ +struct smp_cfg { + uint32_t smp_ctx; + uint32_t smp_ctxtbl; + uint32_t smp_entry; + uint32_t valid; +}; + +static struct smp_cfg *smp_header; + int start_cpu(unsigned int pc, unsigned int context_ptr, unsigned int context, int cpu) { - ohwcfg_v3_t *header = (ohwcfg_v3_t *)nvram; - struct sparc_arch_cfg *sparc_header; - if (!cpu) return -1; - sparc_header = (struct sparc_arch_cfg *)&nvram[header->nvram_arch_ptr]; - sparc_header->smp_entry = pc; - sparc_header->smp_ctxtbl = context_ptr; - sparc_header->smp_ctx = context; - sparc_header->valid = 1; + cpu &= 7; - cpu &= 7; + smp_header->smp_entry = pc; + smp_header->smp_ctxtbl = context_ptr; + smp_header->smp_ctx = context; + smp_header->valid = cpu; + intregs->cpu_intregs[cpu].set = SUN4M_SOFT_INT(14); return 0; } +static void +ob_smp_init(void) +{ + unsigned long mem_size; + // See arch/sparc32/entry.S for memory layout + mem_size = fw_cfg_read_i32(FW_CFG_RAM_SIZE); + smp_header = (struct smp_cfg *)map_io((uint64_t)(mem_size - 0x100), + sizeof(struct smp_cfg)); +} + static void ob_obio_open(__attribute__((unused))int *idx) { @@ -1276,5 +1293,7 @@ ob_interrupt_init(slavio_base, intr_offset); + ob_smp_init(); + return 0; }

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