SerialICE March 2013

serialice@serialice.com

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Patch merged into serialice/master: 601fb79 Add support for Intel D946GZIS
by gerrit＠coreboot.org 26 Mar '13

26 Mar '13

the following patch was just integrated into master: commit 601fb7947a3e0dc6c4b9acd672f3bca9ae14ee47 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Sun Oct 14 07:28:44 2012 +0200 Add support for Intel D946GZIS Change-Id: I48056df9cef6b87987c2588c53b043794f900b83 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> Reviewed-on: http://review.coreboot.org/1579 Reviewed-by: Anton Kochkov <anton.kochkov(a)gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Mar 25 23:46:10 2013, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Mon Mar 25 23:09:43 2013, giving +2 See http://review.coreboot.org/1579 for details. -gerrit

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Patch merged into serialice/master: dc031cd Add support for Intel D945GNT
by gerrit＠coreboot.org 26 Mar '13

26 Mar '13

the following patch was just integrated into master: commit dc031cd14435eeee8cba796c8e59bc8e5f4ee620 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Mon Mar 25 20:45:39 2013 +0100 Add support for Intel D945GNT This is based on the patch from Beata dalHagen, see http://serialice.com/pipermail/serialice/2012-May/000372.html This version has only been compile tested. To share the code added by this and following patches of similar boards the file originally added for the D945GCLF is renamed to be more generic. Also, the Super I/O options get passed to the init function depending on the configured board. Change-Id: Ia4058d0f73f8357b97d7c0fe1868d9a289c4e2f7 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> Reviewed-on: http://review.coreboot.org/1578 Reviewed-by: Anton Kochkov <anton.kochkov(a)gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Mar 25 23:25:13 2013, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Mon Mar 25 23:08:48 2013, giving +2 See http://review.coreboot.org/1578 for details. -gerrit

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Patch set updated for serialice: cb678f2 SerialICE: move superio defines
by Idwer Vollering 26 Mar '13

26 Mar '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2911 -gerrit commit cb678f2ef913c0195ff840a71a95297528f0e4f7 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Tue Mar 26 01:08:46 2013 +0100 SerialICE: move superio defines Move local superio defines to a header file. Change-Id: Ic7a55a2b2848bc7f647e73b97f5cae4836c0e3c1 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- SerialICE/mainboard/amd_serengeti-cheetah.c | 17 +++++++------- SerialICE/mainboard/aopen_dxpl-plus.c | 26 ++++++++++----------- SerialICE/mainboard/asrock_775i65g.c | 18 +++++++-------- SerialICE/mainboard/asrock_939a785gmh.c | 16 ++++++------- SerialICE/mainboard/asrock_p4i65gv.c | 18 +++++++-------- SerialICE/mainboard/asus_f2a85-m.c | 20 ++++++++--------- SerialICE/mainboard/asus_k8v-x.c | 20 ++++++++--------- SerialICE/mainboard/asus_m2v-mx_se.c | 20 ++++++++--------- SerialICE/mainboard/asus_m4a77td-pro.c | 20 ++++++++--------- SerialICE/mainboard/asus_p4p800-vm.c | 18 +++++++-------- SerialICE/mainboard/commell_lv_672.c | 20 ++++++++--------- SerialICE/mainboard/hp_dl165_g6.c | 18 +++++++-------- SerialICE/mainboard/intel_d845gbv2.c | 16 ++++++------- SerialICE/mainboard/msi_ms6178.c | 16 ++++++------- SerialICE/mainboard/msi_ms7133.c | 18 +++++++-------- SerialICE/mainboard/televideo_tc7010.c | 35 +++++++++++++++-------------- SerialICE/mainboard/tyan_s2892.c | 17 +++++++------- SerialICE/mainboard/tyan_s2895.c | 7 +++--- SerialICE/mainboard/tyan_s2912.c | 17 +++++++------- SerialICE/mainboard/via_epia_m850.c | 14 ++++++------ SerialICE/superio.h | 6 +++++ 21 files changed, 190 insertions(+), 187 deletions(-) diff --git a/SerialICE/mainboard/amd_serengeti-cheetah.c b/SerialICE/mainboard/amd_serengeti-cheetah.c index bd35711..933e30e 100644 --- a/SerialICE/mainboard/amd_serengeti-cheetah.c +++ b/SerialICE/mainboard/amd_serengeti-cheetah.c @@ -20,22 +20,21 @@ const char boardname[] = "AMD SERENGETI CHEETAH"; -#define SUPERIO_CONFIG_PORT 0x2e -#define W83627HF_SP1 2 +#include "superio.h" static void superio_init(void) { int i; - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, W83627HF_SP1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, W83627HF_SP1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/aopen_dxpl-plus.c b/SerialICE/mainboard/aopen_dxpl-plus.c index 44cdb34..2f1d901 100644 --- a/SerialICE/mainboard/aopen_dxpl-plus.c +++ b/SerialICE/mainboard/aopen_dxpl-plus.c @@ -19,7 +19,7 @@ const char boardname[] = "AOpen DXPL Plus"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" /* Hardware specific functions */ static void southbridge_init(void) @@ -42,24 +42,24 @@ static void southbridge_init(void) static void superio_init(void) { - pnp_enter_ext_func_mode_alt(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode_alt(SUPERIO_CONFIG_PORT_2eh); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 4); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 4); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); #if 0 /* Must route GPIO to UART2 before enabling this */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 5); /* COM2 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x2f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 3); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 5); /* COM2 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x2f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 3); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); #endif - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/asrock_775i65g.c b/SerialICE/mainboard/asrock_775i65g.c index 27d1c36..9870e45 100644 --- a/SerialICE/mainboard/asrock_775i65g.c +++ b/SerialICE/mainboard/asrock_775i65g.c @@ -19,7 +19,7 @@ const char boardname[] = "ASRock 775i65G"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" /* Hardware specific functions */ static void mainboard_set_ich5(void) @@ -39,15 +39,15 @@ static void mainboard_set_ich5(void) /* Winbond W83627HG */ static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Set the clock to 48MHz */ - pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0xc0); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x24, 0xc0); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/asrock_939a785gmh.c b/SerialICE/mainboard/asrock_939a785gmh.c index d44a50b..0c92a60 100644 --- a/SerialICE/mainboard/asrock_939a785gmh.c +++ b/SerialICE/mainboard/asrock_939a785gmh.c @@ -20,20 +20,20 @@ const char boardname[] = "Asrock 939a785gmh"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/asrock_p4i65gv.c b/SerialICE/mainboard/asrock_p4i65gv.c index ccb40ec..8cffca0 100644 --- a/SerialICE/mainboard/asrock_p4i65gv.c +++ b/SerialICE/mainboard/asrock_p4i65gv.c @@ -19,7 +19,7 @@ const char boardname[] = "ASRock P4i65GV"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" /* Hardware specific functions */ static void mainboard_set_ich5(void) @@ -39,15 +39,15 @@ static void mainboard_set_ich5(void) /* Winbond W83627HG */ static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Set the clock to 48MHz */ - pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0xc0); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x24, 0xc0); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/asus_f2a85-m.c b/SerialICE/mainboard/asus_f2a85-m.c index 53a75b6..af1b14e 100644 --- a/SerialICE/mainboard/asus_f2a85-m.c +++ b/SerialICE/mainboard/asus_f2a85-m.c @@ -20,25 +20,25 @@ const char boardname[] = "Asus F2A85-M"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" static void superio_init(void) { u8 byte; - pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT_2eh); /* Disable the watchdog. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7); - pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 7); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x72, 0x00); /* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT_2eh); } diff --git a/SerialICE/mainboard/asus_k8v-x.c b/SerialICE/mainboard/asus_k8v-x.c index df010c9..7e3ee5f 100644 --- a/SerialICE/mainboard/asus_k8v-x.c +++ b/SerialICE/mainboard/asus_k8v-x.c @@ -20,24 +20,24 @@ const char boardname[] = "ASUS K8V-X"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Disable the watchdog. */ -// pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7); -// pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00); +// pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 7); +// pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x72, 0x00); /* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/asus_m2v-mx_se.c b/SerialICE/mainboard/asus_m2v-mx_se.c index ab2a289..7d98739 100644 --- a/SerialICE/mainboard/asus_m2v-mx_se.c +++ b/SerialICE/mainboard/asus_m2v-mx_se.c @@ -20,24 +20,24 @@ const char boardname[] = "ASUS M2V-MX SE"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" static void superio_init(void) { - pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT_2eh); /* Disable the watchdog. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7); - pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 7); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x72, 0x00); /* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/asus_m4a77td-pro.c b/SerialICE/mainboard/asus_m4a77td-pro.c index b41c97d..2c9ab34 100644 --- a/SerialICE/mainboard/asus_m4a77td-pro.c +++ b/SerialICE/mainboard/asus_m4a77td-pro.c @@ -21,24 +21,24 @@ const char boardname[] = "ASUS M4A77TD-PRO"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" static void superio_init(void) { - pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT_2eh); /* Disable the watchdog. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7); - pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 7); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x72, 0x00); /* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/asus_p4p800-vm.c b/SerialICE/mainboard/asus_p4p800-vm.c index 9208870..8a59f7d 100644 --- a/SerialICE/mainboard/asus_p4p800-vm.c +++ b/SerialICE/mainboard/asus_p4p800-vm.c @@ -19,7 +19,7 @@ const char boardname[] = "ASUS P4P800-VM"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" /* Hardware specific functions */ static void mainboard_set_ich5(void) @@ -39,15 +39,15 @@ static void mainboard_set_ich5(void) /* Winbond W83627THF */ static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Set the clock to 48MHz */ - pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0x42); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x24, 0x42); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/commell_lv_672.c b/SerialICE/mainboard/commell_lv_672.c index 047bc9f..0c8d6cd 100644 --- a/SerialICE/mainboard/commell_lv_672.c +++ b/SerialICE/mainboard/commell_lv_672.c @@ -19,7 +19,7 @@ const char boardname[] = "Commell LV-672"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" /* Hardware specific functions */ static void southbridge_init(void) @@ -49,19 +49,19 @@ static void southbridge_init(void) static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Settings for Winbond W83627THF/THG */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 0); - pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0xc2); /* Select oscillator */ + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x24, 0xc2); /* Select oscillator */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/hp_dl165_g6.c b/SerialICE/mainboard/hp_dl165_g6.c index 745bf26..f1f70fe 100644 --- a/SerialICE/mainboard/hp_dl165_g6.c +++ b/SerialICE/mainboard/hp_dl165_g6.c @@ -21,9 +21,7 @@ const char boardname[] = "HP DL165 G6"; -#define SCH4307_CONFIG_PORT 0x162e -#define SUPERIO_CONFIG_PORT 0x2e -#define SUPERIO_SP1 2 +#include "superio.h" static void superio_init(void) { @@ -45,13 +43,13 @@ static void superio_init(void) pnp_exit_ext_func_mode(SCH4307_CONFIG_PORT); /* Enable the serial port. */ - outb(0x5a, SUPERIO_CONFIG_PORT); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, SUPERIO_SP1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); - outb(0xa5, SUPERIO_CONFIG_PORT); + outb(0x5a, SUPERIO_CONFIG_PORT_2eh); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, SUPERIO_SP1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); + outb(0xa5, SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/intel_d845gbv2.c b/SerialICE/mainboard/intel_d845gbv2.c index 6cbd703..aaf1cf8 100644 --- a/SerialICE/mainboard/intel_d845gbv2.c +++ b/SerialICE/mainboard/intel_d845gbv2.c @@ -19,7 +19,7 @@ const char boardname[] = "Intel D845GBV2"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" /* Hardware specific functions */ static void southbridge_init(void) @@ -39,16 +39,16 @@ static void southbridge_init(void) static void superio_init(void) { - pnp_enter_ext_func_mode_alt(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode_alt(SUPERIO_CONFIG_PORT_2eh); /* Settings for LPC47M172 with LD_NUM = 0. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 3); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 3); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/msi_ms6178.c b/SerialICE/mainboard/msi_ms6178.c index fd4af8f..639994f 100644 --- a/SerialICE/mainboard/msi_ms6178.c +++ b/SerialICE/mainboard/msi_ms6178.c @@ -30,7 +30,7 @@ const char boardname[] = "MSI MS6178"; #define TCO2_STS (TCOBASE + 0x06) #define TCO1_CNT (TCOBASE + 0x08) -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" static void southbridge_init(void) { @@ -53,16 +53,16 @@ static void southbridge_init(void) static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Set CLKSEL=1 to select 48 MHz (otherwise serial won't work). */ - pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0xc4); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x24, 0xc4); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); pnp_exit_ext_func_mode(0x2e); } diff --git a/SerialICE/mainboard/msi_ms7133.c b/SerialICE/mainboard/msi_ms7133.c index 1248f78..687d20c 100644 --- a/SerialICE/mainboard/msi_ms7133.c +++ b/SerialICE/mainboard/msi_ms7133.c @@ -31,7 +31,7 @@ const char boardname[] = "MSI MS7133"; #define TCO2_STS (TCOBASE + 0x06) #define TCO1_CNT (TCOBASE + 0x08) -#define SUPERIO_CONFIG_PORT 0x4e +#include "superio.h" static void southbridge_init(void) { @@ -54,18 +54,18 @@ static void southbridge_init(void) static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_4eh); /* Set CLKSEL=1 to select 48 MHz (otherwise serial won't work). */ - pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0xc6); + pnp_write_register(SUPERIO_CONFIG_PORT_4eh, 0x24, 0xc6); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_4eh, 2); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_4eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_4eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_4eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_4eh, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_4eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/televideo_tc7010.c b/SerialICE/mainboard/televideo_tc7010.c index a915387..5c92437 100644 --- a/SerialICE/mainboard/televideo_tc7010.c +++ b/SerialICE/mainboard/televideo_tc7010.c @@ -19,16 +19,17 @@ const char boardname[] = "Televideo TC7010"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" + #define PM_BASE 0xe8 static void superio_init(void) { /* Set base address of power management unit */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 8); - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, PM_BASE); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 8); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, PM_BASE); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); /* Use on-chip clock multiplier */ outb(0x03, PM_BASE); @@ -38,20 +39,20 @@ static void superio_init(void) while (!(inb(PM_BASE + 1) & 0x80)) ; /* Enable the serial ports. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 6); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 6); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); /* Set LDN 5 UART Mode */ - outb(0x21, SUPERIO_CONFIG_PORT); - outb(inb(SUPERIO_CONFIG_PORT + 1) | (1 << 3), SUPERIO_CONFIG_PORT + 1); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 5); /* COM2 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x2f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 3); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + outb(0x21, SUPERIO_CONFIG_PORT_2eh); + outb(inb(SUPERIO_CONFIG_PORT_2eh + 1) | (1 << 3), SUPERIO_CONFIG_PORT_2eh + 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 5); /* COM2 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x2f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 3); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); } static void chipset_init(void) diff --git a/SerialICE/mainboard/tyan_s2892.c b/SerialICE/mainboard/tyan_s2892.c index 043ebf7..bb4427a 100644 --- a/SerialICE/mainboard/tyan_s2892.c +++ b/SerialICE/mainboard/tyan_s2892.c @@ -20,8 +20,7 @@ const char boardname[] = "Tyan S2892"; -#define SUPERIO_CONFIG_PORT 0x2e -#define W83627HF_SP1 2 +#include "superio.h" static void sio_setup(void) { @@ -41,16 +40,16 @@ static void sio_setup(void) static void superio_init(void) { int i; - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, W83627HF_SP1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, CONFIG_SERIAL_PORT); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, W83627HF_SP1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, CONFIG_SERIAL_PORT); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/tyan_s2895.c b/SerialICE/mainboard/tyan_s2895.c index 8606bbe..08093f7 100644 --- a/SerialICE/mainboard/tyan_s2895.c +++ b/SerialICE/mainboard/tyan_s2895.c @@ -20,7 +20,8 @@ const char boardname[] = "Tyan S2895"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" + #define SUPERIO_GPIO_IO_BASE 0x400 #define LPC47B397_SP1 4 /* Com1 */ @@ -68,7 +69,7 @@ static void superio_init(void) dword |= (1<<16); pci_write_config32(PCI_ADDR(0, 1, 0, 0xa4), dword); - smsc_enable_serial(SUPERIO_CONFIG_PORT, LPC47B397_RT, SUPERIO_GPIO_IO_BASE); + smsc_enable_serial(SUPERIO_CONFIG_PORT_2eh, LPC47B397_RT, SUPERIO_GPIO_IO_BASE); value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77); value &= 0xbf; lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); @@ -77,7 +78,7 @@ static void superio_init(void) static void chipset_init(void) { superio_init(); - smsc_enable_serial(SUPERIO_CONFIG_PORT, LPC47B397_SP1, CONFIG_SERIAL_PORT); + smsc_enable_serial(SUPERIO_CONFIG_PORT_2eh, LPC47B397_SP1, CONFIG_SERIAL_PORT); __asm__ __volatile__("\ jmp skip\n\ .align 128\n\ diff --git a/SerialICE/mainboard/tyan_s2912.c b/SerialICE/mainboard/tyan_s2912.c index 77b5d29..9d74a18 100644 --- a/SerialICE/mainboard/tyan_s2912.c +++ b/SerialICE/mainboard/tyan_s2912.c @@ -20,22 +20,21 @@ const char boardname[] = "Tyan S2912"; -#define SUPERIO_CONFIG_PORT 0x2e -#define W83627HF_SP1 2 +#include "superio.h" static void superio_init(void) { int i; - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, W83627HF_SP1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, W83627HF_SP1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/via_epia_m850.c b/SerialICE/mainboard/via_epia_m850.c index 55c2574..89c1335 100644 --- a/SerialICE/mainboard/via_epia_m850.c +++ b/SerialICE/mainboard/via_epia_m850.c @@ -19,7 +19,7 @@ const char boardname[] = "VIA EPIA M-850"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" static inline void pnp_enter_conf_state(u16 port) { @@ -34,12 +34,12 @@ static inline void pnp_exit_conf_state(u16 port) static void superio_init(void) { - pnp_enter_conf_state(SUPERIO_CONFIG_PORT); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 0); - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x03f8); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); - pnp_exit_conf_state(SUPERIO_CONFIG_PORT); + pnp_enter_conf_state(SUPERIO_CONFIG_PORT_2eh); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x03f8); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); + pnp_exit_conf_state(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/superio.h b/SerialICE/superio.h new file mode 100644 index 0000000..9edca27 --- /dev/null +++ b/SerialICE/superio.h @@ -0,0 +1,6 @@ +#define SUPERIO_CONFIG_PORT_2eh 0x2e +#define SUPERIO_CONFIG_PORT_4eh 0x4e +#define W83627HF_SP1 2 + +#define SCH4307_CONFIG_PORT 0x162e +#define SUPERIO_SP1 2

1 0

Patch set updated for serialice: 90bead1 SerialICE: move superio defines
by Idwer Vollering 26 Mar '13

26 Mar '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2911 -gerrit commit 90bead1b28238bde73cf396e41b5b6611fde9eb8 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Tue Mar 26 01:08:46 2013 +0100 SerialICE: move superio defines Move local superio defines to a header file. Change-Id: Ic7a55a2b2848bc7f647e73b97f5cae4836c0e3c1 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- SerialICE/mainboard/amd_serengeti-cheetah.c | 17 +++++++------- SerialICE/mainboard/aopen_dxpl-plus.c | 26 ++++++++++----------- SerialICE/mainboard/asrock_775i65g.c | 18 +++++++-------- SerialICE/mainboard/asrock_939a785gmh.c | 16 ++++++------- SerialICE/mainboard/asrock_p4i65gv.c | 18 +++++++-------- SerialICE/mainboard/asus_f2a85-m.c | 20 ++++++++--------- SerialICE/mainboard/asus_k8v-x.c | 20 ++++++++--------- SerialICE/mainboard/asus_m2v-mx_se.c | 20 ++++++++--------- SerialICE/mainboard/asus_m4a77td-pro.c | 20 ++++++++--------- SerialICE/mainboard/asus_p4p800-vm.c | 18 +++++++-------- SerialICE/mainboard/commell_lv_672.c | 20 ++++++++--------- SerialICE/mainboard/hp_dl165_g6.c | 18 +++++++-------- SerialICE/mainboard/intel_d845gbv2.c | 16 ++++++------- SerialICE/mainboard/msi_ms6178.c | 16 ++++++------- SerialICE/mainboard/msi_ms7133.c | 18 +++++++-------- SerialICE/mainboard/televideo_tc7010.c | 35 +++++++++++++++-------------- SerialICE/mainboard/tyan_s2892.c | 17 +++++++------- SerialICE/mainboard/tyan_s2895.c | 5 ++--- SerialICE/mainboard/tyan_s2912.c | 17 +++++++------- SerialICE/mainboard/via_epia_m850.c | 14 ++++++------ SerialICE/superio.h | 6 +++++ 21 files changed, 188 insertions(+), 187 deletions(-) diff --git a/SerialICE/mainboard/amd_serengeti-cheetah.c b/SerialICE/mainboard/amd_serengeti-cheetah.c index bd35711..933e30e 100644 --- a/SerialICE/mainboard/amd_serengeti-cheetah.c +++ b/SerialICE/mainboard/amd_serengeti-cheetah.c @@ -20,22 +20,21 @@ const char boardname[] = "AMD SERENGETI CHEETAH"; -#define SUPERIO_CONFIG_PORT 0x2e -#define W83627HF_SP1 2 +#include "superio.h" static void superio_init(void) { int i; - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, W83627HF_SP1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, W83627HF_SP1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/aopen_dxpl-plus.c b/SerialICE/mainboard/aopen_dxpl-plus.c index 44cdb34..2f1d901 100644 --- a/SerialICE/mainboard/aopen_dxpl-plus.c +++ b/SerialICE/mainboard/aopen_dxpl-plus.c @@ -19,7 +19,7 @@ const char boardname[] = "AOpen DXPL Plus"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" /* Hardware specific functions */ static void southbridge_init(void) @@ -42,24 +42,24 @@ static void southbridge_init(void) static void superio_init(void) { - pnp_enter_ext_func_mode_alt(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode_alt(SUPERIO_CONFIG_PORT_2eh); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 4); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 4); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); #if 0 /* Must route GPIO to UART2 before enabling this */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 5); /* COM2 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x2f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 3); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 5); /* COM2 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x2f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 3); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); #endif - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/asrock_775i65g.c b/SerialICE/mainboard/asrock_775i65g.c index 27d1c36..9870e45 100644 --- a/SerialICE/mainboard/asrock_775i65g.c +++ b/SerialICE/mainboard/asrock_775i65g.c @@ -19,7 +19,7 @@ const char boardname[] = "ASRock 775i65G"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" /* Hardware specific functions */ static void mainboard_set_ich5(void) @@ -39,15 +39,15 @@ static void mainboard_set_ich5(void) /* Winbond W83627HG */ static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Set the clock to 48MHz */ - pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0xc0); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x24, 0xc0); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/asrock_939a785gmh.c b/SerialICE/mainboard/asrock_939a785gmh.c index d44a50b..0c92a60 100644 --- a/SerialICE/mainboard/asrock_939a785gmh.c +++ b/SerialICE/mainboard/asrock_939a785gmh.c @@ -20,20 +20,20 @@ const char boardname[] = "Asrock 939a785gmh"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/asrock_p4i65gv.c b/SerialICE/mainboard/asrock_p4i65gv.c index ccb40ec..8cffca0 100644 --- a/SerialICE/mainboard/asrock_p4i65gv.c +++ b/SerialICE/mainboard/asrock_p4i65gv.c @@ -19,7 +19,7 @@ const char boardname[] = "ASRock P4i65GV"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" /* Hardware specific functions */ static void mainboard_set_ich5(void) @@ -39,15 +39,15 @@ static void mainboard_set_ich5(void) /* Winbond W83627HG */ static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Set the clock to 48MHz */ - pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0xc0); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x24, 0xc0); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/asus_f2a85-m.c b/SerialICE/mainboard/asus_f2a85-m.c index 53a75b6..af1b14e 100644 --- a/SerialICE/mainboard/asus_f2a85-m.c +++ b/SerialICE/mainboard/asus_f2a85-m.c @@ -20,25 +20,25 @@ const char boardname[] = "Asus F2A85-M"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" static void superio_init(void) { u8 byte; - pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT_2eh); /* Disable the watchdog. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7); - pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 7); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x72, 0x00); /* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT_2eh); } diff --git a/SerialICE/mainboard/asus_k8v-x.c b/SerialICE/mainboard/asus_k8v-x.c index df010c9..7e3ee5f 100644 --- a/SerialICE/mainboard/asus_k8v-x.c +++ b/SerialICE/mainboard/asus_k8v-x.c @@ -20,24 +20,24 @@ const char boardname[] = "ASUS K8V-X"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Disable the watchdog. */ -// pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7); -// pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00); +// pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 7); +// pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x72, 0x00); /* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/asus_m2v-mx_se.c b/SerialICE/mainboard/asus_m2v-mx_se.c index ab2a289..7d98739 100644 --- a/SerialICE/mainboard/asus_m2v-mx_se.c +++ b/SerialICE/mainboard/asus_m2v-mx_se.c @@ -20,24 +20,24 @@ const char boardname[] = "ASUS M2V-MX SE"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" static void superio_init(void) { - pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT_2eh); /* Disable the watchdog. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7); - pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 7); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x72, 0x00); /* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/asus_m4a77td-pro.c b/SerialICE/mainboard/asus_m4a77td-pro.c index b41c97d..2c9ab34 100644 --- a/SerialICE/mainboard/asus_m4a77td-pro.c +++ b/SerialICE/mainboard/asus_m4a77td-pro.c @@ -21,24 +21,24 @@ const char boardname[] = "ASUS M4A77TD-PRO"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" static void superio_init(void) { - pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT_2eh); /* Disable the watchdog. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7); - pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 7); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x72, 0x00); /* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/asus_p4p800-vm.c b/SerialICE/mainboard/asus_p4p800-vm.c index 9208870..8a59f7d 100644 --- a/SerialICE/mainboard/asus_p4p800-vm.c +++ b/SerialICE/mainboard/asus_p4p800-vm.c @@ -19,7 +19,7 @@ const char boardname[] = "ASUS P4P800-VM"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" /* Hardware specific functions */ static void mainboard_set_ich5(void) @@ -39,15 +39,15 @@ static void mainboard_set_ich5(void) /* Winbond W83627THF */ static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Set the clock to 48MHz */ - pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0x42); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x24, 0x42); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/commell_lv_672.c b/SerialICE/mainboard/commell_lv_672.c index 047bc9f..0c8d6cd 100644 --- a/SerialICE/mainboard/commell_lv_672.c +++ b/SerialICE/mainboard/commell_lv_672.c @@ -19,7 +19,7 @@ const char boardname[] = "Commell LV-672"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" /* Hardware specific functions */ static void southbridge_init(void) @@ -49,19 +49,19 @@ static void southbridge_init(void) static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Settings for Winbond W83627THF/THG */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 0); - pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0xc2); /* Select oscillator */ + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x24, 0xc2); /* Select oscillator */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/hp_dl165_g6.c b/SerialICE/mainboard/hp_dl165_g6.c index 745bf26..f1f70fe 100644 --- a/SerialICE/mainboard/hp_dl165_g6.c +++ b/SerialICE/mainboard/hp_dl165_g6.c @@ -21,9 +21,7 @@ const char boardname[] = "HP DL165 G6"; -#define SCH4307_CONFIG_PORT 0x162e -#define SUPERIO_CONFIG_PORT 0x2e -#define SUPERIO_SP1 2 +#include "superio.h" static void superio_init(void) { @@ -45,13 +43,13 @@ static void superio_init(void) pnp_exit_ext_func_mode(SCH4307_CONFIG_PORT); /* Enable the serial port. */ - outb(0x5a, SUPERIO_CONFIG_PORT); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, SUPERIO_SP1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); - outb(0xa5, SUPERIO_CONFIG_PORT); + outb(0x5a, SUPERIO_CONFIG_PORT_2eh); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, SUPERIO_SP1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); + outb(0xa5, SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/intel_d845gbv2.c b/SerialICE/mainboard/intel_d845gbv2.c index 6cbd703..aaf1cf8 100644 --- a/SerialICE/mainboard/intel_d845gbv2.c +++ b/SerialICE/mainboard/intel_d845gbv2.c @@ -19,7 +19,7 @@ const char boardname[] = "Intel D845GBV2"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" /* Hardware specific functions */ static void southbridge_init(void) @@ -39,16 +39,16 @@ static void southbridge_init(void) static void superio_init(void) { - pnp_enter_ext_func_mode_alt(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode_alt(SUPERIO_CONFIG_PORT_2eh); /* Settings for LPC47M172 with LD_NUM = 0. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 3); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 3); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/msi_ms6178.c b/SerialICE/mainboard/msi_ms6178.c index fd4af8f..639994f 100644 --- a/SerialICE/mainboard/msi_ms6178.c +++ b/SerialICE/mainboard/msi_ms6178.c @@ -30,7 +30,7 @@ const char boardname[] = "MSI MS6178"; #define TCO2_STS (TCOBASE + 0x06) #define TCO1_CNT (TCOBASE + 0x08) -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" static void southbridge_init(void) { @@ -53,16 +53,16 @@ static void southbridge_init(void) static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Set CLKSEL=1 to select 48 MHz (otherwise serial won't work). */ - pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0xc4); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x24, 0xc4); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); pnp_exit_ext_func_mode(0x2e); } diff --git a/SerialICE/mainboard/msi_ms7133.c b/SerialICE/mainboard/msi_ms7133.c index 1248f78..687d20c 100644 --- a/SerialICE/mainboard/msi_ms7133.c +++ b/SerialICE/mainboard/msi_ms7133.c @@ -31,7 +31,7 @@ const char boardname[] = "MSI MS7133"; #define TCO2_STS (TCOBASE + 0x06) #define TCO1_CNT (TCOBASE + 0x08) -#define SUPERIO_CONFIG_PORT 0x4e +#include "superio.h" static void southbridge_init(void) { @@ -54,18 +54,18 @@ static void southbridge_init(void) static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_4eh); /* Set CLKSEL=1 to select 48 MHz (otherwise serial won't work). */ - pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0xc6); + pnp_write_register(SUPERIO_CONFIG_PORT_4eh, 0x24, 0xc6); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_4eh, 2); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_4eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_4eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_4eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_4eh, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_4eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/televideo_tc7010.c b/SerialICE/mainboard/televideo_tc7010.c index a915387..5c92437 100644 --- a/SerialICE/mainboard/televideo_tc7010.c +++ b/SerialICE/mainboard/televideo_tc7010.c @@ -19,16 +19,17 @@ const char boardname[] = "Televideo TC7010"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" + #define PM_BASE 0xe8 static void superio_init(void) { /* Set base address of power management unit */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 8); - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, PM_BASE); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 8); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, PM_BASE); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); /* Use on-chip clock multiplier */ outb(0x03, PM_BASE); @@ -38,20 +39,20 @@ static void superio_init(void) while (!(inb(PM_BASE + 1) & 0x80)) ; /* Enable the serial ports. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 6); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 6); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); /* Set LDN 5 UART Mode */ - outb(0x21, SUPERIO_CONFIG_PORT); - outb(inb(SUPERIO_CONFIG_PORT + 1) | (1 << 3), SUPERIO_CONFIG_PORT + 1); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 5); /* COM2 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x2f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 3); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + outb(0x21, SUPERIO_CONFIG_PORT_2eh); + outb(inb(SUPERIO_CONFIG_PORT_2eh + 1) | (1 << 3), SUPERIO_CONFIG_PORT_2eh + 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 5); /* COM2 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x2f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 3); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); } static void chipset_init(void) diff --git a/SerialICE/mainboard/tyan_s2892.c b/SerialICE/mainboard/tyan_s2892.c index 043ebf7..bb4427a 100644 --- a/SerialICE/mainboard/tyan_s2892.c +++ b/SerialICE/mainboard/tyan_s2892.c @@ -20,8 +20,7 @@ const char boardname[] = "Tyan S2892"; -#define SUPERIO_CONFIG_PORT 0x2e -#define W83627HF_SP1 2 +#include "superio.h" static void sio_setup(void) { @@ -41,16 +40,16 @@ static void sio_setup(void) static void superio_init(void) { int i; - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, W83627HF_SP1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, CONFIG_SERIAL_PORT); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, W83627HF_SP1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, CONFIG_SERIAL_PORT); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/tyan_s2895.c b/SerialICE/mainboard/tyan_s2895.c index 8606bbe..edc4920 100644 --- a/SerialICE/mainboard/tyan_s2895.c +++ b/SerialICE/mainboard/tyan_s2895.c @@ -20,7 +20,6 @@ const char boardname[] = "Tyan S2895"; -#define SUPERIO_CONFIG_PORT 0x2e #define SUPERIO_GPIO_IO_BASE 0x400 #define LPC47B397_SP1 4 /* Com1 */ @@ -68,7 +67,7 @@ static void superio_init(void) dword |= (1<<16); pci_write_config32(PCI_ADDR(0, 1, 0, 0xa4), dword); - smsc_enable_serial(SUPERIO_CONFIG_PORT, LPC47B397_RT, SUPERIO_GPIO_IO_BASE); + smsc_enable_serial(SUPERIO_CONFIG_PORT_2eh, LPC47B397_RT, SUPERIO_GPIO_IO_BASE); value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77); value &= 0xbf; lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); @@ -77,7 +76,7 @@ static void superio_init(void) static void chipset_init(void) { superio_init(); - smsc_enable_serial(SUPERIO_CONFIG_PORT, LPC47B397_SP1, CONFIG_SERIAL_PORT); + smsc_enable_serial(SUPERIO_CONFIG_PORT_2eh, LPC47B397_SP1, CONFIG_SERIAL_PORT); __asm__ __volatile__("\ jmp skip\n\ .align 128\n\ diff --git a/SerialICE/mainboard/tyan_s2912.c b/SerialICE/mainboard/tyan_s2912.c index 77b5d29..9d74a18 100644 --- a/SerialICE/mainboard/tyan_s2912.c +++ b/SerialICE/mainboard/tyan_s2912.c @@ -20,22 +20,21 @@ const char boardname[] = "Tyan S2912"; -#define SUPERIO_CONFIG_PORT 0x2e -#define W83627HF_SP1 2 +#include "superio.h" static void superio_init(void) { int i; - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, W83627HF_SP1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, W83627HF_SP1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/via_epia_m850.c b/SerialICE/mainboard/via_epia_m850.c index 55c2574..89c1335 100644 --- a/SerialICE/mainboard/via_epia_m850.c +++ b/SerialICE/mainboard/via_epia_m850.c @@ -19,7 +19,7 @@ const char boardname[] = "VIA EPIA M-850"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" static inline void pnp_enter_conf_state(u16 port) { @@ -34,12 +34,12 @@ static inline void pnp_exit_conf_state(u16 port) static void superio_init(void) { - pnp_enter_conf_state(SUPERIO_CONFIG_PORT); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 0); - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x03f8); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); - pnp_exit_conf_state(SUPERIO_CONFIG_PORT); + pnp_enter_conf_state(SUPERIO_CONFIG_PORT_2eh); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x03f8); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); + pnp_exit_conf_state(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/superio.h b/SerialICE/superio.h new file mode 100644 index 0000000..9edca27 --- /dev/null +++ b/SerialICE/superio.h @@ -0,0 +1,6 @@ +#define SUPERIO_CONFIG_PORT_2eh 0x2e +#define SUPERIO_CONFIG_PORT_4eh 0x4e +#define W83627HF_SP1 2 + +#define SCH4307_CONFIG_PORT 0x162e +#define SUPERIO_SP1 2

1 0

New patch to review for serialice: 3f2c789 SerialICE: move superio defines
by Idwer Vollering 26 Mar '13

26 Mar '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2911 -gerrit commit 3f2c7897a318d4ad6dec08f6817fc7fa4ece1f81 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Tue Mar 26 01:08:46 2013 +0100 SerialICE: move superio defines Move local superio defines to a header file. Change-Id: Ic7a55a2b2848bc7f647e73b97f5cae4836c0e3c1 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- SerialICE/mainboard/amd_serengeti-cheetah.c | 17 +++++++------- SerialICE/mainboard/aopen_dxpl-plus.c | 26 ++++++++++----------- SerialICE/mainboard/asrock_775i65g.c | 18 +++++++-------- SerialICE/mainboard/asrock_939a785gmh.c | 16 ++++++------- SerialICE/mainboard/asrock_p4i65gv.c | 18 +++++++-------- SerialICE/mainboard/asus_f2a85-m.c | 20 ++++++++--------- SerialICE/mainboard/asus_k8v-x.c | 20 ++++++++--------- SerialICE/mainboard/asus_m2v-mx_se.c | 20 ++++++++--------- SerialICE/mainboard/asus_m4a77td-pro.c | 20 ++++++++--------- SerialICE/mainboard/asus_p4p800-vm.c | 18 +++++++-------- SerialICE/mainboard/commell_lv_672.c | 20 ++++++++--------- SerialICE/mainboard/hp_dl165_g6.c | 18 +++++++-------- SerialICE/mainboard/intel_d845gbv2.c | 16 ++++++------- SerialICE/mainboard/msi_ms6178.c | 16 ++++++------- SerialICE/mainboard/msi_ms7133.c | 2 +- SerialICE/mainboard/televideo_tc7010.c | 35 +++++++++++++++-------------- SerialICE/mainboard/tyan_s2892.c | 17 +++++++------- SerialICE/mainboard/tyan_s2895.c | 5 ++--- SerialICE/mainboard/tyan_s2912.c | 17 +++++++------- SerialICE/mainboard/via_epia_m850.c | 14 ++++++------ SerialICE/superio.h | 6 +++++ 21 files changed, 180 insertions(+), 179 deletions(-) diff --git a/SerialICE/mainboard/amd_serengeti-cheetah.c b/SerialICE/mainboard/amd_serengeti-cheetah.c index bd35711..933e30e 100644 --- a/SerialICE/mainboard/amd_serengeti-cheetah.c +++ b/SerialICE/mainboard/amd_serengeti-cheetah.c @@ -20,22 +20,21 @@ const char boardname[] = "AMD SERENGETI CHEETAH"; -#define SUPERIO_CONFIG_PORT 0x2e -#define W83627HF_SP1 2 +#include "superio.h" static void superio_init(void) { int i; - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, W83627HF_SP1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, W83627HF_SP1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/aopen_dxpl-plus.c b/SerialICE/mainboard/aopen_dxpl-plus.c index 44cdb34..2f1d901 100644 --- a/SerialICE/mainboard/aopen_dxpl-plus.c +++ b/SerialICE/mainboard/aopen_dxpl-plus.c @@ -19,7 +19,7 @@ const char boardname[] = "AOpen DXPL Plus"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" /* Hardware specific functions */ static void southbridge_init(void) @@ -42,24 +42,24 @@ static void southbridge_init(void) static void superio_init(void) { - pnp_enter_ext_func_mode_alt(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode_alt(SUPERIO_CONFIG_PORT_2eh); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 4); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 4); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); #if 0 /* Must route GPIO to UART2 before enabling this */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 5); /* COM2 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x2f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 3); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 5); /* COM2 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x2f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 3); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); #endif - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/asrock_775i65g.c b/SerialICE/mainboard/asrock_775i65g.c index 27d1c36..9870e45 100644 --- a/SerialICE/mainboard/asrock_775i65g.c +++ b/SerialICE/mainboard/asrock_775i65g.c @@ -19,7 +19,7 @@ const char boardname[] = "ASRock 775i65G"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" /* Hardware specific functions */ static void mainboard_set_ich5(void) @@ -39,15 +39,15 @@ static void mainboard_set_ich5(void) /* Winbond W83627HG */ static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Set the clock to 48MHz */ - pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0xc0); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x24, 0xc0); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/asrock_939a785gmh.c b/SerialICE/mainboard/asrock_939a785gmh.c index d44a50b..0c92a60 100644 --- a/SerialICE/mainboard/asrock_939a785gmh.c +++ b/SerialICE/mainboard/asrock_939a785gmh.c @@ -20,20 +20,20 @@ const char boardname[] = "Asrock 939a785gmh"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/asrock_p4i65gv.c b/SerialICE/mainboard/asrock_p4i65gv.c index ccb40ec..8cffca0 100644 --- a/SerialICE/mainboard/asrock_p4i65gv.c +++ b/SerialICE/mainboard/asrock_p4i65gv.c @@ -19,7 +19,7 @@ const char boardname[] = "ASRock P4i65GV"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" /* Hardware specific functions */ static void mainboard_set_ich5(void) @@ -39,15 +39,15 @@ static void mainboard_set_ich5(void) /* Winbond W83627HG */ static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Set the clock to 48MHz */ - pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0xc0); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x24, 0xc0); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/asus_f2a85-m.c b/SerialICE/mainboard/asus_f2a85-m.c index 53a75b6..af1b14e 100644 --- a/SerialICE/mainboard/asus_f2a85-m.c +++ b/SerialICE/mainboard/asus_f2a85-m.c @@ -20,25 +20,25 @@ const char boardname[] = "Asus F2A85-M"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" static void superio_init(void) { u8 byte; - pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT_2eh); /* Disable the watchdog. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7); - pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 7); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x72, 0x00); /* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT_2eh); } diff --git a/SerialICE/mainboard/asus_k8v-x.c b/SerialICE/mainboard/asus_k8v-x.c index df010c9..7e3ee5f 100644 --- a/SerialICE/mainboard/asus_k8v-x.c +++ b/SerialICE/mainboard/asus_k8v-x.c @@ -20,24 +20,24 @@ const char boardname[] = "ASUS K8V-X"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Disable the watchdog. */ -// pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7); -// pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00); +// pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 7); +// pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x72, 0x00); /* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/asus_m2v-mx_se.c b/SerialICE/mainboard/asus_m2v-mx_se.c index ab2a289..7d98739 100644 --- a/SerialICE/mainboard/asus_m2v-mx_se.c +++ b/SerialICE/mainboard/asus_m2v-mx_se.c @@ -20,24 +20,24 @@ const char boardname[] = "ASUS M2V-MX SE"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" static void superio_init(void) { - pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT_2eh); /* Disable the watchdog. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7); - pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 7); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x72, 0x00); /* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/asus_m4a77td-pro.c b/SerialICE/mainboard/asus_m4a77td-pro.c index b41c97d..2c9ab34 100644 --- a/SerialICE/mainboard/asus_m4a77td-pro.c +++ b/SerialICE/mainboard/asus_m4a77td-pro.c @@ -21,24 +21,24 @@ const char boardname[] = "ASUS M4A77TD-PRO"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" static void superio_init(void) { - pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT_2eh); /* Disable the watchdog. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7); - pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 7); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x72, 0x00); /* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/asus_p4p800-vm.c b/SerialICE/mainboard/asus_p4p800-vm.c index 9208870..8a59f7d 100644 --- a/SerialICE/mainboard/asus_p4p800-vm.c +++ b/SerialICE/mainboard/asus_p4p800-vm.c @@ -19,7 +19,7 @@ const char boardname[] = "ASUS P4P800-VM"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" /* Hardware specific functions */ static void mainboard_set_ich5(void) @@ -39,15 +39,15 @@ static void mainboard_set_ich5(void) /* Winbond W83627THF */ static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Set the clock to 48MHz */ - pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0x42); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x24, 0x42); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/commell_lv_672.c b/SerialICE/mainboard/commell_lv_672.c index 047bc9f..0c8d6cd 100644 --- a/SerialICE/mainboard/commell_lv_672.c +++ b/SerialICE/mainboard/commell_lv_672.c @@ -19,7 +19,7 @@ const char boardname[] = "Commell LV-672"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" /* Hardware specific functions */ static void southbridge_init(void) @@ -49,19 +49,19 @@ static void southbridge_init(void) static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Settings for Winbond W83627THF/THG */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 0); - pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0xc2); /* Select oscillator */ + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x24, 0xc2); /* Select oscillator */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/hp_dl165_g6.c b/SerialICE/mainboard/hp_dl165_g6.c index 745bf26..f1f70fe 100644 --- a/SerialICE/mainboard/hp_dl165_g6.c +++ b/SerialICE/mainboard/hp_dl165_g6.c @@ -21,9 +21,7 @@ const char boardname[] = "HP DL165 G6"; -#define SCH4307_CONFIG_PORT 0x162e -#define SUPERIO_CONFIG_PORT 0x2e -#define SUPERIO_SP1 2 +#include "superio.h" static void superio_init(void) { @@ -45,13 +43,13 @@ static void superio_init(void) pnp_exit_ext_func_mode(SCH4307_CONFIG_PORT); /* Enable the serial port. */ - outb(0x5a, SUPERIO_CONFIG_PORT); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, SUPERIO_SP1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); - outb(0xa5, SUPERIO_CONFIG_PORT); + outb(0x5a, SUPERIO_CONFIG_PORT_2eh); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, SUPERIO_SP1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); + outb(0xa5, SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/intel_d845gbv2.c b/SerialICE/mainboard/intel_d845gbv2.c index 6cbd703..aaf1cf8 100644 --- a/SerialICE/mainboard/intel_d845gbv2.c +++ b/SerialICE/mainboard/intel_d845gbv2.c @@ -19,7 +19,7 @@ const char boardname[] = "Intel D845GBV2"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" /* Hardware specific functions */ static void southbridge_init(void) @@ -39,16 +39,16 @@ static void southbridge_init(void) static void superio_init(void) { - pnp_enter_ext_func_mode_alt(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode_alt(SUPERIO_CONFIG_PORT_2eh); /* Settings for LPC47M172 with LD_NUM = 0. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 3); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 3); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/msi_ms6178.c b/SerialICE/mainboard/msi_ms6178.c index fd4af8f..639994f 100644 --- a/SerialICE/mainboard/msi_ms6178.c +++ b/SerialICE/mainboard/msi_ms6178.c @@ -30,7 +30,7 @@ const char boardname[] = "MSI MS6178"; #define TCO2_STS (TCOBASE + 0x06) #define TCO1_CNT (TCOBASE + 0x08) -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" static void southbridge_init(void) { @@ -53,16 +53,16 @@ static void southbridge_init(void) static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Set CLKSEL=1 to select 48 MHz (otherwise serial won't work). */ - pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0xc4); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x24, 0xc4); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); pnp_exit_ext_func_mode(0x2e); } diff --git a/SerialICE/mainboard/msi_ms7133.c b/SerialICE/mainboard/msi_ms7133.c index 1248f78..784a2b7 100644 --- a/SerialICE/mainboard/msi_ms7133.c +++ b/SerialICE/mainboard/msi_ms7133.c @@ -31,7 +31,7 @@ const char boardname[] = "MSI MS7133"; #define TCO2_STS (TCOBASE + 0x06) #define TCO1_CNT (TCOBASE + 0x08) -#define SUPERIO_CONFIG_PORT 0x4e +#include "superio.h" static void southbridge_init(void) { diff --git a/SerialICE/mainboard/televideo_tc7010.c b/SerialICE/mainboard/televideo_tc7010.c index a915387..5c92437 100644 --- a/SerialICE/mainboard/televideo_tc7010.c +++ b/SerialICE/mainboard/televideo_tc7010.c @@ -19,16 +19,17 @@ const char boardname[] = "Televideo TC7010"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" + #define PM_BASE 0xe8 static void superio_init(void) { /* Set base address of power management unit */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 8); - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, PM_BASE); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 8); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, PM_BASE); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); /* Use on-chip clock multiplier */ outb(0x03, PM_BASE); @@ -38,20 +39,20 @@ static void superio_init(void) while (!(inb(PM_BASE + 1) & 0x80)) ; /* Enable the serial ports. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 6); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 6); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); /* Set LDN 5 UART Mode */ - outb(0x21, SUPERIO_CONFIG_PORT); - outb(inb(SUPERIO_CONFIG_PORT + 1) | (1 << 3), SUPERIO_CONFIG_PORT + 1); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 5); /* COM2 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x2f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 3); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + outb(0x21, SUPERIO_CONFIG_PORT_2eh); + outb(inb(SUPERIO_CONFIG_PORT_2eh + 1) | (1 << 3), SUPERIO_CONFIG_PORT_2eh + 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 5); /* COM2 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x2f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 3); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); } static void chipset_init(void) diff --git a/SerialICE/mainboard/tyan_s2892.c b/SerialICE/mainboard/tyan_s2892.c index 043ebf7..bb4427a 100644 --- a/SerialICE/mainboard/tyan_s2892.c +++ b/SerialICE/mainboard/tyan_s2892.c @@ -20,8 +20,7 @@ const char boardname[] = "Tyan S2892"; -#define SUPERIO_CONFIG_PORT 0x2e -#define W83627HF_SP1 2 +#include "superio.h" static void sio_setup(void) { @@ -41,16 +40,16 @@ static void sio_setup(void) static void superio_init(void) { int i; - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, W83627HF_SP1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, CONFIG_SERIAL_PORT); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, W83627HF_SP1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, CONFIG_SERIAL_PORT); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/tyan_s2895.c b/SerialICE/mainboard/tyan_s2895.c index 8606bbe..edc4920 100644 --- a/SerialICE/mainboard/tyan_s2895.c +++ b/SerialICE/mainboard/tyan_s2895.c @@ -20,7 +20,6 @@ const char boardname[] = "Tyan S2895"; -#define SUPERIO_CONFIG_PORT 0x2e #define SUPERIO_GPIO_IO_BASE 0x400 #define LPC47B397_SP1 4 /* Com1 */ @@ -68,7 +67,7 @@ static void superio_init(void) dword |= (1<<16); pci_write_config32(PCI_ADDR(0, 1, 0, 0xa4), dword); - smsc_enable_serial(SUPERIO_CONFIG_PORT, LPC47B397_RT, SUPERIO_GPIO_IO_BASE); + smsc_enable_serial(SUPERIO_CONFIG_PORT_2eh, LPC47B397_RT, SUPERIO_GPIO_IO_BASE); value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77); value &= 0xbf; lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); @@ -77,7 +76,7 @@ static void superio_init(void) static void chipset_init(void) { superio_init(); - smsc_enable_serial(SUPERIO_CONFIG_PORT, LPC47B397_SP1, CONFIG_SERIAL_PORT); + smsc_enable_serial(SUPERIO_CONFIG_PORT_2eh, LPC47B397_SP1, CONFIG_SERIAL_PORT); __asm__ __volatile__("\ jmp skip\n\ .align 128\n\ diff --git a/SerialICE/mainboard/tyan_s2912.c b/SerialICE/mainboard/tyan_s2912.c index 77b5d29..9d74a18 100644 --- a/SerialICE/mainboard/tyan_s2912.c +++ b/SerialICE/mainboard/tyan_s2912.c @@ -20,22 +20,21 @@ const char boardname[] = "Tyan S2912"; -#define SUPERIO_CONFIG_PORT 0x2e -#define W83627HF_SP1 2 +#include "superio.h" static void superio_init(void) { int i; - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, W83627HF_SP1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, W83627HF_SP1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/mainboard/via_epia_m850.c b/SerialICE/mainboard/via_epia_m850.c index 55c2574..89c1335 100644 --- a/SerialICE/mainboard/via_epia_m850.c +++ b/SerialICE/mainboard/via_epia_m850.c @@ -19,7 +19,7 @@ const char boardname[] = "VIA EPIA M-850"; -#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" static inline void pnp_enter_conf_state(u16 port) { @@ -34,12 +34,12 @@ static inline void pnp_exit_conf_state(u16 port) static void superio_init(void) { - pnp_enter_conf_state(SUPERIO_CONFIG_PORT); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 0); - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x03f8); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); - pnp_exit_conf_state(SUPERIO_CONFIG_PORT); + pnp_enter_conf_state(SUPERIO_CONFIG_PORT_2eh); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x03f8); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); + pnp_exit_conf_state(SUPERIO_CONFIG_PORT_2eh); } static void chipset_init(void) diff --git a/SerialICE/superio.h b/SerialICE/superio.h new file mode 100644 index 0000000..9edca27 --- /dev/null +++ b/SerialICE/superio.h @@ -0,0 +1,6 @@ +#define SUPERIO_CONFIG_PORT_2eh 0x2e +#define SUPERIO_CONFIG_PORT_4eh 0x4e +#define W83627HF_SP1 2 + +#define SCH4307_CONFIG_PORT 0x162e +#define SUPERIO_SP1 2

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New patch to review for serialice: 815c50f SerialICE: C: clean up mainboard naming
by Idwer Vollering 26 Mar '13

26 Mar '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2910 -gerrit commit 815c50f1f36e21c972ded80c1e2440f69427683f Author: Idwer Vollering <vidwer(a)gmail.com> Date: Tue Mar 26 00:22:22 2013 +0100 SerialICE: C: clean up mainboard naming Clean up mainboard naming: shorten boardname[] by removing the spaces from the end and drop the predetermined string length. Change-Id: I5eef75612c128e1ac5c4513b8eabe44a6a7eb19a Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- SerialICE/mainboard/amd_serengeti-cheetah.c | 2 +- SerialICE/mainboard/aopen_dxpl-plus.c | 2 +- SerialICE/mainboard/asrock_775i65g.c | 2 +- SerialICE/mainboard/asrock_939a785gmh.c | 2 +- SerialICE/mainboard/asrock_p4i65gv.c | 2 +- SerialICE/mainboard/asus_f2a85-m.c | 2 +- SerialICE/mainboard/asus_k8v-x.c | 2 +- SerialICE/mainboard/asus_m2v-mx_se.c | 2 +- SerialICE/mainboard/asus_m4a77td-pro.c | 2 +- SerialICE/mainboard/asus_p2b.c | 2 +- SerialICE/mainboard/asus_p4p800-vm.c | 2 +- SerialICE/mainboard/commell_lv_672.c | 2 +- SerialICE/mainboard/dell_s1850.c | 2 +- SerialICE/mainboard/hp_dl165_g6.c | 2 +- SerialICE/mainboard/intel_d845gbv2.c | 2 +- SerialICE/mainboard/intel_d945gclf.c | 2 +- SerialICE/mainboard/kontron_986lcd-m.c | 2 +- SerialICE/mainboard/msi_ms6178.c | 2 +- SerialICE/mainboard/msi_ms7133.c | 2 +- SerialICE/mainboard/qemu-x86.c | 2 +- SerialICE/mainboard/rca_rm4100.c | 2 +- SerialICE/mainboard/roda_rk886ex.c | 2 +- SerialICE/mainboard/televideo_tc7010.c | 2 +- SerialICE/mainboard/thomson_ip1000.c | 2 +- SerialICE/mainboard/tyan_s2892.c | 2 +- SerialICE/mainboard/tyan_s2895.c | 2 +- SerialICE/mainboard/tyan_s2912.c | 2 +- SerialICE/mainboard/via_epia_m850.c | 2 +- SerialICE/mainboard/wyse_s50.c | 2 +- 29 files changed, 29 insertions(+), 29 deletions(-) diff --git a/SerialICE/mainboard/amd_serengeti-cheetah.c b/SerialICE/mainboard/amd_serengeti-cheetah.c index 78505ad..bd35711 100644 --- a/SerialICE/mainboard/amd_serengeti-cheetah.c +++ b/SerialICE/mainboard/amd_serengeti-cheetah.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -const char boardname[33]="AMD SERENGETI CHEETAH "; +const char boardname[] = "AMD SERENGETI CHEETAH"; #define SUPERIO_CONFIG_PORT 0x2e #define W83627HF_SP1 2 diff --git a/SerialICE/mainboard/aopen_dxpl-plus.c b/SerialICE/mainboard/aopen_dxpl-plus.c index d8c6bea..44cdb34 100644 --- a/SerialICE/mainboard/aopen_dxpl-plus.c +++ b/SerialICE/mainboard/aopen_dxpl-plus.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -const char boardname[33]="AOpen DXPL Plus "; +const char boardname[] = "AOpen DXPL Plus"; #define SUPERIO_CONFIG_PORT 0x2e diff --git a/SerialICE/mainboard/asrock_775i65g.c b/SerialICE/mainboard/asrock_775i65g.c index 4d1512f..27d1c36 100644 --- a/SerialICE/mainboard/asrock_775i65g.c +++ b/SerialICE/mainboard/asrock_775i65g.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -const char boardname[33]="ASRock 775i65G "; +const char boardname[] = "ASRock 775i65G"; #define SUPERIO_CONFIG_PORT 0x2e diff --git a/SerialICE/mainboard/asrock_939a785gmh.c b/SerialICE/mainboard/asrock_939a785gmh.c index 6f8c9be..d44a50b 100644 --- a/SerialICE/mainboard/asrock_939a785gmh.c +++ b/SerialICE/mainboard/asrock_939a785gmh.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -const char boardname[33]="Asrock 939a785gmh "; +const char boardname[] = "Asrock 939a785gmh"; #define SUPERIO_CONFIG_PORT 0x2e diff --git a/SerialICE/mainboard/asrock_p4i65gv.c b/SerialICE/mainboard/asrock_p4i65gv.c index d0f46f4..ccb40ec 100644 --- a/SerialICE/mainboard/asrock_p4i65gv.c +++ b/SerialICE/mainboard/asrock_p4i65gv.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -const char boardname[33]="ASRock P4i65GV "; +const char boardname[] = "ASRock P4i65GV"; #define SUPERIO_CONFIG_PORT 0x2e diff --git a/SerialICE/mainboard/asus_f2a85-m.c b/SerialICE/mainboard/asus_f2a85-m.c index 8eebde3..53a75b6 100644 --- a/SerialICE/mainboard/asus_f2a85-m.c +++ b/SerialICE/mainboard/asus_f2a85-m.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -const char boardname[33]="Asus F2A85-M "; +const char boardname[] = "Asus F2A85-M"; #define SUPERIO_CONFIG_PORT 0x2e diff --git a/SerialICE/mainboard/asus_k8v-x.c b/SerialICE/mainboard/asus_k8v-x.c index bc3dbe9..df010c9 100644 --- a/SerialICE/mainboard/asus_k8v-x.c +++ b/SerialICE/mainboard/asus_k8v-x.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -const char boardname[33]="ASUS K8V-X "; +const char boardname[] = "ASUS K8V-X"; #define SUPERIO_CONFIG_PORT 0x2e diff --git a/SerialICE/mainboard/asus_m2v-mx_se.c b/SerialICE/mainboard/asus_m2v-mx_se.c index cd694fd..ab2a289 100644 --- a/SerialICE/mainboard/asus_m2v-mx_se.c +++ b/SerialICE/mainboard/asus_m2v-mx_se.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -const char boardname[33]="ASUS M2V-MX SE "; +const char boardname[] = "ASUS M2V-MX SE"; #define SUPERIO_CONFIG_PORT 0x2e diff --git a/SerialICE/mainboard/asus_m4a77td-pro.c b/SerialICE/mainboard/asus_m4a77td-pro.c index 6b91f80..b41c97d 100644 --- a/SerialICE/mainboard/asus_m4a77td-pro.c +++ b/SerialICE/mainboard/asus_m4a77td-pro.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -const char boardname[33]="ASUS M4A77TD-PRO "; +const char boardname[] = "ASUS M4A77TD-PRO"; #define SUPERIO_CONFIG_PORT 0x2e diff --git a/SerialICE/mainboard/asus_p2b.c b/SerialICE/mainboard/asus_p2b.c index c93045a..9d97349 100644 --- a/SerialICE/mainboard/asus_p2b.c +++ b/SerialICE/mainboard/asus_p2b.c @@ -19,7 +19,7 @@ /* This is a chipset init file for the ASUS P2B mainboard. */ -const char boardname[33]="ASUS P2B "; +const char boardname[] = "ASUS P2B"; #define PNP_PORT 0x3f0 diff --git a/SerialICE/mainboard/asus_p4p800-vm.c b/SerialICE/mainboard/asus_p4p800-vm.c index 4109bc0..9208870 100644 --- a/SerialICE/mainboard/asus_p4p800-vm.c +++ b/SerialICE/mainboard/asus_p4p800-vm.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -const char boardname[33]="ASUS P4P800-VM "; +const char boardname[] = "ASUS P4P800-VM"; #define SUPERIO_CONFIG_PORT 0x2e diff --git a/SerialICE/mainboard/commell_lv_672.c b/SerialICE/mainboard/commell_lv_672.c index 8f81e8e..047bc9f 100644 --- a/SerialICE/mainboard/commell_lv_672.c +++ b/SerialICE/mainboard/commell_lv_672.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -const char boardname[33]="Commell LV-672 "; +const char boardname[] = "Commell LV-672"; #define SUPERIO_CONFIG_PORT 0x2e diff --git a/SerialICE/mainboard/dell_s1850.c b/SerialICE/mainboard/dell_s1850.c index b970650..8fd0937 100644 --- a/SerialICE/mainboard/dell_s1850.c +++ b/SerialICE/mainboard/dell_s1850.c @@ -19,7 +19,7 @@ /* This is a chipset init file for the Dell S1850 */ -const char boardname[33]="DELL S1850 "; +const char boardname[] = "DELL S1850"; /* Hardware specific functions */ static void mainboard_set_ich5(void) diff --git a/SerialICE/mainboard/hp_dl165_g6.c b/SerialICE/mainboard/hp_dl165_g6.c index 3301ad5..745bf26 100644 --- a/SerialICE/mainboard/hp_dl165_g6.c +++ b/SerialICE/mainboard/hp_dl165_g6.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -const char boardname[33]="HP DL165 G6 "; +const char boardname[] = "HP DL165 G6"; #define SCH4307_CONFIG_PORT 0x162e #define SUPERIO_CONFIG_PORT 0x2e diff --git a/SerialICE/mainboard/intel_d845gbv2.c b/SerialICE/mainboard/intel_d845gbv2.c index 3588c33..6cbd703 100644 --- a/SerialICE/mainboard/intel_d845gbv2.c +++ b/SerialICE/mainboard/intel_d845gbv2.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -const char boardname[33]="Intel D845GBV2 "; +const char boardname[] = "Intel D845GBV2"; #define SUPERIO_CONFIG_PORT 0x2e diff --git a/SerialICE/mainboard/intel_d945gclf.c b/SerialICE/mainboard/intel_d945gclf.c index 85d4d82..dd35d9c 100644 --- a/SerialICE/mainboard/intel_d945gclf.c +++ b/SerialICE/mainboard/intel_d945gclf.c @@ -20,7 +20,7 @@ /* This is a chipset init file for the Intel D945GCLF mainboard */ #include "config.h" -const char boardname[33]="Intel D945GCLF "; +const char boardname[] = "Intel D945GCLF"; /* Hardware specific functions */ diff --git a/SerialICE/mainboard/kontron_986lcd-m.c b/SerialICE/mainboard/kontron_986lcd-m.c index 62d8c46..ca42287 100644 --- a/SerialICE/mainboard/kontron_986lcd-m.c +++ b/SerialICE/mainboard/kontron_986lcd-m.c @@ -19,7 +19,7 @@ /* This is a chipset init file for the Kontron 986LCD-M mainboard */ -const char boardname[33]="Kontron 986LCD-M "; +const char boardname[] = "Kontron 986LCD-M"; static void chipset_init(void) { diff --git a/SerialICE/mainboard/msi_ms6178.c b/SerialICE/mainboard/msi_ms6178.c index f0a505a..fd4af8f 100644 --- a/SerialICE/mainboard/msi_ms6178.c +++ b/SerialICE/mainboard/msi_ms6178.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -const char boardname[33]="MSI MS6178 "; +const char boardname[] = "MSI MS6178"; #define PMBASE 0x40 #define COM_DEC 0xe0 diff --git a/SerialICE/mainboard/msi_ms7133.c b/SerialICE/mainboard/msi_ms7133.c index fc7e753..1248f78 100644 --- a/SerialICE/mainboard/msi_ms7133.c +++ b/SerialICE/mainboard/msi_ms7133.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -const char boardname[33]="MSI MS7133 "; +const char boardname[] = "MSI MS7133"; #define PMBASE 0x40 #define COM_DEC 0x80 diff --git a/SerialICE/mainboard/qemu-x86.c b/SerialICE/mainboard/qemu-x86.c index 0177fad..876063c 100644 --- a/SerialICE/mainboard/qemu-x86.c +++ b/SerialICE/mainboard/qemu-x86.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -const char boardname[33]="QEMU X86 "; +const char boardname[] = "QEMU X86"; static void southbridge_init(void) { diff --git a/SerialICE/mainboard/rca_rm4100.c b/SerialICE/mainboard/rca_rm4100.c index 81ff089..5551af3 100644 --- a/SerialICE/mainboard/rca_rm4100.c +++ b/SerialICE/mainboard/rca_rm4100.c @@ -19,7 +19,7 @@ /* This is a chipset init file for the RCA RM4100 mainboard */ -const char boardname[33]="RCA RM4100 "; +const char boardname[] = "RCA RM4100"; /* Hardware specific functions */ diff --git a/SerialICE/mainboard/roda_rk886ex.c b/SerialICE/mainboard/roda_rk886ex.c index 048f30d..ab60b8e 100644 --- a/SerialICE/mainboard/roda_rk886ex.c +++ b/SerialICE/mainboard/roda_rk886ex.c @@ -22,7 +22,7 @@ */ #include "config.h" -const char boardname[33]="Roda RK886EX (Rocky III+) "; +const char boardname[] = "Roda RK886EX (Rocky III+)"; /* Hardware specific functions */ diff --git a/SerialICE/mainboard/televideo_tc7010.c b/SerialICE/mainboard/televideo_tc7010.c index 9c79e05..a915387 100644 --- a/SerialICE/mainboard/televideo_tc7010.c +++ b/SerialICE/mainboard/televideo_tc7010.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -const char boardname[33] = "Televideo TC7010 "; +const char boardname[] = "Televideo TC7010"; #define SUPERIO_CONFIG_PORT 0x2e #define PM_BASE 0xe8 diff --git a/SerialICE/mainboard/thomson_ip1000.c b/SerialICE/mainboard/thomson_ip1000.c index d558e42..ce54ff2 100644 --- a/SerialICE/mainboard/thomson_ip1000.c +++ b/SerialICE/mainboard/thomson_ip1000.c @@ -19,7 +19,7 @@ /* This is a chipset init file for the THOMSON IP1000 mainboard */ -const char boardname[33]="THOMSON IP1000 "; +const char boardname[] = "THOMSON IP1000"; /* Hardware specific functions */ diff --git a/SerialICE/mainboard/tyan_s2892.c b/SerialICE/mainboard/tyan_s2892.c index d009165..043ebf7 100644 --- a/SerialICE/mainboard/tyan_s2892.c +++ b/SerialICE/mainboard/tyan_s2892.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -const char boardname[33]="Tyan S2892 "; +const char boardname[] = "Tyan S2892"; #define SUPERIO_CONFIG_PORT 0x2e #define W83627HF_SP1 2 diff --git a/SerialICE/mainboard/tyan_s2895.c b/SerialICE/mainboard/tyan_s2895.c index 3f06ba6..8606bbe 100644 --- a/SerialICE/mainboard/tyan_s2895.c +++ b/SerialICE/mainboard/tyan_s2895.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -const char boardname[33]="Tyan S2895 "; +const char boardname[] = "Tyan S2895"; #define SUPERIO_CONFIG_PORT 0x2e #define SUPERIO_GPIO_IO_BASE 0x400 diff --git a/SerialICE/mainboard/tyan_s2912.c b/SerialICE/mainboard/tyan_s2912.c index ad7184a..77b5d29 100644 --- a/SerialICE/mainboard/tyan_s2912.c +++ b/SerialICE/mainboard/tyan_s2912.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -const char boardname[33]="Tyan S2912 "; +const char boardname[] = "Tyan S2912"; #define SUPERIO_CONFIG_PORT 0x2e #define W83627HF_SP1 2 diff --git a/SerialICE/mainboard/via_epia_m850.c b/SerialICE/mainboard/via_epia_m850.c index 6d041bd..55c2574 100644 --- a/SerialICE/mainboard/via_epia_m850.c +++ b/SerialICE/mainboard/via_epia_m850.c @@ -17,7 +17,7 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -const char boardname[33]="VIA EPIA M-850 "; +const char boardname[] = "VIA EPIA M-850"; #define SUPERIO_CONFIG_PORT 0x2e diff --git a/SerialICE/mainboard/wyse_s50.c b/SerialICE/mainboard/wyse_s50.c index d23d5a9..cd0ebe1 100644 --- a/SerialICE/mainboard/wyse_s50.c +++ b/SerialICE/mainboard/wyse_s50.c @@ -19,7 +19,7 @@ /* This is a chipset init file for the WYSE S50 thin client. */ -const char boardname[33]="WYSE S50 "; +const char boardname[] = "WYSE S50"; #define GPIO_IO_BASE 0x6100

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Patch set updated for serialice: 843ca08 Add support for Intel D945GNT
by Stefan Tauner 25 Mar '13

25 Mar '13

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1578 -gerrit commit 843ca0888da9daf07c5425771a6bc3fa46ad766e Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Mon Mar 25 20:45:39 2013 +0100 Add support for Intel D945GNT This is based on the patch from Beata dalHagen, see http://serialice.com/pipermail/serialice/2012-May/000372.html This version has only been compile tested. To share the code added by this and following patches of similar boards the file originally added for the D945GCLF is renamed to be more generic. Also, the Super I/O options get passed to the init function depending on the configured board. Change-Id: Ia4058d0f73f8357b97d7c0fe1868d9a289c4e2f7 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- SerialICE/Kconfig | 5 +- SerialICE/mainboard/intel_d945gclf.c | 92 ------------------------------- SerialICE/mainboard/intel_d94x.c | 102 +++++++++++++++++++++++++++++++++++ 3 files changed, 106 insertions(+), 93 deletions(-) diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig index 3d5fa9c..fc56696 100644 --- a/SerialICE/Kconfig +++ b/SerialICE/Kconfig @@ -42,6 +42,9 @@ config BOARD_RODA_RK886EX config BOARD_INTEL_D945GCLF bool "Intel D945GCLF" +config BOARD_INTEL_D945GNT + bool "Intel D945GNT" + config BOARD_DELL_S1850 bool "Dell PowerEdge S1850" @@ -132,7 +135,7 @@ config BOARD_INIT default "amd_serengeti-cheetah.c" if BOARD_AMD_SERENGETI_CHEETAH default "kontron_986lcd-m.c" if BOARD_KONTRON_986LCD_M default "roda_rk886ex.c" if BOARD_RODA_RK886EX - default "intel_d945gclf.c" if BOARD_INTEL_D945GCLF + default "intel_d94x.c" if BOARD_INTEL_D945GCLF || BOARD_INTEL_D945GNT default "dell_s1850.c" if BOARD_DELL_S1850 default "asus_f2a85-m.c" if BOARD_ASUS_F2A85_M default "asus_m2v-mx_se.c" if BOARD_ASUS_M2V_MX_SE diff --git a/SerialICE/mainboard/intel_d945gclf.c b/SerialICE/mainboard/intel_d945gclf.c deleted file mode 100644 index 85d4d82..0000000 --- a/SerialICE/mainboard/intel_d945gclf.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * SerialICE - * - * Copyright (C) 2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This is a chipset init file for the Intel D945GCLF mainboard */ -#include "config.h" - -const char boardname[33]="Intel D945GCLF "; - -/* Hardware specific functions */ - -#define RCBA 0xfed1c000 -#define GCS 0x3410 -#define RCBA32(x) *((volatile u32 *)(RCBA + x)) - -static void southbridge_init(void) -{ - u16 reg16; - u32 reg32; - - // Set up RCBA - pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1); - -#if defined(CONFIG_POST_LPC) - // port80 writes go to LPC: - reg32 = RCBA32(GCS); - reg32 = reg32 & ~0x04; - RCBA32(GCS) = reg32; - outb(0x23, 0x80); -#endif - - // Enable Serial IRQ - pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x64), 0xd0); - // Set COM1 decode range - pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x80), 0x0010); - // Enable COM1 - pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x82), 0x140d); - // Enable SIO PM Events at 0x680 - pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x84), 0x007c0681); - - // Disable watchdog -#define PMBASE 0x500 -#define TCOBASE (PMBASE + 0x60) - pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x40), PMBASE | 1); - pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x44), 0x80); - reg16 = inw(TCOBASE + 0x08); - reg16 |= (1 << 11); - outw(reg16, TCOBASE + 0x08); - outw(0x0008, TCOBASE + 0x04); - outw(0x0002, TCOBASE + 0x06); -} - -static void superio_init(void) -{ - pnp_enter_ext_func_mode_alt(0x2e); - - pnp_set_logical_device(0x2e, 4); // COM-A - pnp_set_enable(0x2e, 0); - pnp_set_iobase0(0x2e, 0x3f8); - pnp_set_irq0(0x2e, 4); - pnp_set_enable(0x2e, 1); - - pnp_set_logical_device(0x2e, 10); // PM - pnp_set_enable(0x2e, 0); - pnp_set_iobase0(0x2e, 0x680); - pnp_set_irq0(0x2e, 3); - pnp_set_enable(0x2e, 1); - - pnp_exit_ext_func_mode(0x2e); -} - -static void chipset_init(void) -{ - southbridge_init(); - superio_init(); -} - diff --git a/SerialICE/mainboard/intel_d94x.c b/SerialICE/mainboard/intel_d94x.c new file mode 100644 index 0000000..f3fd0ea --- /dev/null +++ b/SerialICE/mainboard/intel_d94x.c @@ -0,0 +1,102 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is a chipset init file for the Intel D945GCLF/D945GNT mainboards */ +#include "config.h" + +#if defined(CONFIG_BOARD_INTEL_D945GCLF) +const char boardname[33]="Intel D945GCLF "; +#elif defined(CONFIG_BOARD_INTEL_D945GNT) +const char boardname[33]="Intel D945GNT "; +#else +#error "Unsupported board" +#endif + +/* Hardware specific functions */ + +#define RCBA 0xfed1c000 +#define GCS 0x3410 +#define RCBA32(x) *((volatile u32 *)(RCBA + x)) + +static void southbridge_init(void) +{ + u16 reg16; + u32 reg32; + + // Set up RCBA + pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1); + +#if defined(CONFIG_POST_LPC) + // port80 writes go to LPC: + reg32 = RCBA32(GCS); + reg32 = reg32 & ~0x04; + RCBA32(GCS) = reg32; + outb(0x23, 0x80); +#endif + + // Enable Serial IRQ + pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x64), 0xd0); + // Set COM1 decode range + pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x80), 0x0010); + // Enable COM1 + pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x82), 0x140d); + // Enable SIO PM Events at 0x680 + pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x84), 0x007c0681); + + // Disable watchdog +#define PMBASE 0x500 +#define TCOBASE (PMBASE + 0x60) + pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x40), PMBASE | 1); + pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x44), 0x80); + reg16 = inw(TCOBASE + 0x08); + reg16 |= (1 << 11); + outw(reg16, TCOBASE + 0x08); + outw(0x0008, TCOBASE + 0x04); + outw(0x0002, TCOBASE + 0x06); +} + +static void superio_init(u8 cfg_port, u8 com_port, u8 pm) +{ + pnp_enter_ext_func_mode_alt(cfg_port); + + pnp_set_logical_device(cfg_port, com_port); + pnp_set_enable(cfg_port, 0); + pnp_set_iobase0(cfg_port, 0x3f8); + pnp_set_irq0(cfg_port, 4); + pnp_set_enable(cfg_port, 1); + + pnp_set_logical_device(cfg_port, pm); + pnp_set_enable(cfg_port, 0); + pnp_set_iobase0(cfg_port, 0x680); + pnp_set_irq0(cfg_port, 3); + pnp_set_enable(cfg_port, 1); + + pnp_exit_ext_func_mode(cfg_port); +} + +static void chipset_init(void) +{ + southbridge_init(); +#if defined(CONFIG_BOARD_INTEL_D945GCLF) + superio_init(0x2e, 4, 10); +#elif defined(CONFIG_BOARD_INTEL_D945GNT) + superio_init(0x2e, 3, 4); // LPC47M182 +#endif +} +

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Patch set updated for serialice: 71b2429 Add support for Intel D946GZIS
by Stefan Tauner 25 Mar '13

25 Mar '13

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1579 -gerrit commit 71b2429b9abdde499aab361e2f2205b59fcb3f26 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Sun Oct 14 07:28:44 2012 +0200 Add support for Intel D946GZIS Change-Id: I48056df9cef6b87987c2588c53b043794f900b83 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- SerialICE/Kconfig | 5 ++++- SerialICE/mainboard/intel_d94x.c | 16 +++++++++++----- 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig index fc56696..089ac13 100644 --- a/SerialICE/Kconfig +++ b/SerialICE/Kconfig @@ -45,6 +45,9 @@ config BOARD_INTEL_D945GCLF config BOARD_INTEL_D945GNT bool "Intel D945GNT" +config BOARD_INTEL_D946GZIS + bool "Intel D946GZIS" + config BOARD_DELL_S1850 bool "Dell PowerEdge S1850" @@ -135,7 +138,7 @@ config BOARD_INIT default "amd_serengeti-cheetah.c" if BOARD_AMD_SERENGETI_CHEETAH default "kontron_986lcd-m.c" if BOARD_KONTRON_986LCD_M default "roda_rk886ex.c" if BOARD_RODA_RK886EX - default "intel_d94x.c" if BOARD_INTEL_D945GCLF || BOARD_INTEL_D945GNT + default "intel_d94x.c" if BOARD_INTEL_D945GCLF || BOARD_INTEL_D945GNT || BOARD_INTEL_D946GZIS default "dell_s1850.c" if BOARD_DELL_S1850 default "asus_f2a85-m.c" if BOARD_ASUS_F2A85_M default "asus_m2v-mx_se.c" if BOARD_ASUS_M2V_MX_SE diff --git a/SerialICE/mainboard/intel_d94x.c b/SerialICE/mainboard/intel_d94x.c index f3fd0ea..02eb701 100644 --- a/SerialICE/mainboard/intel_d94x.c +++ b/SerialICE/mainboard/intel_d94x.c @@ -24,6 +24,8 @@ const char boardname[33]="Intel D945GCLF "; #elif defined(CONFIG_BOARD_INTEL_D945GNT) const char boardname[33]="Intel D945GNT "; +#elif defined(CONFIG_BOARD_INTEL_D946GZIS) +const char boardname[33]="Intel D946GZIS "; #else #error "Unsupported board" #endif @@ -81,11 +83,13 @@ static void superio_init(u8 cfg_port, u8 com_port, u8 pm) pnp_set_irq0(cfg_port, 4); pnp_set_enable(cfg_port, 1); - pnp_set_logical_device(cfg_port, pm); - pnp_set_enable(cfg_port, 0); - pnp_set_iobase0(cfg_port, 0x680); - pnp_set_irq0(cfg_port, 3); - pnp_set_enable(cfg_port, 1); + if (pm != 0) { + pnp_set_logical_device(cfg_port, pm); + pnp_set_enable(cfg_port, 0); + pnp_set_iobase0(cfg_port, 0x680); + pnp_set_irq0(cfg_port, 3); + pnp_set_enable(cfg_port, 1); + } pnp_exit_ext_func_mode(cfg_port); } @@ -97,6 +101,8 @@ static void chipset_init(void) superio_init(0x2e, 4, 10); #elif defined(CONFIG_BOARD_INTEL_D945GNT) superio_init(0x2e, 3, 4); // LPC47M182 +#elif defined(CONFIG_BOARD_INTEL_D946GZIS) + superio_init(0x2e, 3, 0); // PC8374 #endif }

1 0

Patch set updated for serialice: 3e01696 Add support for Intel D946GZIS
by Stefan Tauner 25 Mar '13

25 Mar '13

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1579 -gerrit commit 3e0169695cf588349882821ebcdec68d519a299f Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Sun Oct 14 07:28:44 2012 +0200 Add support for Intel D946GZIS Change-Id: I48056df9cef6b87987c2588c53b043794f900b83 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- SerialICE/Kconfig | 5 ++++- SerialICE/mainboard/intel_d94x.c | 16 +++++++++++----- 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig index fc56696..089ac13 100644 --- a/SerialICE/Kconfig +++ b/SerialICE/Kconfig @@ -45,6 +45,9 @@ config BOARD_INTEL_D945GCLF config BOARD_INTEL_D945GNT bool "Intel D945GNT" +config BOARD_INTEL_D946GZIS + bool "Intel D946GZIS" + config BOARD_DELL_S1850 bool "Dell PowerEdge S1850" @@ -135,7 +138,7 @@ config BOARD_INIT default "amd_serengeti-cheetah.c" if BOARD_AMD_SERENGETI_CHEETAH default "kontron_986lcd-m.c" if BOARD_KONTRON_986LCD_M default "roda_rk886ex.c" if BOARD_RODA_RK886EX - default "intel_d94x.c" if BOARD_INTEL_D945GCLF || BOARD_INTEL_D945GNT + default "intel_d94x.c" if BOARD_INTEL_D945GCLF || BOARD_INTEL_D945GNT || BOARD_INTEL_D946GZIS default "dell_s1850.c" if BOARD_DELL_S1850 default "asus_f2a85-m.c" if BOARD_ASUS_F2A85_M default "asus_m2v-mx_se.c" if BOARD_ASUS_M2V_MX_SE diff --git a/SerialICE/mainboard/intel_d94x.c b/SerialICE/mainboard/intel_d94x.c index f3fd0ea..02eb701 100644 --- a/SerialICE/mainboard/intel_d94x.c +++ b/SerialICE/mainboard/intel_d94x.c @@ -24,6 +24,8 @@ const char boardname[33]="Intel D945GCLF "; #elif defined(CONFIG_BOARD_INTEL_D945GNT) const char boardname[33]="Intel D945GNT "; +#elif defined(CONFIG_BOARD_INTEL_D946GZIS) +const char boardname[33]="Intel D946GZIS "; #else #error "Unsupported board" #endif @@ -81,11 +83,13 @@ static void superio_init(u8 cfg_port, u8 com_port, u8 pm) pnp_set_irq0(cfg_port, 4); pnp_set_enable(cfg_port, 1); - pnp_set_logical_device(cfg_port, pm); - pnp_set_enable(cfg_port, 0); - pnp_set_iobase0(cfg_port, 0x680); - pnp_set_irq0(cfg_port, 3); - pnp_set_enable(cfg_port, 1); + if (pm != 0) { + pnp_set_logical_device(cfg_port, pm); + pnp_set_enable(cfg_port, 0); + pnp_set_iobase0(cfg_port, 0x680); + pnp_set_irq0(cfg_port, 3); + pnp_set_enable(cfg_port, 1); + } pnp_exit_ext_func_mode(cfg_port); } @@ -97,6 +101,8 @@ static void chipset_init(void) superio_init(0x2e, 4, 10); #elif defined(CONFIG_BOARD_INTEL_D945GNT) superio_init(0x2e, 3, 4); // LPC47M182 +#elif defined(CONFIG_BOARD_INTEL_D946GZIS) + superio_init(0x2e, 3, 0); // PC8374 #endif }

1 0

Patch set updated for serialice: 9f23af0 Add support for Intel D945GNT
by Stefan Tauner 25 Mar '13

25 Mar '13

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1578 -gerrit commit 9f23af0cea64e81707d13926b750faeb03a4fd1c Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Mon Mar 25 20:45:39 2013 +0100 Add support for Intel D945GNT This is based on the patch from Beata dalHagen, see http://serialice.com/pipermail/serialice/2012-May/000372.html This version has only been compile tested. It seems like we should use kconfig more, but i don't know this stuff good enough yet. Still better than copying the whole file :) Change-Id: Ia4058d0f73f8357b97d7c0fe1868d9a289c4e2f7 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- SerialICE/Kconfig | 5 +- SerialICE/mainboard/intel_d945gclf.c | 92 ------------------------------- SerialICE/mainboard/intel_d94x.c | 102 +++++++++++++++++++++++++++++++++++ 3 files changed, 106 insertions(+), 93 deletions(-) diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig index 3d5fa9c..fc56696 100644 --- a/SerialICE/Kconfig +++ b/SerialICE/Kconfig @@ -42,6 +42,9 @@ config BOARD_RODA_RK886EX config BOARD_INTEL_D945GCLF bool "Intel D945GCLF" +config BOARD_INTEL_D945GNT + bool "Intel D945GNT" + config BOARD_DELL_S1850 bool "Dell PowerEdge S1850" @@ -132,7 +135,7 @@ config BOARD_INIT default "amd_serengeti-cheetah.c" if BOARD_AMD_SERENGETI_CHEETAH default "kontron_986lcd-m.c" if BOARD_KONTRON_986LCD_M default "roda_rk886ex.c" if BOARD_RODA_RK886EX - default "intel_d945gclf.c" if BOARD_INTEL_D945GCLF + default "intel_d94x.c" if BOARD_INTEL_D945GCLF || BOARD_INTEL_D945GNT default "dell_s1850.c" if BOARD_DELL_S1850 default "asus_f2a85-m.c" if BOARD_ASUS_F2A85_M default "asus_m2v-mx_se.c" if BOARD_ASUS_M2V_MX_SE diff --git a/SerialICE/mainboard/intel_d945gclf.c b/SerialICE/mainboard/intel_d945gclf.c deleted file mode 100644 index 85d4d82..0000000 --- a/SerialICE/mainboard/intel_d945gclf.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * SerialICE - * - * Copyright (C) 2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This is a chipset init file for the Intel D945GCLF mainboard */ -#include "config.h" - -const char boardname[33]="Intel D945GCLF "; - -/* Hardware specific functions */ - -#define RCBA 0xfed1c000 -#define GCS 0x3410 -#define RCBA32(x) *((volatile u32 *)(RCBA + x)) - -static void southbridge_init(void) -{ - u16 reg16; - u32 reg32; - - // Set up RCBA - pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1); - -#if defined(CONFIG_POST_LPC) - // port80 writes go to LPC: - reg32 = RCBA32(GCS); - reg32 = reg32 & ~0x04; - RCBA32(GCS) = reg32; - outb(0x23, 0x80); -#endif - - // Enable Serial IRQ - pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x64), 0xd0); - // Set COM1 decode range - pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x80), 0x0010); - // Enable COM1 - pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x82), 0x140d); - // Enable SIO PM Events at 0x680 - pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x84), 0x007c0681); - - // Disable watchdog -#define PMBASE 0x500 -#define TCOBASE (PMBASE + 0x60) - pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x40), PMBASE | 1); - pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x44), 0x80); - reg16 = inw(TCOBASE + 0x08); - reg16 |= (1 << 11); - outw(reg16, TCOBASE + 0x08); - outw(0x0008, TCOBASE + 0x04); - outw(0x0002, TCOBASE + 0x06); -} - -static void superio_init(void) -{ - pnp_enter_ext_func_mode_alt(0x2e); - - pnp_set_logical_device(0x2e, 4); // COM-A - pnp_set_enable(0x2e, 0); - pnp_set_iobase0(0x2e, 0x3f8); - pnp_set_irq0(0x2e, 4); - pnp_set_enable(0x2e, 1); - - pnp_set_logical_device(0x2e, 10); // PM - pnp_set_enable(0x2e, 0); - pnp_set_iobase0(0x2e, 0x680); - pnp_set_irq0(0x2e, 3); - pnp_set_enable(0x2e, 1); - - pnp_exit_ext_func_mode(0x2e); -} - -static void chipset_init(void) -{ - southbridge_init(); - superio_init(); -} - diff --git a/SerialICE/mainboard/intel_d94x.c b/SerialICE/mainboard/intel_d94x.c new file mode 100644 index 0000000..f3fd0ea --- /dev/null +++ b/SerialICE/mainboard/intel_d94x.c @@ -0,0 +1,102 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is a chipset init file for the Intel D945GCLF/D945GNT mainboards */ +#include "config.h" + +#if defined(CONFIG_BOARD_INTEL_D945GCLF) +const char boardname[33]="Intel D945GCLF "; +#elif defined(CONFIG_BOARD_INTEL_D945GNT) +const char boardname[33]="Intel D945GNT "; +#else +#error "Unsupported board" +#endif + +/* Hardware specific functions */ + +#define RCBA 0xfed1c000 +#define GCS 0x3410 +#define RCBA32(x) *((volatile u32 *)(RCBA + x)) + +static void southbridge_init(void) +{ + u16 reg16; + u32 reg32; + + // Set up RCBA + pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1); + +#if defined(CONFIG_POST_LPC) + // port80 writes go to LPC: + reg32 = RCBA32(GCS); + reg32 = reg32 & ~0x04; + RCBA32(GCS) = reg32; + outb(0x23, 0x80); +#endif + + // Enable Serial IRQ + pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x64), 0xd0); + // Set COM1 decode range + pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x80), 0x0010); + // Enable COM1 + pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x82), 0x140d); + // Enable SIO PM Events at 0x680 + pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x84), 0x007c0681); + + // Disable watchdog +#define PMBASE 0x500 +#define TCOBASE (PMBASE + 0x60) + pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x40), PMBASE | 1); + pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x44), 0x80); + reg16 = inw(TCOBASE + 0x08); + reg16 |= (1 << 11); + outw(reg16, TCOBASE + 0x08); + outw(0x0008, TCOBASE + 0x04); + outw(0x0002, TCOBASE + 0x06); +} + +static void superio_init(u8 cfg_port, u8 com_port, u8 pm) +{ + pnp_enter_ext_func_mode_alt(cfg_port); + + pnp_set_logical_device(cfg_port, com_port); + pnp_set_enable(cfg_port, 0); + pnp_set_iobase0(cfg_port, 0x3f8); + pnp_set_irq0(cfg_port, 4); + pnp_set_enable(cfg_port, 1); + + pnp_set_logical_device(cfg_port, pm); + pnp_set_enable(cfg_port, 0); + pnp_set_iobase0(cfg_port, 0x680); + pnp_set_irq0(cfg_port, 3); + pnp_set_enable(cfg_port, 1); + + pnp_exit_ext_func_mode(cfg_port); +} + +static void chipset_init(void) +{ + southbridge_init(); +#if defined(CONFIG_BOARD_INTEL_D945GCLF) + superio_init(0x2e, 4, 10); +#elif defined(CONFIG_BOARD_INTEL_D945GNT) + superio_init(0x2e, 3, 4); // LPC47M182 +#endif +} +

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SerialICE March 2013