Patch set updated for serialice: 3e01696 Add support for Intel D946GZIS

[Stefan Tauner]

Stefan Tauner ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1579

-gerrit

commit 3e0169695cf588349882821ebcdec68d519a299f
Author: Stefan Tauner <[e-mail]>
Date:   Sun Oct 14 07:28:44 2012 +0200

    Add support for Intel D946GZIS
    
    Change-Id: I48056df9cef6b87987c2588c53b043794f900b83
    Signed-off-by: Stefan Tauner <[e-mail]>
---
 SerialICE/Kconfig                |  5 ++++-
 SerialICE/mainboard/intel_d94x.c | 16 +++++++++++-----
 2 files changed, 15 insertions(+), 6 deletions(-)

diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig
index fc56696..089ac13 100644
--- a/SerialICE/Kconfig
+++ b/SerialICE/Kconfig
@@ -45,6 +45,9 @@ config BOARD_INTEL_D945GCLF
 config BOARD_INTEL_D945GNT
 	bool "Intel D945GNT"
 
+config BOARD_INTEL_D946GZIS
+	bool "Intel D946GZIS"
+
 config BOARD_DELL_S1850
 	bool "Dell PowerEdge S1850"
 
@@ -135,7 +138,7 @@ config BOARD_INIT
 	default "amd_serengeti-cheetah.c" if BOARD_AMD_SERENGETI_CHEETAH
 	default "kontron_986lcd-m.c" if BOARD_KONTRON_986LCD_M
 	default "roda_rk886ex.c" if BOARD_RODA_RK886EX
-	default "intel_d94x.c" if BOARD_INTEL_D945GCLF || BOARD_INTEL_D945GNT
+	default "intel_d94x.c" if BOARD_INTEL_D945GCLF || BOARD_INTEL_D945GNT || BOARD_INTEL_D946GZIS
 	default "dell_s1850.c" if BOARD_DELL_S1850
 	default "asus_f2a85-m.c" if BOARD_ASUS_F2A85_M
 	default "asus_m2v-mx_se.c" if BOARD_ASUS_M2V_MX_SE
diff --git a/SerialICE/mainboard/intel_d94x.c b/SerialICE/mainboard/intel_d94x.c
index f3fd0ea..02eb701 100644
--- a/SerialICE/mainboard/intel_d94x.c
+++ b/SerialICE/mainboard/intel_d94x.c
@@ -24,6 +24,8 @@
 const char boardname[33]="Intel D945GCLF                  ";
 #elif defined(CONFIG_BOARD_INTEL_D945GNT)
 const char boardname[33]="Intel D945GNT                   ";
+#elif defined(CONFIG_BOARD_INTEL_D946GZIS)
+const char boardname[33]="Intel D946GZIS                  ";
 #else
 #error "Unsupported board"
 #endif
@@ -81,11 +83,13 @@ static void superio_init(u8 cfg_port, u8 com_port, u8 pm)
 	pnp_set_irq0(cfg_port, 4);
 	pnp_set_enable(cfg_port, 1);
 
-	pnp_set_logical_device(cfg_port, pm);
-	pnp_set_enable(cfg_port, 0);
-	pnp_set_iobase0(cfg_port, 0x680);
-	pnp_set_irq0(cfg_port, 3);
-	pnp_set_enable(cfg_port, 1);
+	if (pm != 0) {
+		pnp_set_logical_device(cfg_port, pm);
+		pnp_set_enable(cfg_port, 0);
+		pnp_set_iobase0(cfg_port, 0x680);
+		pnp_set_irq0(cfg_port, 3);
+		pnp_set_enable(cfg_port, 1);
+	}
 
 	pnp_exit_ext_func_mode(cfg_port);
 }
@@ -97,6 +101,8 @@ static void chipset_init(void)
 	superio_init(0x2e, 4, 10);
 #elif defined(CONFIG_BOARD_INTEL_D945GNT)
 	superio_init(0x2e, 3, 4); // LPC47M182
+#elif defined(CONFIG_BOARD_INTEL_D946GZIS)
+	superio_init(0x2e, 3, 0); // PC8374
 #endif
 }