Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/835
-gerrit
commit fe9b4cf949649a6e161eb7e215efd2336051729c Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Sat Mar 31 14:03:58 2012 +0300
Add mainboard AOpen DXPL Plus
Change-Id: Ic23e99f50e1d1acddccd90f3791c872c3e22023a Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- SerialICE/Kconfig | 4 ++ SerialICE/mainboard/aopen_dxpl-plus.c | 70 +++++++++++++++++++++++++++++++++ 2 files changed, 74 insertions(+), 0 deletions(-)
diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig index ac53de1..b645309 100644 --- a/SerialICE/Kconfig +++ b/SerialICE/Kconfig @@ -102,6 +102,9 @@ config BOARD_ASROCK_P4I65GV config BOARD_ASUS_P4P800_VM bool "ASUS P4P800-VM"
+config BOARD_AOPEN_DXPL_PLUS + bool "AOpen DXPL Plus" + endchoice
config BOARD_INIT @@ -128,6 +131,7 @@ config BOARD_INIT default "wyse_s50.c" if BOARD_WYSE_S50 default "asrock_p4i65gv.c" if BOARD_ASROCK_P4I65GV default "asus_p4p800-vm.c" if BOARD_ASUS_P4P800_VM + default "aopen_dxpl-plus.c" if BOARD_AOPEN_DXPL_PLUS
config SOUTHBRIDGE_INIT string diff --git a/SerialICE/mainboard/aopen_dxpl-plus.c b/SerialICE/mainboard/aopen_dxpl-plus.c new file mode 100644 index 0000000..d8c6bea --- /dev/null +++ b/SerialICE/mainboard/aopen_dxpl-plus.c @@ -0,0 +1,70 @@ +/* + * SerialICE + * + * Copyright (C) 2012 Kyösti Mälkki kyosti.malkki@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +const char boardname[33]="AOpen DXPL Plus "; + +#define SUPERIO_CONFIG_PORT 0x2e + +/* Hardware specific functions */ +static void southbridge_init(void) +{ + /* Set NO_REBOOT flag */ + pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0xd4), 0x02); + + /* Set SuperIO GPIO decode range. */ + pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0xe4), 0x0e01); + + /* Select COM1 COM2 I/O ranges. */ + pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0xe0), 0x10); + + /* Enable COM1, COM2, KBD, SIO config registers 0x2e. */ + pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0xe6), 0x1403); + + /* Enable Serial IRQ */ + pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x64), 0xd0); +} + +static void superio_init(void) +{ + pnp_enter_ext_func_mode_alt(SUPERIO_CONFIG_PORT); + + pnp_set_logical_device(SUPERIO_CONFIG_PORT, 4); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + +#if 0 + /* Must route GPIO to UART2 before enabling this */ + pnp_set_logical_device(SUPERIO_CONFIG_PORT, 5); /* COM2 */ + pnp_set_enable(SUPERIO_CONFIG_PORT, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x2f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT, 3); + pnp_set_enable(SUPERIO_CONFIG_PORT, 1); +#endif + + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); +} + +static void chipset_init(void) +{ + southbridge_init(); + superio_init(); +} +