Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5214
-gerrit
commit 10238c6f0c7fca5903211c9ed10dff094753f9c1 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Fri Feb 14 01:03:34 2014 +1100
SerialICE/mainboard: Add initial Jetway NF81-T56N-LF support.
Add support for Jetway NF81-T56N-LF mainboard and its Super I/O.
Change-Id: Idef372f1f2654a93dbd1023101fd0bb15fef32f8 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- SerialICE/Kconfig | 8 +++++- SerialICE/mainboard/jetway_nf81_t56n_lf.c | 27 ++++++++++++++++++++ SerialICE/superio/fintek-f71869ad.c | 41 +++++++++++++++++++++++++++++++ 3 files changed, 75 insertions(+), 1 deletion(-)
diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig index 00933b2..328950e 100644 --- a/SerialICE/Kconfig +++ b/SerialICE/Kconfig @@ -130,6 +130,10 @@ config BOARD_ASROCK_775I65G config BOARD_COMMELL_LV_672 bool "Commell LV-672"
+config BOARD_JETWAY_NF81_T56N_LF + bool "Jetway NF81-T56N-LF" + select BUILD_XMMSTACK + endchoice
config BOARD_INIT @@ -163,15 +167,17 @@ config BOARD_INIT default "intel_d845gbv2.c" if BOARD_INTEL_D845GBV2 default "asrock_775i65g.c" if BOARD_ASROCK_775I65G default "commell_lv_672.c" if BOARD_COMMELL_LV_672 + default "jetway_nf81_t56n_lf.c" if BOARD_JETWAY_NF81_T56N_LF
config SOUTHBRIDGE_INIT string default "southbridge/intel-ich7.c" if BOARD_KONTRON_986LCD_M - default "southbridge/amd-sbxxx.c" if BOARD_ASUS_F2A85_M + default "southbridge/amd-sbxxx.c" if BOARD_ASUS_F2A85_M || BOARD_JETWAY_NF81_T56N_LF
config SUPERIO_INIT string default "superio/winbond-w83627thg.c" if BOARD_KONTRON_986LCD_M + default "superio/fintek-f71869ad.c" if BOARD_JETWAY_NF81_T56N_LF
choice prompt "ROM size" diff --git a/SerialICE/mainboard/jetway_nf81_t56n_lf.c b/SerialICE/mainboard/jetway_nf81_t56n_lf.c new file mode 100644 index 0000000..7b704a0 --- /dev/null +++ b/SerialICE/mainboard/jetway_nf81_t56n_lf.c @@ -0,0 +1,27 @@ +/* + * SerialICE + * + * Copyright (C) 2014 Edward O'Callaghan eocallaghan@alterapraxis.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +const char boardname[33]="Jetway NF81-T56N-LF "; + +static void chipset_init(void) +{ + southbridge_init(); + sbxxx_enable_48mhzout(); + superio_init(); +} diff --git a/SerialICE/superio/fintek-f71869ad.c b/SerialICE/superio/fintek-f71869ad.c new file mode 100644 index 0000000..c04389b --- /dev/null +++ b/SerialICE/superio/fintek-f71869ad.c @@ -0,0 +1,41 @@ +/* + * SerialICE + * + * Copyright (C) 2014 Edward O'Callaghan eocallaghan@alterapraxis.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define SUPERIO_CONFIG_PORT 0x2e +#define UART_IO_PORT 0x3F8 +#define UART_IRQ_ADDR 4 + +static void superio_init(void) +{ + u8 byte; + pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + + /* Disable the watchdog. */ + pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7); + pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00); + + /* Enable the serial port. */ + pnp_set_logical_device(SUPERIO_CONFIG_PORT, 1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT, UART_IO_PORT); + pnp_set_irq0(SUPERIO_CONFIG_PORT, UART_IRQ_ADDR); + pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + + pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT); +}